Control and Status Registers

In document DMA2281 (Page 26-36)

4. The Three Serial Interfaces

4.3. The Burst Bus

4.3.1. Control and Status Registers

Note: Not–used bits must be set to zero for control (receive) registers and are don’t care for status (transmit) registers.

Table 4–1: 16–bit DMA control registers, instructions from CCU to DMA Address Label Bit No. Default

Setting

VCO adjustment (range –128...+127) alignment of the 20.25 MHz VCO VCO select

1 = VCO3 selected 2 = VCO2 selected 4 = VCO1 selected

disable PLL output (pin 25, 26) if (DI1 . or . DI2 . or DI3) then PLL output = high impedance 23

saturation V adjust 0: gain = 0 63: gain = 2 saturation U adjust 0: gain = 0

luma delay adjust (range 0...30) resolution: 20.25 MHz clock luma contrast switch luma contrast adjust 0: gain = 0

disable sync outputs (pins 50–53, 58–60) 0 = enabled

1 = high impedance

disable clamping output (pin 48) 0 = enabled

1 = high impedance

disable luma/chroma output (pin 21–24, 27–38) 0 = enabled

1 = high impedance non interlace 0 = interlace on 1 = interlace off PLL open 0 = PLL closed 1 = PLL opened stand alone operation 0 = digital insertion 1 = stand alone

chroma output multiplex 0 = 4 x 4 multiplex 1 = 2 x 8 multiplex

Table 4–1, continued

Address Label Bit No. Default Setting

disable gray code converter input signal (pin 39–45) 0 = gray coded

1 = binary coded

525 lines standard select 0 = 625 lines standard selected 1 = 252 lines standard selected luma filter selection

chroma filter selection 202

horizontal blank delay adjust (pin 50–52) resolution: 10.125 MHz clock

comp. sync delay adjust (pin 53) resolution: 10.125 MHz clock 203

channel 1 packet address channel 1 enable

channel 1 mode update channel 1 mode

194 see register 203 channel 2

195 see register 203 channel 3

196 see register 203 channel 4

197

subframe select

SFS = sample number of the first bit in the selected subframe

examples:

DRS = 1, first subframe SFS = 7 DRS = 1, second subframe SFS = 106 DRS = 0, first subframe SFS = 14 chip definition

0 = DMA 2280 1 = DMA 2285 auto mode 0 = auto mode off

1 = sound coding in packet header data rate select

0 = 10.125 Mbits/s D2–MAC

1 = 20.25 Mbits/s C/D–MAC

198

energy dispersal compensation (–8...+7) clamping loop gain

chip select

0 = IM bus of DMA 2280 active 1 = IM bus of DMA 2285 active

linear/nicam

hamming/parity protection high/medium quality stereo/mono

Table 4–1, continued

Address Label Bit No. Default Setting

PLL select

0 = D/D2 MAC PLL 1 = CMAC PLL enable filter 2 0 for C/D MAC 1 for D2 MAC slicer select 0 for D2–MAC 1 for D–MAC 2 for C–MAC PLL gain

0 = maximal gain 3 = minimal gain full channel data

0: DBW is gated (pin 52) 1: DBW is active all the time burst phase

0 = with DMA 2285 1 = only DMA 2280

slice level (range –128...+127) for D/D2–MAC

for C–MAC 204

S bus enable

data group type selection packet 0 reset

1: select first byte in packet 0 buffer (first byte = data group type DGT) packet 0 clear

1: enable packet 0 buffer to store next packet 0

disable S bus outputs (pins 64, 66, 67) 0 = enabled

1 = high impedance audio clock switch (pin 65) 0: audio clock = main clock 1: audio clock = 18.432 MHz audio clock free running

0 = audio clock locked to main clock 1 = audio clock free running

channel 1 enable channel 2 enable channel 3 enable channel 4 enable

Table 4–1, continued

Address Label Bit No. Default Setting

Typical Value

Function

205 205 205 205 205 205 205 205 205 205 205 205 205 205 205 205

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

for test only for test only for test only for test only for test only for test only enable PDAT input for test only

disable error concealment for test only

enable BDAT input for test only for test only

disable luma/chroma interpolation filters for test only

for test only

Table 4–2: 16–bit DMA status registers, information from DMA to CCU Address Label Bit No. Function

206

206

206

206

206

206

206

206

BER

VER

C1S

C2S

C3S

C4S

P0S

SYNC

0–7

8–9

10

11

12

13

14

15

bit error rate

number of erroneous bits detected by the golay decoder within the 82 packet headers of one frame

version

0: C/D/D2–MAC Decoder 1: D2–MAC Decoder 2: D–MAC Decoder 3: C/D2–MAC Decoder

status of sound signal selected by C1A 0: sound signal is inactive or interrupted 1: sound signal is present

status of sound signal selected by C2A 0: sound signal is inactive or interrupted 1: sound signal is present

status of sound signal selected by C3A 0: sound signal is inactive or interrupted 1: sound signal is present

status of sound signal selected by C4A 0: sound signal is inactive or interrupted 1: sound signal is present

status of packet 0 buffer

0: packet 0 selected by DGT not received 1: packet 0 received

status of frame sync word detector

0: frame sync word not detected within 8 frames 1: frame sync word detected

207 207

WL BL

0–7 8–15

white level measured in line 624 (typical value = 240) black level measured in line 624 (typical value = 16) 208

208 208 208

C1L C2L C3L C4L

0–3 4–7 8–11 12–15

coding law of sound signal selected by C1A coding law of sound signal selected by C2A coding law of sound signal selected by C3A coding law of sound signal selected by C4A L = 0: companded law

1: linear law

H = 0: first level protection 1: second level protection HQ = 0: medium quality sound

1: high quality sound S = 0: monophonic sound

1: stereophonic sound 209

209

PSL PSH

0–7 8–15

packet 0 syndrom low byte packet 0 syndrom high byte

PSL + PSH = 0: packet 0 received without error PSL + PSH > 0: packet 0 received with error 210

210

PDL PDH

0–7 8–15

packet 0 data low byte packet 0 data high byte

Bits must be set to zero for write registers (W) and Bits not used in DMA 2280 registers, but in other devices

Table 4–3: DMA control and status registers, graphical overview

Addr. Bit No.

VCOS VCOA

VCO Adjustment

0 0

SAV

Saturation V

40 0

CT

Luma Contrast 32

LD

CFI

Chroma Filter 0

MSB LSB

Luma Delay

DGC

Composite Sync. Delay

64 0 0

BD

Blank Delay 64

L

S HQ H

C1M

Channel Mode

C1U

Mode 0 Update

C1A

Channel Packet Addres 100

C2A

Channel Packet Address 100

C3A

Channel Packet Address 100

C4A

Channel Packet Address 100

SFS

Subframe Select 7

FCDFull

0

DI3 DI2 DI1

0 0 0 0 0 1 0

SAU

Saturation U

28 0 0 0

Luma Filter

C1E

Channel Mode

C2U

Channel Mode

C3U

Channel Mode

C4U

Slice Level 0

0 0

EDC

Energy Dispersal 2

Data Group Type 0

SBE

S_Bus Enable 3 0

0 0

206 BER

Bit Error Rate

R

207 WL

White Level

R

208

C4L

Coding Law CH4

R

209 PSL

Packet 0 Syndrom Low Byte

R

210 PDL

Packet 0 Data Low Byte

R

SYNC P0S C49 C39 C29 C19

Status

BL

Black Level

L

S HQ H S HQ H L S HQ H L S HQ H L

C3L

Coding Law CH3

C2L

Coding Law CH2

C1L

Coding Law CH1

PSH

Packet 0 Syndrom High Byte

PDH

Packet 0 Data High Byte

Table 4–4: VCU control and status registers, graphical overview

Addr. Bit No.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

16

17

18

19

27

BR

Brightness 128

DR

White Drive Red 127

CG

Cutoff Voltage Green 127

DG

CB

Cutoff Voltage Blue 127

MSB LSB

White Drive Green

0

RGBC

Ext. RGB Contrast 32 No.

Direct.

W

W

W

W

W

CR

Cutoff Voltage Red 127

127

SCS

SECAM

1 Chroma

Sync

NIE

Noise

0 Invert.

Enable

BCR

Beam Current 0 Reduction

VI2

Video 0 Input 2

COB

Code Bits 7

YDA

Luma 1 Adder

BLD

Blank 1 Disable

YDASLuma

0 Adder

Shift

DGD

Double

1 Gain Disable

BEN

Bit 1 Enlarg.

DB

White Drive Blue 127

Bits must be set to zero for write registers (W) and are don’t care for read registers (R)

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In document DMA2281 (Page 26-36)

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