TABLE 7-1. MACSI Memory Map (BMAC Registers)(Continued)
Address Register Name Access Rules Reset
Value
Read Write
028 Internal Event Latch Register (IELR) Always Conditional 00
029 – 02B Reserved N/A N/A
02C Exception Status Register (ESR) Always Conditional 00
02D Exception Mask Register (EMR) Always Always 00
02E Interrupt Condition Register (ICR) Always Data Ignored 00
02F Interrupt Mask Register (IMR) Always Always 00
030 – 03F Reserved N/A N/A
040 – 07F MAC Parameters Stop Mode Stop Mode NA
080 – 0BF Counters/Timers Always Stop Mode NA
0C0-0FF Reserved N/A N/A
*eContains a MAC Revision code.
NAeNot altered upon reset.
N/AeNot Applicable
Table 7-2. MACSI Memory Map (BSI Registers)
Address Register Name Access Rules Reset
Value
Read Write
100 System Interface Mode Register 0 (SIMR0) Always Always 00
101 System Interface Mode Register 1 (SIMR1) Always Always 00
102 Pointer RAM Control and Address Register (PCAR) Always Always NA
103 Mailbox Address Register (MBAR) Always Always ²
104 Master Attention Register (MAR) Always Data Ignored 00
105 Master Notify Register (MNR) Always Always 00
106 State Attention Register (STAR) Always Conditional 07
107 State Notify Register (STNR) Always Always 00
108 Service Attention Register (SAR) Always Conditional 0F
109 Service Notify Register (SNR) Always Always 00
10A No Space Attention Register (NSAR) Always Conditional FF
10B No Space Notify Register (NSNR) Always Always 00
10C Limit Address Register (LAR) Always Always NA
10D Limit Data Register (LDR) Always Always NA
10E Request Attention Register (RAR) Always Conditional 00
10F Request Notify Register (RNR) Always Always 00
110 Request Channel 0 Configuration Register 0 (R0CR0) Always Always NA
111 Request Channel 1 Configuration Register 0 (R1CR0) Always Always NA
112 Request Channel 0 Expected Frame Status Register (R0EFSR) Always Always NA 113 Request Channel 1 Expected Frame Status Register (R1EFSR)
Obsolete
Always Always NA7.0 Control Information
(Continued)Table 7-2. MACSI Memory Map (BSI Registers)
Address Register Name Access Rules Reset
Value
Read Write
114 Indicate Attention Register (IAR) Always Conditional 00
115 Indicate Notify Register (INR) Always Always 00
116 Indicate Threshold Register (ITR) Always INSTOP Mode NA
or EXCe1 Only
117 Indicate Mode Configuration Register (IMCR) Always INSTOP Mode NA
Only
118 Indicate Copy Configuration Register (ICCR) Always Always NA
119 Indicate Header Length Register (IHLR) Always INSTOP Mode NA
or EXCe1 Only
11A Address Configuration Register (ACR) Always Always 00
11B Request Channel 0 Configuration Register 1 (R0CR1) Always Always 00
11C Request Channel 1 Configuration Register 1 (R1CR1) Always Always 00
11D – 11E Reserved N/A N/A
11F System Interface Compare Register (SICMP) Always Always NA
120 – 1FF Reserved N/A N/A
² eInitialized to a System Interface Revision code upon reset. The System Interface Revision code remains until it is overwritten by the host.
NAeNot altered upon reset.
N/AeNot Applicable
The MAC Control Information Address Space is divided into 4 groups as shown in Table 7-3. An information summary is given for each group followed by a detailed description of all registers.
# MAC Operation Registers (Table 7-4)
# MAC Event Registers (Table 7-5)
# MAC Parameters (Table 7-6)
# MAC Counters/Timers (Table 7-7)
The System Interface Operation registers are accessed di-rectly via the Control Bus. Limit RAM Registers are ac-cessed indirectly via the Control Bus using the Limit RAM Data and Limit RAM Address Registers. The Pointer RAM Registers are accessed indirectly via the Control Bus and
ABus using the Pointer RAM Address and Control Register, the Mailbox Address Register, and a mailbox location in ABus memory. Descriptors are fetched (or written) by the MACSI device across the ABus.
# System Interface Registers (Table 7-8) 7.2 CONVENTIONS
When referring to multi-byte fields, byte 0 is always the most significant byte. When referring to bits within a byte, bit (7) is the most significant bit and bit (0) is the least significant bit.
When referring to the contents of a byte, the most signifi-cant bit is always referred to first. When referring to a bit within a byte the notation registerÐname.bitÐname is used. For example, MCMR0.RUN references the RUN bit in MAC Mode Register 0.
Obsolete
7.0 Control Information
(Continued)TABLE 7-3. MAC Control Information Address Space Address
Description Read Write
Range Conditions Conditions
000 – 007 Operation Registers Always (Note 2) Always (Note 2) 008 – 02F Event Registers Always (Note 2) Always (cond) (Note 2) 030 – 03F Reserved N/A (Note 4) N/A (Note 4) 040 – 07F MAC Parameters Stop Mode Stop Mode
(Notes 1, 3) (Notes 1, 3) 080-0BF Counters/Timers Always Stop Mode (Note 1) 0C0-0FF Reserved N/A (Note 4) N/A (Note 4) Note 1:An attempt to access a currently inaccessible MAC Control location because of the current mode or because it is a reserved address space will cause a command error (bit CCE of the Exception Status Register is set to One).
Note 2:Read and write accesses to reserved locations within the Operation and Event Address ranges of the MAC Control Information Space cause a command error (bit CCE of the Exception Status Register is set to One).
Note 3:The MAC Parameter RAM is also accessible when conditions a, b and c are true. Other-wise accesses will cause a command error (bit CCE of the Exception Status Register is set to One) and the access will not be performed.
a) The MAC Transmitter is in state T0 or T1 or T3;
b) Option.ITCe1 and Option.IRRe1 c) Function.BCNe0 and Function.CLMe0
Note 4:Reserved bits in registers are always read as 0 and are not writable.
TABLE 7-4. MAC Operation Registers
Addr Name D7 D6 D5 D4 D3 D2 D1 D0 Read Write
000 MCMR0 DIAG ILB RES RES PIP MRP CBP RUN Always Always
001 Option ITC EMIND IFCS IRPT IRR ITR ELA ESA Always Always
002 Function RES RES RES CLM BCN MCRST RES MARST Always Always
003 – 004 Reserved RES RES RES RES RES RES RES RES N/A N/A
005 MCMR2 RES RES RES AFIE LLC MCE SMT MCE RES BOSEL Always Always
006 Reserved RES RES RES RES RES RES RES RES N/A N/A
007 MCRev REV(7 – 0) Always Ignored
Note 1:Attempts to access reserved locations within the MAC Operation Registers will result in Command Rejects (ESR.CCE set to ONE).
Note 2:On Master Reset, all MAC Operation Registers are set to Zero except the Revision Register.
Obsolete
7.0 Control Information
(Continued)TABLE 7-5. MAC Event Registers
Addr Name D7 D6 D5 D4 D3 D2 D1 D0 Read Write
008 MCCMP MCCMP(7 – 0) Always Always
009 – 00B Reserved RES RES RES RES RES RES RES RES N/A N/A
00C CRS0 RFLG RS2 RS1 RS0 RES RTS2 RTS1 RTS0 Always Ignored
00D Reserved RES RES RES RES RES RES RES RES N/A N/A
00E CTS0 ROP TS2 TS1 TS0 TTS3 TTS2 TTS1 TTS0 Always Ignored
00F Reserved RES RES RES RES RES RES RES RES N/A N/A
010 RELR0 RES DUP ADD PINV OTR MAC CLMR BCNR RNOP ROP Always Conditional
011 REMR0 RES DUP ADD PINV OTR MAC CLMR BCNR RNOP ROP Always Always
012 RELR1 LOCLM HICLM MYCLM RES RES RES MYBCN OTRBCN Always Conditional
013 REMR1 LOCLM HICLM MYCLM RES RES RES MYBCN OTRBCN Always Always
014 TELR0 RLVD TKPASS TKCAPT CBERR DUPTKR TRTEXP TVXEXP ENTRMD Always Conditional
015 TEMR0 RLVD TKPASS TKCAPT CBERR DUPTKR TRTEXP TVXEXP ENTRMD Always Always
016 – 017 Reserved RES RES RES RES RES RES RES RES N/A N/A
018 CILR RES TK RCVD FR TRX FR NCOP FR COP FR LST FREI FR RCV Always Conditional
019 CIMR RES TK RCVD FR TRX FR NCOP FR COP FR LST FREI FR RCV Always Always
01A – 01B Reserved RES RES RES RES RES RES RES RES N/A N/A
01C COLR RES TK RCVD FR TRX FR NCOP FR COP FR LST FREI FR RCV Always Conditional
01D COMR RES TK RCVD FR TRX FR NCOP FR COP FR LST FREI FR RCV Always Always
01E – 027 Reserved RES RES RES RES RES RES RES RES N/A N/A
028 IELR RES RES RES RES TSM ERR RSM ERR RES MPE Always Conditional
029 – 02B Reserved RES RES RES RES RES RES RES RES N/A N/A
02C ESR CWI CCE CPE RES RES RES RES PPE Always Conditional
02D EMR ZERO CCE CPE RES RES RES RES PPE Always Always
02E ICR ESE IERR RES RES COE CIE TTE RNG Always Ignored
02F IMR ESE IERR RES RES COE CIE TTE RNG Always Always
030 – 03F Reserved RES RES RES RES RES RES RES RES N/A N/A
Note 1:Attempts to access reserved locations within the MAC Event Registers will result in Command Rejects (ESR.CCE set to ONE).
Note 2:Bits in the conditional write registers are only written when the corresponding bit in the Compare Register is equal to the bit to be overwritten.
Note 3:On Master Reset all Event Registers are reset to Zero.