jump; and software interrupt capabilities. These instructions redirect program flow by changing the Program Counter.
The unconditional jump instructions support both relative in
struction addressing, the (JuMP instruction), and absolute instruction addressing, (the Long JuMP instruction), using the following addressing modes: Immediate, Register, Abso
lute, and Indexed. Table 2-10 lists the unconditional jump instructions and their variations.
The conditional jump instructions support both relative in
struction addressing and absolute instruction addressing us
ing the Immediate and Absolute addressing modes. The conditional relative jump instruction tests flags in the Condi
tion Code Register, (CCR), and the Transceiver Status Register, {TSRj. Two possible syntaxes are supported for the conditional relative jump instruction; see Table 2-11.
Table 2-12 lists the various flags “ f” that the conditional JMP instruction can test and Table 2-13 lists the various conditions “ cc” that the Jcc instruction can test for. Keep in
TABLE 2-8. Shift and Rotate Instructions
Note: "b " = the number of bit shifts/rotates to perform.
TABLE 2-9. Comparison Instructions Syntax Instruction Operation Addressing Mode CMP rs, n
BIT rs, n
register - n register & n
Limited Register Limited Register Note: & = logical AND operation
TABLE 2-10. Unconditional Jump Instructions
Syntax Instruction Operation Operand Range Addressing Mode
JMP n PC + n (sign extended) —► PC -1 2 8 , +127 Immediate
JMP Rs PC + Rs (sign extended) —*• PC -1 2 8 , +127 Register
LJMP nn nn —> PC 0, 64k Absolute
UMP [lr] lr —> PC 0, 64k Indexed
Note: PC = Program Counter; contents initially points to instruction following jump.
On the other hand, the conditional absolute jump instruc
tion, LJMP, can test any bit in any currently active CPU reg
ister. Table 2-14 shows the conditional long jump instruction syntax.
JMP Z,NS,SKIP.IT ;If [Z]=0 goto SKIP.IT
-or-JNZ SKIP.IT ;If [Z]=0 goto SKIP.IT FIGURE 2-5. Coding Examples of Equivalent
Conditional Jump Instructions
2.0 CPU Description
(Continued)TABLE 2-11. Conditional Relative Jump Instruction
Syntax Instruction Operation Operand Range Addressing Mode
JMP f,s,n If the flag “ f” is in the state “ s”
then PC + n (sign extended) —> PC
-1 2 8 , +127 Immediate
Jcc n If the condition “cc” is met
then PC + n (sign extended) —> PC
-1 2 8 , +127 Immediate
Note: PC = Program Counter; contents initially points to instruction following jump.
TABLE 2-12. “f” Flags
“f”(Binary) Flag Flag Name Register Containing Flag
000 z Zero (CCRj
001 c Carry [CCRj
010 V Overflow (CCRj
011 N Negative (CCRj
100 RA Receiver Active (TSR)
101 RE Receiver Error (TSR)
110 DAV Data Available (TSR)
111 TFF Transmitter FIFO Full (TSR)
TABLE 2-13. “cc” Conditions Tested
“cc” Field Condition Tested for Flag “f ”s Condition
Z Zero [Z] = 1
NZ Not Zero [Z] = 0
EQ Equal [Z] = 1
NEQ Not Equal [Z] = 0
C Carry [C] = 1
NC No Carry [C] = 0
V Overflow [V] = 1
NV No Overflow [V] = 0
N Negative [N] = 1
P Positive [N] = 0
RA Receiver Active [RA] = 1
NRA Not Receiver Active [RA] = 0
RE Receiver Error [RE] = 1
NRE No Receiver Error [RE] = 0
DA Data Available [DAV] = 1
NDA No Data Available [DAV] = 0
TFF Transmitter FIFO FULL [TFF] = 1
NTFF Transmitter FI FO Not Full [TFF] = 0
TABLE 2-14. Conditional Absolute Jump Instruction
Syntax Instruction Operation Operand Range Addressing Mode
LJMP Rs,p,s,nn If the bit of register “ Rs” in 0, 64k Register, Absolute
position “ p” is in the state “ s”
then nn —* PC Note: PC = Program Counter
mind that the Jcc instruction is just an optional syntax for the conditional JMP instruction.
The example in Figure 2-5 demonstrates two possible ways to code the conditional relative jump instruction when test
ing for a false [Z] flag in (CCRj. In the example, assume that the symbol “ Z” equals “ 000” binary, that the symbol
“ NS” equals “ 0” binary, and that the symbol “ SKIP.IT”
points to the desired instruction with which to begin execu
tion if [Z] is false.
P 8 3 4 4 B
D P 8 3 4 4 B
The BCP also has a specialized relative jump instruction called relative Jump with Rotate and Mask on source regis
ter, JRMK. This instruction facilitates the decoding of regis
ter fields often involved in communications processing.
JRMK does this by rotating and masking a copy of its regis
ter operand to form a signed program counter displacement which usually points into a jump table. Table 2-15 shows the syntax and operation of the JRMK instruction.
JRMK’s masking, (setting to zero), the least significant bit of the displacement allows the construction of a jump table using either one or two word instructions; for instance, a table of JMP and/or LJMP instructions, respectively. The example in Figure 2-6 demonstrates the JRMK instruction decoding the address frame of the 3299 Terminal Multiplex
2.0 CPU Description
(Continued)er protocol which is located in the Receive/Transmit Regis
ter, {R TR [4-2]j.
The BCP has two unconditional call instructions; CALL, which supports relative instruction addressing and LCALL, (Long CALL), which supports absolute instruction address
ing. These instructions push the following information onto the CPU’s internal Address Stack: the address of the next instruction; the status of the Global Interrupt Enable flag, [GIE]; the status of the ALU flags [Z], [C], [N], and [V]; and the status of which register banks are currently active. Table 2-16 lists the two unconditional call instructions. Note that the Address Stack is only twelve positions deep; therefore, the BCP allows twelve levels of nested subroutine invoca
tions, (this includes both interrupts and calls).
TABLE 2-15. JRMK Instruction
Syntax Instruction Operation Displacement
Range Addressing Mode JRMK Rs, b, m (a) Rotate a copy of register “ Rs” “ b” bits to the right.
(b) Mask the most significant “ m” bits and the least significant bit of the above result.
(c) PC + resulting displacement (sign extended) —> PC.
-1 2 8 , +126 Register
Note: PC = Program Counter; contents initially points to instruction following jump.
Example Code
JRMK RTR,1,4 {decode terminal address
LJMP ADDR.O {jump to device handler #0
LJMP ADDR.l {jump to device handler #1
LJMP ADDR.7 {jump to device handler #7
Instruction Execution JRMK Displacement Register Contents
(a) Copy (RTR) into JRMK’s displacement register: X X X A2 A1 A0 y y
(b) Rotate displacement register 1 bit to the right: y X X X A2 A1 A0 y
(c) AND result with “ 00001110” binary mask: 0 0 0 0 A2 A1 A0 0
(d) Sign extend resulting displacement and add it to the program counter, (PC).
If the bits A2 A1 AO equal “ 0 0 1 ” binary then + 2 is added to the Program Counter;
(i.e., PC + 2 - > PC).
(e) Execute the instruction pointed to by the PC, which in this example is:
LJMP ADDR.1
FIGURE 2-6. JRMK Instruction Example
TABLE 2-16. Unconditional Call Instructions
Syntax Instruction Operation Operand
Range Addressing Mode CALL n PC & [GIE] & ALU flags & reg. bank selection —*■ Address Stack
PC + n (sign extended) —> PC
-12 8 , +127 Immediate
LCALL , nn PC & [GIE] & ALU flags & reg. bank selection —► Address Stack nn —> PC
0 ,64k Absolute
Note: PC = Program Counter; contents initially points to instruction following call.
[GIE] '=" Global Interrupt Enable bit
& = concatenation operator, combines operands together forming one long operand.
The BCP has one conditional call instruction capable of testing any bit in any currently active CPU register. This call only supports absolute instruction addressing. Table 2-17 shows the conditional call instruction syntax and operation.
The return instruction complements the above call instruc
tions. Two versions of the return instruction exist, the un- condtional return and the conditional return. When the un
conditional return instruction is executed, it pops the last address on the CPU's Address Stack into the program counter and it can optionally affect the [GIE] bit, the ALU
2.0 CPU Description
(Continued)flags, and the register bank selection. Table 2-18 shows the syntax and operation of the unconditional return instruction.
The conditional return instruction functions the same as the unconditional return instruction if a desired condition is met.
As with the conditional jump instruction, the conditional re
turn instruction has two possible syntaxes. Table 2-19 lists the syntax for the conditional return. The “ f" flags and the
“cc” conditions for the return instruction are the same as for the conditional jump instruction, therefore refer to Table 2-12 and Table 2-13 for the listing of “f” and "cc”, respec
tively.
TABLE 2-17. Conditional Call Instruction
Syntax Instruction Operation Operand Range Addressing Mode
LCALL Rs, p, s, nn If the bit of register “ Rs” in position
“ p” is in the state “ s” then PC & [GIE] & ALU flags &
reg. bank selection —► Address Stack nn —* PC
End if
0,64k Register, Absolute
Note: PC = Program Counter; contents initially points to instruction following call.
[GIE] = Global Interrupt Enable bit
& = concatenation operator, combines operands together forming one long operand.
TABLE 2-18. Unconditional Return Instruction Syntax
RET !g (, rfj]
Instruction Operation Case“ g” of
0: leave [GIE] unaffected, (default) 1: restore [GIE] from Address Stack 2: set [GIE]
3: clear [GIE]
End case If “ rf” = 1 then
restore ALU flags from Address Stack
restore register bank selection from Address Stack Else (the default)
leave the ALU flags and register bank selections unchanged End if
Address Stack —> PC Note: PC = Program Counter
[GIE] = Global Interrupt Enable bit
I ) = surrounds optional operands that are not part of the instruction syntax.
Optional operands may either be specified or omitted.
TABLE 2-19. Conditional Return Instruction
Syntax Instruction Operand
RETF f , s f , [g ], {, r f ) } Rcc ( g( , r f ) ]
If the flag “ f” is in the state “ s” then perform a RET (g (, rf) ] If the condition “cc” is met then perform a RET (g (,rf)) Note: See Table XVIII for an explanation of "RET (g (, r f) )"
{) = surrounds optional operands that are not part of the instruction syntax.
Optional operands may either be specified or omitted.
P 8 3 4 4 B
D P 8 3 4 4 B
In addition to the above jump, call and return program flow instructions, the BCP is capable of generating software in
terrupts via the TRAP instruction. This instruction generates a call to any one of 64 possible interrupt table addresses based on its vector number operand. This allows both the simulation of hardware interrupts and the construction of special software interrupts, if desired. The actual interrupt table entry address is determined by concatenating the In
terrupt Base Register, (IBR), to an 8-bit representation of the vector number operand in the TRAP instruction. This instruction may also clear the [GIE] bit, if desired. Table 2-20 shows the syntax and operation of the TRAP instruc
tion.
2.0 CPU Description
(Continued)Miscellaneous Instructions
As stated in the “ CPU Register Set” section, the BCP has 44 registers with 24 of them arranged into four register banks: Main Bank A, Alternate Bank A, Main Bank B, and Alternate Bank B. The exchange instruction, EXX, selects which register banks are currently available to the CPU, for example either Main Bank A or Alternate Bank A. The dese
lected register banks retain their current values. The EXX instruction can also alter the state of [GIE], if desired. Table 2-21 shows the EXX instruction syntax and operation.
TABLE 2-20. TRAP Instruction
Syntax Instruction Operation Operand Range
TRAP v [, g 'j PC & [GIE] & ALU flags &
reg. Bank Selection —> Address Stack If “ g '” = 1 then clear [GIE]
Form PC address as shown below:
0, 63
I I I I I I I I I I I I I . „
{lBR> 0 0 v — ►PC
15 7 5 0
Note: PC = Program Counter; contents initially points to instruction following call.
[GIE] = Global Interrupt Enable bit IBR = Interrupt Base Register
& = concatenation operator, combines operands together forming one long operand.
I ) = surrounds optional operands that are not part of the instruction syntax.
Optional operands may either be specified or omitted.
TABLE 2-21. EXX Instruction Syntax Instruction Operation EXX ba, bb (,g) Case “ ba” of
0: activate Main Bank A 1: activate Alternate Bank A End case
Case “ bb” of
0: activate Main Bank B 1: activate Alternate Bank B End case
Case “ g” of
0: leave [GIE] unaffected, (default) 1: (reserved)
2: set [GIE]
3: clear [GIE]
End case Note: [GIE] = Global Interrupt Enable bit
( ! = surrounds optional operands that are not part of the instruction syntax.
Optional operands may either be specified or omitted.
2.2 CPU FUNCTIONAL DESCRIPTION