CPU Description (Continued)

In document DP8344B (Page 25-29)

mind that the Jcc instruction is just an optional syntax for the conditional JMP instruction.

The example inFigure 2-5 demonstrates two possible ways to code the conditional relative jump instruction when test-ing for a false [Z] flag inÀCCRÓ. In the example, assume that the symbol ‘‘Z’’ equals ‘‘000’’ binary, that the symbol

‘‘NS’’ equals ‘‘0’’ binary, and that the symbol ‘‘SKIP.IT’’

points to the desired instruction with which to begin execu-tion if [Z] is false.

On the other hand, the conditional absolute jump instruc-tion, LJMP, can test any bit in any currently active CPU reg-ister. Table 2-14 shows the conditional long jump instruction syntax.

JMP Z,NS,SKIP.IT ;If [Z]40 goto SKIP.IT

-or-JNZ SKIP.IT ;If [Z]40 goto SKIP.IT FIGURE 2-5. Coding Examples of Equivalent

Conditional Jump Instructions TABLE 2-11. Conditional Relative Jump Instruction

Syntax Instruction Operation Operand Range Addressing Mode

JMP f,s,n If the flag ‘‘f’’ is in the state ‘‘s’’ b128,a127 Immediate then PCan (sign extended)

x

PC

Jcc n If the condition ‘‘cc’’ is met b128,a127 Immediate

then PCan (sign extended)

x

PC

Note:PCeProgram Counter; contents initially points to instruction following jump.

TABLE 2-12. ‘‘f’’ Flags

‘‘f’’(Binary) Flag Flag Name Register Containing Flag

000 Z Zero ÀCCRÓ

001 C Carry ÀCCRÓ

010 V Overflow ÀCCRÓ

011 N Negative ÀCCRÓ

100 RA Receiver Active ÀTSRÓ

101 RE Receiver Error ÀTSRÓ

110 DAV Data Available ÀTSRÓ

111 TFF Transmitter FIFO Full ÀTSRÓ

TABLE 2-13. ‘‘cc’’ Conditions Tested

‘‘cc’’ Field Condition Tested for Flag ‘‘f’’’s Condition

Z Zero [Z] e1

RA Receiver Active [RA] e1

NRA Not Receiver Active [RA] e0

RE Receiver Error [RE] e1

NRE No Receiver Error [RE] e0

DA Data Available [DAV] e1

NDA No Data Available [DAV] e0

TFF Transmitter FIFO FULL [TFF] e1

NTFF Transmitter FIFO Not Full [TFF] e0

TABLE 2-14. Conditional Absolute Jump Instruction

Syntax Instruction Operation Operand Range Addressing Mode

LJMP Rs,p,s,nn If the bit of register ‘‘Rs’’ in 0, 64k Register, Absolute

position ‘‘p’’ is in the state ‘‘s’’

then nn

x

PC

Note:PCeProgram Counter

Obsolete

2.0 CPU Description

(Continued)

The BCP also has a specialized relative jump instruction called relative Jump with Rotate and Mask on source ter, JRMK. This instruction facilitates the decoding of regis-ter fields often involved in communications processing.

JRMK does this by rotating and masking a copy of its regis-ter operand to form a signed program counregis-ter displacement which usually points into a jump table. Table 2-15 shows the syntax and operation of the JRMK instruction.

JRMK’s masking, (setting to zero), the least significant bit of the displacement allows the construction of a jump table using either one or two word instructions; for instance, a table of JMP and/or LJMP instructions, respectively. The example inFigure 2-6 demonstrates the JRMK instruction decoding the address frame of the 3299 Terminal

Multiplex-er protocol which is located in the Receive/Transmit Regis-ter,ÀRTR[4 – 2]Ó.

The BCP has two unconditional call instructions; CALL, which supports relative instruction addressing and LCALL, (Long CALL), which supports absolute instruction address-ing. These instructions push the following information onto the CPU’s internal Address Stack: the address of the next instruction; the status of the Global Interrupt Enable flag, [GIE]; the status of the ALU flags [Z], [C], [N], and [V]; and the status of which register banks are currently active. Table 2-16 lists the two unconditional call instructions. Note that the Address Stack is only twelve positions deep; therefore, the BCP allows twelve levels of nested subroutine invoca-tions, (this includes both interrupts and calls).

TABLE 2-15. JRMK Instruction

Syntax Instruction Operation Displacement

Addressing Mode Range

JRMK Rs, b, m (a) Rotate a copy of register ‘‘Rs’’ ‘‘b’’ bits to the right. b128,a126 Register (b) Mask the most significant ‘‘m’’ bits and the least

significant bit of the above result.

(c) PCaresulting displacement (sign extended)

x

PC.

Note:PCeProgram Counter; contents initially points to instruction following jump.

Example Code

JRMK RTR,1,4 ;decode terminal address LJMP ADDR.0 ;jump to device handler #0 LJMP ADDR.1 ;jump to device handler #1 . . .

LJMP ADDR.7 ;jump to device handler #7

Instruction Execution JRMK Displacement Register Contents

(a) CopyÀRTRÓinto JRMK’s displacement register: x x x A2 A1 A0 y y

(b) Rotate displacement register 1 bit to the right: y x x x A2 A1 A0 y

(c) AND result with ‘‘00001110’’ binary mask: 0 0 0 0 A2 A1 A0 0

(d) Sign extend resulting displacement and add it to the program counter, (PC).

If the bits A2 A1 A0 equal ‘‘0 0 1’’ binary then

a2 is added to the Program Counter; 0 0 0 0 0 0 1 0

(i.e., PCa2

x

PC).

(e) Execute the instruction pointed to by the PC, which in this example is:

LJMP ADDR.1

FIGURE 2-6. JRMK Instruction Example TABLE 2-16. Unconditional Call Instructions

Syntax Instruction Operation Operand

Addressing Mode Range

CALL n PC & [GIE] & ALU flags & reg. bank selection

x

Address Stack b128,a127 Immediate PCan (sign extended)

x

PC

LCALL nn PC & [GIE] & ALU flags & reg. bank selection

x

Address Stack 0, 64k Absolute nn

x

PC

Note:PCeProgram Counter; contents initially points to instruction following call.

[GIE]eGlobal Interrupt Enable bit.

&econcatenation operator, combines operands together forming one long operand.

Obsolete

2.0 CPU Description

(Continued)

The BCP has one conditional call instruction capable of testing any bit in any currently active CPU register. This call only supports absolute instruction addressing. Table 2-17 shows the conditional call instruction syntax and operation.

The return instruction complements the above call instruc-tions. Two versions of the return instruction exist, the condtional return and the conditional return. When the un-conditional return instruction is executed, it pops the last address on the CPU’s Address Stack into the program counter and it can optionally affect the [GIE] bit, the ALU

flags, and the register bank selection. Table 2-18 shows the syntax and operation of the unconditional return instruction.

The conditional return instruction functions the same as the unconditional return instruction if a desired condition is met.

As with the conditional jump instruction, the conditional re-turn instruction has two possible syntaxes. Table 2-19 lists the syntax for the conditional return. The ‘‘f’’ flags and the

‘‘cc’’ conditions for the return instruction are the same as for the conditional jump instruction, therefore refer to Table 2-12 and Table 2-13 for the listing of ‘‘f’’ and ‘‘cc’’, respec-tively.

TABLE 2-17. Conditional Call Instruction

Syntax Instruction Operation Operand Range Addressing Mode

LCALL Rs, p, s, nn If the bit of register ‘‘Rs’’ in position 0, 64k Register, Absolute

‘‘p’’ is in the state ‘‘s’’ then PC & [GIE] & ALU flags &

reg. bank selection

x

Address Stack nn

x

PC

End if

Note:PCeProgram Counter; contents initially points to instruction following call.

[GIE]eGlobal Interrupt Enable bit

&econcatenation operator, combines operands together forming one long operand.

TABLE 2-18. Unconditional Return Instruction

Syntax Instruction Operation

RET ÀgÀ, rfÓ Ó Case ‘‘g’’ of

0: leave [GIE] unaffected, (default) 1: restore [GIE] from Address Stack 2: set [GIE]

3: clear [GIE]

End case If ‘‘rf’’e1 then

restore ALU flags from Address Stack

restore register bank selection from Address Stack Else (the default)

leave the ALU flags and register bank selections unchanged End if

Address Stack

x

PC

Note:PCeProgram Counter [GIE]eGlobal Interrupt Enable bit

À Ó esurrounds optional operands that are not part of the instruction syntax.

Optional operands may either be specified or omitted.

TABLE 2-19. Conditional Return Instruction

Syntax Instruction Operand

RETF f, sÀ,ÀgÓ,À, rfÓ Ó If the flag ‘‘f’’ is in the state ‘‘s’’ then perform a RETÀgÀ, rfÓ Ó Rcc ÀgÀ, rfÓ Ó If the condition ‘‘cc’’ is met then perform a RETÀgÀ,rfÓ Ó Note:See Table XVIII for an explanation of ‘‘RETÀgÀ, rfÓ Ó’’

À Ó esurrounds optional operands that are not part of the instruction syntax.

Optional operands may either be specified or omitted.

Obsolete

2.0 CPU Description

(Continued)

In addition to the above jump, call and return program flow instructions, the BCP is capable of generating software in-terrupts via the TRAP instruction. This instruction generates a call to any one of 64 possible interrupt table addresses based on its vector number operand. This allows both the simulation of hardware interrupts and the construction of special software interrupts, if desired. The actual interrupt table entry address is determined by concatenating the In-terrupt Base Register,ÀIBRÓ, to an 8-bit representation of the vector number operand in the TRAP instruction. This instruction may also clear the [GIE] bit, if desired. Table 2-20 shows the syntax and operation of the TRAP instruc-tion.

Miscellaneous Instructions

As stated in the ‘‘CPU Register Set’’ section, the BCP has 44 registers with 24 of them arranged into four register banks: Main Bank A, Alternate Bank A, Main Bank B, and Alternate Bank B. The exchange instruction, EXX, selects which register banks are currently available to the CPU, for example either Main Bank A or Alternate Bank A. The dese-lected register banks retain their current values. The EXX instruction can also alter the state of [GIE], if desired. Table 2-21 shows the EXX instruction syntax and operation.

TABLE 2-20. TRAP Instruction

Syntax Instruction Operation Operand Range

TRAP vÀ, gÊÓ PC & [GIE] & ALU flags & 0, 63 reg. Bank Selection

x

Address Stack

If ‘‘gÊ’’e1 then clear [GIE]

Form PC address as shown below:

Note:PCeProgram Counter; contents initially points to instruction following call.

[GIE]eGlobal Interrupt Enable bit IBReInterrupt Base Register

&econcatenation operator, combines operands together forming one long operand.

À Ó esurrounds optional operands that are not part of the instruction syntax.

Optional operands may either be specified or omitted.

TABLE 2-21. EXX Instruction Syntax Instruction Operation EXX ba, bbÀ, gÓ Case ‘‘ba’’ of

0: activate Main Bank A 1: activate Alternate Bank A End case

Case ‘‘bb’’ of

0: activate Main Bank B 1: activate Alternate Bank B End case

Case ‘‘g’’ of

0: leave [GIE] unaffected, (default) 1: (reserved)

2: set [GIE]

3: clear [GIE]

End case Note: [GIE]eGlobal Interrupt Enable bit

À Ó esurrounds optional operands that are not part of the instruction syntax.

Optional operands may either be specified or omitted.

Obsolete

2.0 CPU Description

(Continued)

In document DP8344B (Page 25-29)