DATA REGISTERS & COMPANDING

Each SPORT has a transmit and a receive register; SPORTO's registers are RXO and TXO, SPORTl's are RX1 and TXl. Companding (a contraction of COMpressing and exPANDing) is the process of logarithmically encoding data to minimize the number of bits that must be sent. Both SPORTs share the companding hardware: one expansion and one compression operation can occur in each processor cycle. In the event of contention, SPORTO has priority. The ADSP-2101 supports both of the widely used algorithms for companding: A-law and Il-law. The type of companding can be

independently selected for each SPORT.

Figure 6.1 shows the two data registers associated with each SPORT.

These registers, TXn and RXn, are identified by name in the ADSP-2101 assembly language, not memory-mapped.

TXn and RXn can be read and written (like other non-data registers) with the following instructions: read/write to data memory (direct address), load non-data immediate, and internal (register-to-register) moves.

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See Appendix A, Instruction Coding, for additional information and consult the instruction set reference found in the ADSP-2101 Cross-Software Manual.

6.6.1 Simple Operation Example

There are two ways to generate the SPORT interrupts, after the

transmisstion or receipt of 1) each data word or 2) each complete buffer of data words. This section discusses the first method. Section 6.7,

"Interrupts & Autobuffering," discusses the second.

Writing to the TXn register readies the SPORT for transmission; the TFS signal initiates it. The value in TXn is written to the internal transmit register and, after framing synchronization has occurred (if required), the bits are sent, MSB first.

When the first bit has been transferred, the SPORT generates the transmit interrupt. TXn is now available for the next piece of data, even though the transmission of the first is not complete.

In the receiving section, bits accumulate as they are received in an internal receive register. When a complete word has been received, it is written to the RXn register and the receive interrupt for that SPORT is generated.

6.6.2 Companding

Data Format: DTYPE

Companding is done according to the CCITT G.711 recommendation.

Companding and data format are controlled by the OTYPE field in the SPORT control register (shown in Figure 6.20) and described in Table 6.4.

SPORTO Control Register: H#3FF6 SPORT1 Control Register: H#3FF2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DTYPE (Data Format I Companding)

Figure 6.20 DTYPE Field in SPORT Control Register

DTYPE 00 01 10 11

Format of data

Right justify, zero fill unused MSBs

Right justify, sign extend into unused MSBs Compand using Il-law

Compand using A-law Table 6.4 DTYPE Field Values

6.6.2.1 Companding Internal Data

When companding is enabled, valid data in RXn is the right-justified, sign-extended, expanded value of the eight LSBs received. Likewise, a write to TXn causes the 16-bit value to be compressed to eight LSBs (sign-extended to the width of the transmit word) before being written to the internal transmit register. If the 16-bit value is greater than the 13-bit A-law or 14-bit Il-A-law maximum, it is automatically compressed to the maximum value.

Because the values in the RXn and TXn registers are actually companded

"in place" it is possible to use the companding hardware internally, without any transmission at all, such as for debugging and testing. This requires a single cycle of overhead.

With companding enabled:

1. Write data to TXn (compression is calculated).

2. Wait for one cycle (TXn is written with compressed value) 3. Read TXn (it returns the eight-bit compressed data)

Exactly the same approach works for expanding data, using RXn instead of TXn.

6.6.3 Companding Operation Example

With hardware companding, interfacing to a codec requires little additional programming effort. See the codec hardware interfacing example in the last section of this chapter.

Here is a typical sequence of operations for transmitting companded data:

• Write data to the TXn register

• The value in TXn is compressed

• The compressed value is written back to TXn

• After the frame sync signal has occurred (if required), TXn is written to

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As soon as the SPORT has started to send the second bit of the current word, TXn can be written with the next word, even though transmission of the first is not complete. When the first bit has been transferred, the SPORT generates the transmit interrupt to indicate that TXn is ready for the next data word. If the framing signal is being provided externally, the next word must be written to TXn early enough to allow for compression before the next framing signal arrives.

Here is a typical sequence of operations for receiving companded data:

• Bits accumulate as received in the internal receive register

• When a complete word is received, it is written to RXn

• The value in Rxn is expanded

• The expanded value is written back to RXn

The receive interrupt for that SPORT is then generated.

6.6.4 Contention For Companding Hardware

Since both SPORTs share the companding hardware, only one

compression and one expansion operation can take place during a single machine cycle. If contention arises, such as when two expansions need to occur in the same cycle, SPORTO has priority, while SPORTl is forced to wait one cycle.

The effects of contention, however, are usually small. The instruction set does not support loading both

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consequently these operations will be naturally out of phase for contention in many cases. The overhead cycle for the receive operation occurs prior to the receive interrupt and does not increase the time needed to service the interrupt, although it does affect the interval between interrupts.