Debug Control Register 3 (DBCR3)

DBCR3, shown in Figure 2-36, is an e200z3 implementation-specific register to enable and configure the debug counter and debug counter events. For counter operation, the specific debug events that cause counters to decrement are specified in DBCR3.

NOTE

Corresponding events do not need to be (and probably should not be) enabled in DBCR0.

The IAC1–IAC4 and DAC1–DAC2 control fields in DBCR0 are ignored for counter operations and the control fields in DBCR3 determine when counting is enabled. DBCR1 and DBCR2 control fields are also used to determine the configuration of IAC1–IAC4 and DAC1–DAC2 operations for counting, even though the setting of bits in DBSR by corresponding events can be disabled via DBCR0. Multiple count-enabled events that occur during execution of an instruction typically cause only one decrement of a counter. For example, if more than one IAC or DAC register hits and is enabled for counting, only one count can occur per counter. During execution of lmw and stmw instructions, multiple DACn hits can occur. If the instruction is not interrupted before completion, a single decrement of a counter occurs.

NOTE

If the counters operate independently, both may count for the same instruction.

The debug counter register (DBCNT) is configured by DBCR3[CONFIG] to operate either as separate 16-bit counter 1 and counter 2 or as a combined 32-bit counter (using control bits in DBCR3 for counter 1). Counters are enabled when any of their respective count enable event control bits are set and either DBCR0 or DBCR0[EDM] is set. Counter 1 can be configured to count down on a number of different debug events. Counter 2 is also configurable to count down on instruction complete, instruction or data address compare events, and external events.

Special capability is provided for counter 1 to be triggered to begin counting down by a subset of events (IAC1, IAC3, DAC1R, DAC1W, DEVT1, DEVT2, and counter 2). When one or more of the counter 1 trigger bits is set (IAC1T1, IAC3T1, DAC1RT1, DAC1WT1, DEVT1T1, DEVT2T1, CNT2T1), counter 1 is frozen until at least one of the triggering events occurs and is then enabled to begin operation.

Triggering status for counter 1 is provided in the debug status register. Triggering mode is enabled by an mtspr DBCR3 which sets one or more of the trigger enable bits and also enables counter 1. The trigger can be re-armed by clearing the DBSR[CNT1TRG] status bit.

Most combinations of enables do not make sense and should be avoided. For example, if DBCR3[ICMP]

is set for counter 1, no other count enable should be set for counter 1. Conversely, multiple instruction address compare count enables are allowed to be set and can be useful.

Due to instruction pipelining issues and other constraints, most combinations of events are not supported for event counting. Only the following combinations are for use; other combinations are not supported:

• Any combination of IAC[1–4]

• Any combination of DAC[1–2] including linking

• Any combination of DEVT[1–2]

• Any combination of IRPT and RET

Limited support is provided for any combination of IAC[1–4] with DAC[1–2] (linked or unlinked).

Due to pipelining and detection of IAC events early in the pipeline and DAC events late in the pipeline, no guarantee is made on the exact instruction boundary that a debug exception is generated when IAC and DAC events are combined for counting. This also applies when counter 1 is triggered by counter 2, and a combination of IAC and DAC events is enabled for the counters, even if only one of these types is enabled for a particular counter. In general, when an IAC event logically follows a DAC event within several instructions, it cannot be recognized immediately because the DAC event may not be generated in the pipeline at the time the IAC appears. Thus, the counter may not decrement to zero for the IAC event until after the instruction with the IAC (and perhaps several additional instructions) proceeds down the execution pipeline. The instruction boundary where the debug exception is actually generated typically follows the IAC by up to several instructions.

Note that the counters operate regardless of whether counters are enabled to generate debug exceptions.

If counter 2 is used to trigger counter 1, counter 2 events should not normally be enabled in DBCR0 and are not blocked.

NOTE

Multiple IAC or DAC events are not counted during an lmw or stmw instruction, and no count occurs if either is interrupted by a critical input or external input interrupt before completion.

32 33 34 35 36 37 38 39

Field DEVT1C1 DEVT2C1 ICMPC1 IAC1C1 IAC2C1 IAC3C1 IAC4C1 DAC1RC1

Reset All zeros

R/W R/W

40 41 42 43 44 45 46 47

Field DAC1WC1 DAC2RC1 DAC2WC1 IRPTC1 RETC1 DEVT1C2 DEVT2C2 ICMPC2

Reset All zeros

R/W R/W

48 49 50 51 52 53 54 55

IAC1C2 IAC2C2 IAC3C2 IAC4C2 DAC1RC2 DAC1WC2 DAC2RC2 DAC2WC2

Reset All zeros

R/W R/W

56 57 58 59 60 61 62 63

DEVT1T1 DEVT2T1 IAC1T1 IAC3T1 DAC1RT1 DAC1WT1 CNT2T1 CONFIG

Reset All zeros

R/W R/W

SPR SPR 561

Figure 2-36. DBCR3 Register

Table 2-20 provides field definitions for DBCR3

Table 2-20. DBCR3 Field Descriptions

Bits Name Description

32 DEVT1C1 External debug event 1 count 1 enable.

0 Counting DEVT1 debug events by counter 1 is disabled.

1 Counting DEVT1 debug events by counter 1 is enabled.

33 DEVT2C1 External debug event 2 count 1 enable.

0 Counting DEVT2 debug events by counter 1 is disabled.

1 Counting DEVT2 debug events by counter 1 is enabled.

34 ICMPC1 Instruction complete debug event count 1 enable.

0 Counting ICMP debug events by counter 1 is disabled.

1 Counting ICMP debug events by counter 1 is enabled.

ICMP events are masked by MSR[DE] = 0 when operating in internal debug mode.

35 IAC1C1 Instruction address compare 1 debug event count 1 enable.

0 Counting IAC1 debug events by counter 1 is disabled.

1 Counting IAC1 debug events by counter 1 is enabled.

36 IAC2C1 Instruction address compare2 debug event count 1 enable.

0 Counting IAC2 debug events by counter 1 is disabled.

1 Counting IAC2 debug events by counter 1 is enabled.

37 IAC3C1 Instruction address compare 3 debug event count 1 enable.

0 Counting IAC3 debug events by counter 1 is disabled.

1 Counting IAC3 debug events by counter 1 is enabled.

38 IAC4C1 Instruction address compare 4 debug event count 1 enable.

0 Counting IAC4 debug events by counter 1 is disabled.

1 Counting IAC4 debug events by counter 1 is enabled.

39 DAC1RC1 Data address compare 1 read debug event count 1 enable¹. 0 Counting DAC1R debug events by counter 1 is disabled.

1 Counting DAC1R debug events by counter 1 is enabled.

40 DAC1WC1 Data address compare 1 write debug event count 1 enable ¹. 0 Counting DAC1W debug events by counter 1 is disabled.

1 Counting DAC1W debug events by counter 1 is enabled.

41 DAC2RC1 Data address compare 2 read debug event count 1 enable ¹. 0 Counting DAC2R debug events by counter 1 is disabled.

1 Counting DAC2R debug events by counter 1 is enabled.

42 DAC2WC1 Data address compare 2 write debug event count 1 enable ¹. 0 Counting DAC2W debug events by counter 1 is disabled.

1 Counting DAC2W debug events by counter 1 is enabled.

43 IRPTC1 Interrupt taken debug event count 1 enable.

0 Counting IRPT debug events by counter 1 is disabled.

1 Counting IRPT debug events by counter 1 is enabled.

44 RETC1 Return debug event count 1 enable.

0 Counting RET debug events by counter 1 is disabled.

1 Counting RET debug events by counter 1 is enabled.

45 DEVT1C2 External debug event 1 count 2 enable.

0 Counting DEVT1 debug events by counter 2 is disabled.

1 Counting DEVT1 debug events by counter 2 is enabled.

46 DEVT2C2 External debug event 2 count 2 enable.

0 Counting DEVT2 debug events by counter 2 is disabled.

1 Counting DEVT2 debug events by counter 2 is enabled.

47 ICMPC2 Instruction complete debug event count 2 enable.

0 Counting ICMP debug events by counter 2 is disabled.

1 Counting ICMP debug events by counter 2 is enabled.

ICMP events are masked by MSR[DE] = 0 when operating in internal debug mode.

48 IAC1C2 Instruction address compare 1 debug event count 2 enable.

0 Counting IAC1 debug events by counter 2 is disabled.

1 Counting IAC1 debug events by counter 2 is enabled.

49 IAC2C2 Instruction address compare2 debug event count 2 enable.

0 Counting IAC2 debug events by counter 2 is disabled.

1 Counting IAC2 debug events by counter 2 is enabled.

50 IAC3C2 Instruction address compare 3 debug event count 2 enable.

0 Counting IAC3 debug events by counter 2 is disabled.

1 Counting IAC3 debug events by counter 2 is enabled.

51 IAC4C2 Instruction address compare 4 debug event count 2 enable.

0 Counting IAC4 debug events by counter 2 is disabled.

1 Counting IAC4 debug events by counter 2 is enabled.

52 DAC1RC2 Data address compare 1 read debug event count 2 enable ¹. 0 Counting DAC1R debug events by counter 2 is disabled.

1 Counting DAC1R debug events by counter 2 is enabled.

53 DAC1WC2 Data address compare 1 write debug event count 2 enable ¹. 0 Counting DAC1W debug events by counter 2 is disabled.

1 Counting DAC1W debug events by counter 2 is enabled.

54 DAC2RC2 Data address compare 2 read debug event count 2 enable ¹. 0 Counting DAC2R debug events by counter 2 is disabled.

1 Counting DAC2R debug events by counter 2 is enabled.

55 DAC2WC2 Data address compare 2 write debug event count 2 enable ¹. 0 Counting DAC2W debug events by counter 2 is disabled.

1 Counting DAC2W debug events by counter 2 is enabled.

56 DEVT1T1 External debug event 1 trigger counter 1 enable.

0 No effect.

1 A DEVT1 debug event triggers counter 1 operation.

57 DEVT2T1 External debug event 2 trigger counter 1 enable.

0 No effect.

1 A DEVT2 debug event triggers counter 1 operation.

58 IAC1T1 Instruction address compare 1 trigger counter 1 enable.

0 No effect.

1 An IAC1 debug event triggers counter 1 operation.

59 IAC3T1 Instruction address compare 3 trigger counter 1 enable.

0 No effect.

1 An IAC3 debug event triggers counter 1 operation.

Table 2-20. DBCR3 Field Descriptions (continued)

Bits Name Description

NOTE

Perform updates to DBCR0, DBSR, DBCR3, and DBCNT carefully if the counters are enabled for counting ICMP events. An instruction that updates the counters or control over the counters can cause one or more counter events (DCNT1, DCNT2, CNT1TRG), even if the result of the instruction is to modify the counter value or control value to a state where counter events are not expected. This is due to the pipelined nature of the counter and control operation.

• For DBCNT, if a counter is enabled to count ICMP events,

MSR[DE] = 1, and the counter value is 1 before execution of an mtspr that loads the counter with a different value, a counter event is generated after the mtspr completes, even though the counter is loaded with a new value. When the mtspr finishes executing, a debug event is posted, but the counter holds the newly written value. The new counter value is assigned at the completion of an mtspr that modifies a counter, regardless of whether a debug event is generated based on the old counter value. To avoid this, modify DBCNT and DBCR3 only when there is no possibility of a counter-related debug event on the mtspr.

• For DBCR3, if a counter is enabled to count ICMP events,

MSR[DE] = 1, and the counter value is 1 before execution of an mtspr that is loading DBCR3 with a different value, a counter event may be generated after the mtspr completes, even though DBCR3 is loaded with a value that prevents the particular event from being counted.

When the mtspr finishes executing, a debug event is posted, but the

60 DAC1RT1 Data address compare 1 read trigger counter 1 enable.

0 No effect.

1 A DAC1R debug event triggers counter 1 operation.

61 DAC1WT1 Data address compare 1 write trigger counter 1 enable.

0 No effect.

1 A DAC1W debug event triggers counter 1 operation.

62 CNT2T1 Debug counter 2 trigger counter 1 enable.

0 No effect.

1 Counter 2 decrementing to 0 triggers counter 1 operation.

63 CONFIG Debug counter configuration.

0 Counter 1 and counter 2 are independent counters.

1 Counter 1 and counter 2 are concatenated into a single 32-bit counter. The event count control bits for counter 1 are used and the event count control bits for counter 2 are ignored.

1 If the DACx field in DBCR0 is set to restrict events to only reads or only writes, only those events are counted if enabled in DBCR3. In general, DAC events should be disabled in DBCR0.

Table 2-20. DBCR3 Field Descriptions (continued)

Bits Name Description

DBCR3 value reflects the newly established control, which may indicate that the particular event is not to cause a counter update.

Modifying DBCR0 to affect counter event enabling/disabling may have similar issues, as may modifying DBSR[CNT1TRG].

W dokumencie E200Z3 (Stron 91-96)