Debug External Resource Control Register (DBERC0)

The Debug External Resource Control Register (DBERC0) controls resource allocation when DBCR0[EDM] is set to ‘1’. DBERC0 provides a mechanism for the hardware debugger to share debug resources with software. Individual resources are allocated based on the settings of DBERC0 when DBCR0[EDM]=1. DBERC0 settings are ignored when DBCR0[EDM]=0.

Hardware-owned resources which generate debug events cause entry into debug mode, while software-owned resources which generate debug events act as if they occurred in internal debug mode, thus causing debug interrupts to occur if DBCR0[IDM]=1 and MSR[DE]=1. DBERC0 is controlled via the OnCE port hardware, and is read-only to software.

39 TRAP Trap taken debug event. Set if a trap taken debug event occurs.

40 IAC1 Instruction address compare 1 debug event. Set if an IAC1 debug event occurs.

41 IAC2 Instruction address compare 2 debug event. Set if an IAC2 debug event occurs.

42 IAC3 Instruction address compare 3 debug event. Set if an IAC3 debug event occurs.

43 IAC4 Instruction address compare 4 debug event. Set if an IAC4 debug event occurs.

44 DAC1R Data address compare 1 read debug event. Set if a read-type DAC1 debug event occurs while DBCR0[DAC1] = 0b10 or DBCR0[DAC1] = 0b11.

45 DAC1W Data address compare 1 write debug event. Set if a write-type DAC1 debug event occurs while DBCR0[DAC1] = 0b01 or DBCR0[DAC1] = 0b11.

46 DAC2R Data address compare 2 read debug event. Set if a read-type DAC2 debug event occurs while DBCR0[DAC2] = 0b10 or DBCR0[DAC2] = 0b11.

47 DAC2W Data address compare 2 write debug event. Set if a write-type DAC2 debug event occurs while DBCR0[DAC2] = 0b01 or DBCR0[DAC2] = 0b11.

48 RET Return debug event. Set if a Return debug event occurs.

49–52 — Reserved, should be cleared.

53 DEVT1 External debug event 1 debug event. Set if a DEVT1 debug event occurs.

54 DEVT2 External debug event 2 debug event. Set if a DEVT2 debug event occurs.

55 DCNT1 Debug counter 1 debug event. Set if a DCNT1 debug event occurs.

56 DCNT2 Debug counter 2 debug event. Set if a DCNT2 debug event occurs.

57 CIRPT Critical interrupt taken debug event. Set if a critical interrupt taken debug event occurs.

58 CRET Critical return debug event. Set if a critical return debug event occurs.

59–60 — Reserved, should be cleared.

61–62 DAC_OFS T

Data Address Compare Offset (e200z335 only, reserved on e200z3)

Indicates offset-1 of saved DSRR0 value from the address of the load or store instruction which took a DAC Debug exception, unless a simultaneous DTLB or DSI error occurs, in which case this field is set to 2‘b00 and DBSR[IDE] is set to 1. Normally set to 2‘b00. A DVC DAC will set this field to 2’b01.

63 CNT1TRG Counter 1 triggered. Set if debug counter 1 is triggered by a trigger event.

Table 2-22. DBSR Field Descriptions (continued)

Bits Name Description

Debug Status bits in DBSR are set by software-owned debug events only while Internal Debug Mode is enabled. When debug interrupts are enabled (MSR[DE]=1 DBCR0[IDM]=1 and DBCR0[EDM]=0, or MSR[DE]=1, DBCR0[IDM]=1 and DBCR0[EDM]=1 and software is allocated resource(s) via DBERC0), a set bit in DBSR which is software-owned other than MRR or VLES will cause a debug interrupt to be generated.

Debug Status bits in DBSR are set by hardware-owned debug events only while External Debug Mode is enabled (DBCR0[EDM]=1).

If DBERC0[IDM]=1, all DBSR status bits corresponding to hardware-owned debug events are masked to 0 when accessed by software. The actual values in the DBSR register is always visible to hardware when accessed via the OnCE port.

Software-owned resources may be modified by software, but only the corresponding control and status bits in DBCR0-4 and DBSR are affected by execution of a mtspr, thus only a portion of these registers may be affected, depending on the allocation settings in DBERC0. The debug interrupt handler is still responsible for clearing software-owned DBSR bits prior to returning to normal execution. Hardware always has full access to all registers and all register fields through the OnCE register access mechanism, and it is up to the debug firmware to properly implement modifications to these registers with read-modify-write operations to implement any control sharing with software. Settings in DBERC0 should be considered by the debug firmware in order to preserve software settings of control and status registers as appropriate when hardware modifications to the debug registers is performed.

The DBERC0 register is shown in Figure 2-39.

0 IDM RST UDE ICMP BRT IRPT TRAP IAC1 IAC2 IAC3 IAC4 DAC1 0

DAC2

0 RET 0

DEVT1 DEVT2 DCNT1 DCNT2 CIRPT CRET BKPT FT

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 569; Read-only by Software; Reset - Unaffected by p_reset_b, cleared by m_por or while in the test-logic-reset

OnCE controller state

Figure 2-39. DBERC0 Register

Table 2-22 provides bit definitions for the Debug External Resource Control Register. Note that DBERC0 controls are disabled when DBCR0[EDM]=0.

Table 2-23. DBERC0 Bit Definitions

Bit(s) Name Description

0 — Reserved

1 IDM

Internal Debug Mode control

0 - Internal Debug mode may not be enabled by software. DBCR0[IDM] is owned exclusively by hardware. mtspr DBCR0-4, DBCNT or DBSR is always ignored. No resource sharing occurs, regardless of the settings of other fields in DBERC0. Hardware exclusively owns all resources.

1 - Internal Debug mode may be enabled by software. DBCR0[IDM], DBSR[IDE], and DBSR[MRR] are owned by software. DBCR0[IDM], DBSR[IDE], and DBSR[MRR] are software readable/writeable.

When DBERC0[IDM]=1, hardware-owned status and control bits in DBSR are masked from software access and read as 0. Software writes to hardware-owned bits in DBCR0-4, DBCNT, and DBSR via mtspr are ignored.

2 RST

Reset Field Control

0 - DBCR0[RST] owned exclusively by hardware debug. No mtspr access by software to DBCR0[RST] field.

1 - DBCR0[RST] accessible by software debug. DBCR0[RST] is software readable/writeable.

3 UDE

Unconditional Debug Event

0 - Event owned by hardware debug. No mtspr access by software to DBSR[UDE] field.

1 - Event owned by software debug. DBSR[UDE] is software readable/writeable.

4 ICMP

Instruction Complete Debug Event

0 - Event owned by hardware debug. No mtspr access by software to DBCR0[ICMP] or DBSR[ICMP] fields.

1 - Event owned by software debug. DBCR0[ICMP] and DBSR[ICMP] are software readable/writeable.

5 BRT

Branch Taken Debug Event

0 - Event owned by hardware debug. No mtspr access by software to DBCR0[BRT] or DBSR[BRT] fields.

1 - Event owned by software debug. DBCR0[BRT] and DBSR[BRT] are software readable/writeable.

6 IRPT

Interrupt Taken Debug Event

0 - Event owned by hardware debug. No mtspr access by software to DBCR0[IRPT] or DBSR[IRPT] fields.

1 - Event owned by software debug. DBCR0[IRPT] and DBSR[IRPT] are software readable/writeable.

7 TRAP

Trap Taken Debug Event

0 - Event owned by hardware debug. No mtspr access by software to DBCR0[TRAP] or DBSR[TRAP] fields.

1 - Event owned by software debug. DBCR0[TRAP] and DBSR[TRAP] are software readable/writeable.

8 IAC1

Instruction Address Compare 1 Debug Event

0 - Event owned by hardware debug. No mtspr access by software to IAC1 control and status fields.

1 - Event owned by software debug. DBCR0[IAC1] and DBSR[IAC1] are software readable/writeable.

9 IAC2

Instruction Address Compare 2 Debug Event

0 - Event owned by hardware debug. No mtspr access by software to IAC2 control and status fields.

1 - Event owned by software debug. IAC2 control and status fields are software readable/writeable.

10 IAC3

Instruction Address Compare 3 Debug Event

0 - Event owned by hardware debug. No mtspr access by software to IAC3 control and status fields.

1 - Event owned by software debug. IAC3 control and status fields are software readable/writeable.

11 IAC4

Instruction Address Compare 4 Debug Event

0 - Event owned by hardware debug. No mtspr access by software to IAC4 control and status fields.

1 - Event owned by software debug. IAC4 control and status fields are software readable/writeable.

12 DAC1

Data Address Compare 1 Debug Event

0 - Event owned by hardware debug. No mtspr access by software to DAC1 control and status fields.

1 - Event owned by software debug. DAC1 control and status fields are software readable/writeable.

13 — Reserved

14 DAC2

Data Address Compare 2 Debug Event

0 - Event owned by hardware debug. No mtspr access by software to DAC2 control and status fields.

1 - Event owned by software debug. DAC2 control and status fields are software readable/writeable.

15 — Reserved

16 RET

Return Debug Event

0 - Event owned by hardware debug. No mtspr access by software to DBCR0[RET] or DBSR[RET] fields.

1 - Event owned by software debug. DBCR0[RET] and DBSR[RET] are software readable/writeable.

17:20 — Reserved

21 DEVT1

External Debug Event 1 Debug Event

0 - Event owned by hardware debug. No mtspr access by software to DBCR0[DEVT1] or DBSR[DEVT1] fields.

1 - Event owned by software debug. DBCR0[DEVT1] and DBSR[DEVT1] are software readable/writeable.

Table 2-23. DBERC0 Bit Definitions (continued)

Bit(s) Name Description

22 DEVT2

External Debug Event 2 Debug Event

0 - Event owned by hardware debug. No mtspr access by software to DBCR0[DEVT2] or DBSR[DEVT2] fields.

1 - Event owned by software debug. DBCR0[DEVT2] and DBSR[DEVT2] are software readable/writeable.

23 DCNT1

Debug Counter 1 Debug Event

0 - Event owned by hardware debug. No mtspr access by software to Counter1 control and status fields.

1 - Event owned by software debug. Counter1 control and status fields are software readable/writeable.

24 DCNT2

Debug Counter 2 Debug Event

0 - Event owned by hardware debug.No mtspr access by software to Counter2 control and status fields.

1 - Event owned by software debug. Counter2 control and status fields are software readable/writeable.

25 CIRPT

Critical Interrupt Taken Debug Event

0 - Event owned by hardware debug. No mtspr access by software to DBCR0[CIRPT] or DBSR[CIRPT] fields.

1 - Event owned by software debug. DBCR0[CIRPT] and DBSR[CIRPT] are software readable/writeable.

26 CRET

Critical Return Debug Event

0 - Event owned by hardware debug. No mtspr access by software to DBCR0[CRET] or DBSR[CRET] fields.

1 - Event owned by software debug. DBCR0[CRET] and DBSR[CRET] are software readable/writeable.

22 BKPT

Breakpoint Instruction Debug Control

0 - Breakpoint owned by hardware debug. Execution of a bkpt instruction (all 0’s opcode) results in entry into debug mode.

1 - Breakpoint owned by software debug. Execution of a bkpt instruction (all 0’s opcode) results in illegal instruction exception.

27:30 — Reserved

31 FT

Freeze Timer Debug Control

0 - DBCR0[FT] owned by hardware debug. No access by software.

1 - DBCR0[FT] owned by software debug. DBSR[FT] is software readable/writeable.

Table 2-23. DBERC0 Bit Definitions (continued)

Bit(s) Name Description

Table 2-24 shows which resources are controlled by DBERC0 settings.

Table 2-24. DBERC0 Resource Control

DBCR0[EDM] DBERC0[IDM] DBERC0[RST] DBERC0[ICMP] DBERC0[BRT] DBERC0[IRPT] DBERC0[TRAP] DBERC0[IAC1] DBERC0[IAC2] DBERC0[IAC3] DBERC0[IAC4] DBERC0[DAC1] DBERC0[DAC2] DBERC0[DEVT1] DBERC0[DEVT2] DBERC0[DCNT1] DBERC0[DCNT2] DBERC0[CIRPT] DBERC0[CRET] DBERC0[BKPT] DBERC0[FT]

Name

1 1 - - - - - - - - - - 1 - - - - - - -

Table 2-24. DBERC0 Resource Control (continued)

DBCR0[EDM] DBERC0[IDM] DBERC0[RST] DBERC0[ICMP] DBERC0[BRT] DBERC0[IRPT] DBERC0[TRAP] DBERC0[IAC1] DBERC0[IAC2] DBERC0[IAC3] DBERC0[IAC4] DBERC0[DAC1] DBERC0[DAC2] DBERC0[DEVT1] DBERC0[DEVT2] DBERC0[DCNT1] DBERC0[DCNT2] DBERC0[CIRPT] DBERC0[CRET] DBERC0[BKPT] DBERC0[FT]

Name

Software Accessible via mtspr,

affected by p_reset_b

DBERC0 also controls which bits or fields in DBCR0-4 are reset by assertion of p_reset_b when DBCR0[EDM]=1. Only software-owned bits or fields as shown in Table 2-24 are affected in this case, except that DBCR0[RST] and DBSR[MRR] are updated by assertion of p_reset_b regardless of the value of DBCR0[EDM] or DBERC0.

W dokumencie E200Z3 (Stron 98-105)