When the enhanced ABus mode is selected, several chang-es occur. The timing of ABÐACK is modified during read accesses. In this mode, read data is expected one cycle after the ABÐACK signal (see Figure 6-8 and Figure 6-11 ).
In addition, channel information is no longer supplied on the upper four bits of the Address/Data lines during the address cycle. Instead, the value of this nibble of address is supplied from a programmable register within the MACSI device (for a full description of these bits please see System Interface Mode Register1 (SIMR1)). Finally, the ABÐDEN signal be-comes an input in this enhanced mode. This signal, along with ABÐACK and ABÐERR, are used to encode a subset of the acknowledge, retry, and error functions supported on the SBus.
These enhancements make it easier to connect the MACSI device to the SBus as a bus master. However, a full FDDI adapter design requires the design of a slave interface from the SBus to the control bus of the MACSI device and the other FDDI components.
6.5.1 Enhanced ABus Mode Bus Transactions
Bus transactions in the Enhanced Abus Mode are shown in Figure 6-8 through Figure 6-11. In the Enhanced ABus mode, the Bus Request signal (ABÐBR) will be deasserted after the bus is granted until the completion of the bus trans-action. The only exception to this may occur when the MACSI device is attempting back-to-back burst reads. In this case ABÐBR may be deasserted for as few as two cycles.
Single Read
Tbr: MACSI device asserts ABÐBR to indicate it wishes to perform a transfer. Host asserts ABÐBG. The MACSI de-vice moves to Tma on the next cycle.
Tma: MACSI device drives ABÐA and ABÐAD with the master address, asserts ABÐAS, drives ABÐR/W and ABÐSIZ[2:0], and negates ABÐBR until the end of this transaction.
Tpa: The Physical address is asserted by the MMU.
Td: MACSI device negates ABÐAS and samples ABÐACK, ABÐERR, and ABÐDEN. Slave asserts ABÐACK, ABÐERR, and ABÐDEN with the appropriate acknowledg-ment. The MACSI device samples a valid acknowledgment and moves to Tr. Tw states may occur after Td.
Tr: MACSI device negates ABÐR/W, ABÐDEN, and ABÐSIZ[2:0], releases ABÐA and ABÐAS, and samples ABÐAD. Slave drives ABÐAD (with data), deasserts ABÐACK, ABÐERR, and ABÐDEN, and releases ABÐ
Obsolete
AD.6.0 Functional Description (Service Engine)
(Continued)TL/F/11705 – 13
FIGURE 6-8. Enhanced ABus Read TimingÐ0 w/s, 1 w/s
TL/F/11705 – 14
FIGURE 6-9. Enhanced ABus Mode Write Timing
Obsolete
6.0 Functional Description (Service Engine)
(Continued)TL/F/11705 – 15
FIGURE 6-10. Enhanced ABus Mode Burst Write Timing Single Write
Tbr: MACSI device asserts ABÐBR to indicate it wishes to perform a transfer. Host asserts ABÐBG. The MACSI de-vice moves to Tma in the next cycle.
Tma: MACSI device drives ABÐA and ABÐAD with the master address, asserts ABÐAS, drives ABÐR/W and ABÐSIZ[2:0], and negates ABÐBR until the end of this transaction.
Tpa: The Physical address is asserted by the MMU.
Td: MACSI device negates ABÐAS, drives ABÐAD with the write data and starts sampling ABÐACK, ABÐERR, and ABÐDEN. Slave captures ABÐAD data, and acknowledges with ABÐACK, ABÐERR, and ABÐDEN. Tw states may occur after Td if the slave does not acknowledge.
Tr: MACSI device negates ABÐR/W, ABÐSIZ[2:0], releas-es ABÐA, ABÐAD, and ABÐAS, and stops driving ABÐAD with data. Slave deasserts ABÐACK, ABÐERR, and ABÐDEN.
Obsolete
6.0 Functional Description (Service Engine)
(Continued)TL/F/11705 – 16
FIGURE 6-11. Enhanced ABus Mode Back-to-Back Read Timing Burst Read
Tbr: MACSI device asserts ABÐBR to indicate it wishes to perform a transfer. Host asserts ABÐBG. The MACSI de-vice moves to Tma in the next cycle. This cycle may be skipped if ABÐBR was asserted during the previous ac-cess. This allows for back-to-back burst reads.
Tma: MACSI device drives ABÐA and ABÐAD with the master address, asserts ABÐAS, drives ABÐR/W and ABÐSIZ[2:0], and negates ABÐBR for at least two cycles.
Tpa: The Physical Address is asserted by the MMU.
Td: MACSI device samples ABÐACK, ABÐERR, and ABÐDEN, and increments the address on ABÐA. Slave acknowledges using ABÐACK, ABÐERR, and ADÐDEN.
MACSI device samples a valid ABÐACK and latches data in the following cycle. Tw states may occur after Td. Td state is repeated four or eight times (according to the burst size). If SIMR1.ASM e 0, the MACSI device negates ABÐAS in the last Td cycle. If SIMR1.ASMe1, the MACSI device negates ABÐAS in the first Td cycle.
Tr: MACSI device negates ABÐR/W and ABÐSIZ[2:0] and releases ABÐA and ABÐAS. Slave drives ABÐAD (with data), deasserts ABÐACK, ABÐERR, and ABÐDEN. If an-other request is pending (ABÐBR asserted) and the Bus is
regranted in this cycle, the MACSI device will proceed di-rectly to the Tma state of the next burst. The normal Tbr state is skipped allowing back-to-back burst reads.
Burst Write
Tbr: MACSI device asserts ABÐBR to indicate it wishes to perform a transfer. Host asserts ABÐBG. The MACSI de-vice moves to Tma in the next cycle.
Tma: MACSI device drives ABÐA and ABÐAD with the master address, asserts ABÐAS, drives ABÐR/W and ABÐSIZ[2:0], and negates ABÐBR until this transaction is completed.
Tpa: The Physical Address is asserted by the MMU.
Td: MACSI device drives ABÐAD with the write data, sam-ples ABÐACK, ABÐERR, and ABÐDEN, and increments the address on ABÐA. Slave captures ABÐAD data and acknowledges using ABÐACK, ABÐERR, and ABÐDEN.
MACSI device samples a valid acknowledge. Tw states may occur after Td. Td state is repeated as required for the com-plete burst. If SIMR1.ASMe0, the MACSI device negates ABÐAS in the last Td cycle. If SIMR1.ASMe1, the MACSI device negates ABÐAS in the first Td cycle.
Tr: MACSI device negates ABÐR/W, ABÐSIZ[2:0], releas-es ABÐA and ABÐAS, and stops driving ABÐAD with data. Slave deasserts ABÐACK, ABÐERR, and ABÐDEN.