Register Model
3.11 Enhanced Debug
The e200z4 implements the Power ISA embedded debug architecture to support the capability to handle the debug interrupt as an additional interrupt level. To support this interrupt level, a new ‘return from debug interrupt’ (rfdi, se_rfdi) instruction is defined as part of the debug instruction set, along with a new pair of save/restore registers, DSRR0, and DSRR1.
When the debug capability is enabled (HID0[DAPUEN] = 1), the rfdi or se_rfdi instruction provides a means to return from a debug interrupt. See Section 2.4.11, “Hardware Implementation Dependent Register 0 (HID0)” for more information about enabling the debug functionality.
The instruction form and definition is as follows.
31 RT RA RB crb 0 1 1 1 1 0
0 5 6 10 11 15 16 20 21 25 26 30 31
rfdi rfdi
Return From Debug Interrupt rfdi
MSR ←DSRR1
PC ←DSRR00:30 || 10
The rfdi instruction is used to return from a debug interrupt, or as a means of simultaneously establishing a new context and synchronizing on that new context.
The contents of debug save/restore register 1 are placed into the machine state register. If the new machine state register value does not enable any pending exceptions, then the next instruction is fetched, under control of the new machine state register value from the address DSRR0[0–30]|| 1’b0. If the new machine state register value enables one or more pending exceptions, the interrupt associated with the highest priority pending exception is generated; in this case the value placed into save/restore register 0 or critical save/restore register 0 by the interrupt processing mechanism is the address of the instruction that would have been executed next had the interrupt not occurred (that is, the address in debug save/restore register 0 at the time of the execution of the rfdi).
Execution of this instruction is privileged and context synchronizing.
Special registers altered:
• MSR
When the debug functionality is disabled (HID0[DAPUEN] = 0), this instruction is treated as an illegal instruction.
se_rfdi se_rfdi
Return From Debug Interrupt se_rfdi
MSR ←DSRR1
PC ←DSRR032:62 || 0b0
The rfdi or se_rfdi instruction is used either to return from a debug interrupt or as a means of simultaneously establishing a new context and synchronizing on that new context.
19 / / / 0 0 0 0 1 0 0 1 1 1 0
0 5 6 20 21 30 31
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
0 15
The contents of debug save/restore register 1 are placed into the machine state register. If the new machine state register value does not enable any pending exceptions, then the next instruction is fetched, under control of the new machine state register value from the address DSRR0[32–62]|| 0b0. If the new machine state register value enables one or more pending exceptions, the interrupt associated with the highest priority pending exception is generated; in this case the value placed into save/restore register 0 or critical save/restore register 0 by the interrupt processing mechanism is the address of the instruction that would have been executed next had the interrupt not occurred (that is, the address in debug save/restore register 0 at the time of the execution of the rfdi or se_rfdi).
Execution of this instruction is privileged and context synchronizing.
Special registers altered:
• MSR
When the debug functionality is disabled (HID0[DAPUEN] = 0), this instruction is treated as an illegal instruction.
3.11.1 Debug Notify Halt Instructions
The dnh, e_dnh, and se_dnh instructions provide a bridge between the execution of instructions on the core in a non-halted mode and an external debug facility. dnh, e_dnh, and se_dnh allows software to transition the core from a running state to a debug halted state if enabled by an external debugger. dnh provides the external debugger with bits reserved in the instruction itself to pass additional information.
When the e200z4 CPU enters a debug halted state due to a dnh, e_dnh, or se_dnh instruction, the instruction is stored in the CPUSCR[IR] portion and the CPUSCR[PC] value points to the instruction.
Prior to exiting the debug halted state, the external debugger should update the CPUSCR to point past the dnh, e_dnh, or se_dnh instruction.
Note that the dnh instruction is only available in the Power ISA embedded category instruction pages, and the e_dnh and se_dnh instructions are only available in VLE instruction pages.
dnh dnh
Debugger Notify Halt
dnh dui, duis
if EDBCR[DNH_EN] = 1 then
implementation dependent register ¨ dui halt processor
else
illegal instruction exception
0 5 6 10 11 15 16 20 21 30 31
0 1 0 0 1 1 dui duis 0 0 1 1 0 0 0 1 1 0 /
Execution of the dnh instruction causes the processor to halt if the external debug facility has enabled such action by previously setting the EDBCR[DNH_EN] bit. If the processor is halted, the contents of the dui field are provided to the external debug facility to identify the reason for the halt.
If EDBCR[DNH_EN] has not been previously set by the external debug facility, executing the dnh instruction produces an illegal instruction exception.
The duis field is provided to pass additional information about the halt, but requires that actions be performed by the external debug facility to access the dnh instruction to read the contents of the field.
The dnh instruction is not privileged, and executes the same regardless of the state of MSR[PR].
Whether the processor is in IDM or EDM mode has no effect on the execution of the dnh instruction.
Other registers altered:
• None
NOTE
After the dnh instruction has executed, the instruction itself can be read back by the Illegal Instruction Interrupt handler or the external debug facility if the contents of the dui and duis field are of interest. If the
processor entered the Illegal Instruction Interrupt handler, software can use SRR0 to obtain the address of the dnh instruction which caused the handler to be invoked. If the processor is halted in debug mode, the external debug facility can access the CPUSCR register to obtain the dnh instruction which caused the processor to halt.
e_dnh e_dnh
Debugger Notify Halt
e_dnh dui, duis
if EDBCR[DNH_EN] = 1 then
implementation dependent register ¨ dui halt processor
else
illegal instruction exception
Execution of the e_dnh instruction causes the processor to halt if the external debug facility has enabled such action by previously setting the EDBCR[DNH_EN] bit. If the processor is halted, the contents of the dui field are provided to the external debug facility to identify the reason for the halt.
If EDBCR[DNH_EN] has not been previously set by the external debug facility, executing the e_dnh instruction produces an illegal instruction exception.
0 5 6 10 11 15 16 20 21 30 31
0 1 1 1 1 1 dui duis 0 0 0 1 1 0 0 0 0 1 /
The duis field is provided to pass additional information about the halt, but requires that actions be performed by the external debug facility to access the e_dnh instruction to read the contents of the field.
The e_dnh instruction is not privileged; it executes the same regardless of the state of MSR[PR].
Whether the processor is in IDM or EDM mode has no effect on the execution of the e_dnh instruction.
Other registers altered:
• None
se_dnh se_dnh
Debugger Notify Halt se_dnh
if EDBCRDNH_EN = 1 then
halt processor else
illegal instruction exception
Execution of the se_dnh instruction causes the processor to halt if the external debug facility has enabled such action by previously setting the EDBCR[DNH_EN] bit.
If EDBCR[DNH_EN] has not been previously set by the external debug facility, executing the se_dnh instruction produces an illegal instruction exception.
The se_dnh instruction is not privileged; it executes the same regardless of the state of MSR[PR].
Whether the processor is in IDM or EDM mode has no effect on the execution of the se_dnh instruction.
Other registers altered:
• None