Exception Recognition and Priorities

The following list of exception categories describes how the e200 handles exceptions up to the point of signaling the appropriate interrupt to occur. Instruction completion is defined as updating all architectural registers associated with that instruction as necessary and then removing the instruction from the pipeline.

• Interrupts caused by asynchronous events (exceptions). These exceptions are further distinguished by whether they are maskable and recoverable.

— Asynchronous, non-maskable, non-recoverable:

– System reset by assertion of p_reset_b

Has highest priority and is taken immediately regardless of other pending exceptions or recoverability. (Includes watchdog timer reset control and debug reset control)

— Asynchronous, non-maskable, possibly non-recoverable:

– Non-maskable interrupt by assertion of p_nmi_b

Has priority over any other pending exception except system reset conditions.

Recoverability is dependent on whether MCSRR0/1 are holding essential state info and are overwritten when the NMI occurs.

— Asynchronous, maskable/non-maskable, recoverable/non-recoverable:

– Machine check interrupt

Has priority over any other pending exception except system reset conditions.

Recoverability is dependent on the source of the exception.

— Asynchronous, maskable, recoverable:

– External Input, Fixed-Interval Timer, Decrementer, Critical Input, Unconditional Debug, External Debug Event, Debug Counter Event, and Watchdog Timer interrupts

Before handling this type of exception, the processor needs to reach a recoverable state. A maskable recoverable exception will remain pending until taken or cancelled by software.

• Synchronous, non instruction-based interrupts. The only exception is this category is the Interrupt Taken debug exception, recognized by an interrupt taken event. It is not considered

instruction-based but is synchronous with respect to the program flow.

— Synchronous, maskable, recoverable:

– Interrupt Taken debug event.

The machine will be in a recoverable state due to the state of the machine at the context switch triggering this event.

• Instruction-based interrupts. These interrupts are further organized by the point in instruction processing in which they generate an exception.

ESR SPE, [VLEMI]. All other bits cleared.

MCSR Unchanged

DEAR Unchanged

Vector IVPR_0–15 || IVOR34_16–27 || 4b0000

Table 5-33. SPE Floating-point Round Interrupt—Register Settings (Continued)

— Instruction Fetch:

– Instruction Storage, Instruction TLB, and Instruction Address Compare debug exceptions.

Once these types of exceptions are detected, the excepting instruction is tagged. When the excepting instruction is next to begin execution and a recoverable state has been reached, the interrupt is taken. If an event prior to the excepting instruction causes a redirection of execution, the instruction fetch exception is discarded (but may be encountered again).

— Instruction Dispatch/Execution:

– Program, System Call, Data Storage, Alignment, Floating-point Unavailable, SPE

Unavailable, Data TLB, EFP Floating-point Data, EFP Floating-point Round, Debug (Trap, Branch Taken, Ret) interrupts.

These types of exceptions are determined during decode or execution of an instruction. The exception remains pending until all instructions before the exception causing instruction in program order complete. The interrupt is then taken without completing the

exception-causing instruction. If completing previous instructions causes an exception, that exception takes priority over the pending instruction dispatch/execution exception, which is discarded (but may be encountered again when instruction processing resumes).

— Post-Instruction Execution

– Debug (Data Address Compare, Instruction Complete) interrupt.

These Debug exceptions are generated following execution and completion of an instruction while the event is enabled. If executing the instruction produces conditions for another type of exception with higher priority, that exception is taken and the post-instruction exception is discarded for the instruction (but may be encountered again when instruction processing resumes)

5.8.1 Exception Priorities

Exceptions are prioritized as described in Table 5-34. Some exceptions may be masked or imprecise which will affect their priority. Non-maskable exceptions, such as reset and machine check, may occur at any time and are not delayed even if an interrupt is being serviced; thus state information for any interrupt may be lost. Reset and certain machine checks are non-recoverable.

Table 5-34. e200 Exception Priorities

Priority Exception Cause IVOR

Asynchronous Exceptions

0 System reset Assertion of p_reset_b, Watchdog Timer Reset Control, or Debug

Reset Control none

1

Machine check

Assertion of p_mcp_b, assertion of p_nmi_b, Cache Parity errors, exception on fetch of first instruction of an interrupt handler, external bus errors

1

2 — —

3¹ Debug:

1. Assertion of p_ude (Unconditional Debug Event)

2. Assertion of p_devt1 and event enabled (External Debug Event 1)

3. Assertion of p_devt2 and event enabled (External Debug Event 2)

4. Debug Counter 1 exception 5. Debug Counter 2 exception

6. Imprecise Debug Event (event imprecise due to previous higher priority interrupt

15

4¹ Critical Input Assertion of p_critint_b 0

5¹ Watchdog Timer Watchdog Timer first enabled time-out 12

6¹ External Input Assertion of p_extint_b 4

7¹

Fixed-Interval Timer Posting of a FIT exception in TSR due to programmer-specified bit transition in the Time Base register

11

8¹

Decrementer Posting of a Decrementer exception in TSR due to programmer-specified Decrementer condition

Instruction address compare match for enabled IAC debug event and DBCR0_IDM asserted

15

11 ITLB Error Instruction translation lookup miss in the TLB 14

12

Instruction Storage

1. Access control.

2. Byte ordering due to misaligned instruction across page boundary to pages with mismatched VLE bits, or access to page with VLE set, and E indicating little-endian.

3. Misaligned Instruction fetch due to a change of flow to an odd half-word instruction boundary on a Power ISA (non-VLE) instruction page, due to value in LR, CTR, or xSRR0

3

Instruction Dispatch/Execution Interrupts

13 Program:

Illegal Attempted execution of an illegal instruction.

6

14 Program:

Privileged Attempted execution of a privileged instruction in user-mode

6

15 Floating-point Unavailable

Any floating-point unavailable exception condition. 7

SPE Unavailable Any SPE unavailable exception condition. 32

16 Program:

Unimplemented Attempted execution of an unimplemented instruction.

6 Table 5-34. e200 Exception Priorities (Continued)

Priority Exception Cause IVOR

17 Debug:

1.BRT 2.Trap 3.RET 4.CRET

1. Attempted execution of a taken branch instruction 2. Condition specified in tw or twi instruction met.

3. Attempted execution of a rfi instruction.

4. Attempted execution of an rfci instruction.

Note: Exceptions requires corresponding debug event enabled, MSR[DE] = 1, and DBCR0[IDM] = 1.

15

18 Program:

Trap Condition specified in tw or twi instruction met and not trap debug.

6

System Call Execution of the System Call (sc, se_sc) instruction. 8 EFP Floating-point

Data

Denormalized, NaN, or Infinity data detected as input or output, or underflow, overflow, divide by zero, or invalid operation in the EFP APU.

33

EFP Round Inexact Result 34

19 Alignment lmw, stmw, lwarx, or stwcx. not word aligned.

lharx, or sthcx. not half word aligned.

dcbz

5

20 Debug:

Debug with

concurrent DTLB or DSI exception:

1.DAC/IAC linked² 2.DAC unlinked²

Debug with concurrent DTLB or DSI exception. DBSR[IDE] also set.

1. Data Address Compare linked with Instruction Address Compare

2. Data Address Compare unlinked

Note: Exceptions requires corresponding debug event enabled, MSR[DE] = 1, and DBCR0[IDM] = 1. In this case, the Debug exception is considered imprecise, and DBSR[IDE] will be set.

Saved PC will point to the load or store instruction causing the DAC event.

15

21 Data TLB Error Data translation lookup miss in the TLB. 13

22

Data Storage

1. Access control.

2. Byte ordering due to misaligned access across page boundary to pages with mismatched E bits.

3. Cache locking due to attempt to execute a icbtls or icblc in user mode with MSR[UCLE] = 0.

2

24 Debug:

1.IRPT 2.CIRPT

1. Interrupt taken (non-critical) 2. Critical Interrupt taken (critical only)

Note: Exceptions requires corresponding debug event enabled, MSR[DE] = 1, and DBCR0[IDM] = 1.

15 Table 5-34. e200 Exception Priorities (Continued)

Priority Exception Cause IVOR

W dokumencie E200Z4 (Stron 196-200)