Tbr: MACSI device asserts ABÐBR to indicate it wishes to perform a transfer. Host asserts ABÐBG. The MACSI de-vice moves to Tpa within the next three clocks.
Tpa: MACSI device drives ABÐA and ABÐAD with the ad-dress, asserts ABÐAS, drives ABÐR/W and ABÐSIZ[2:0], and negates ABÐBR if another transaction is not required.
Td: MACSI device negates ABÐAS, asserts ABÐDEN, and samples ABÐACK and ABÐERR. Slave asserts ABÐACK, drives ABÐERR, drives ABÐAD (with data) when ready.
The MACSI device samples a valid ABÐACK, capturing the read data. Tw states may occur after Td.
Tr: MACSI device negates ABÐR/W, ABÐDEN, and ABÐSIZ[2:0], and releases ABÐA and ABÐAS. Slave deasserts ABÐACK and ABÐERR, and releases ABÐAD.
Single Write
Tbr: MACSI device asserts ABÐBR to indicate it wishes to perform a transfer. Host asserts ABÐBG. The MACSI de-vice moves to Tpa within the next three clocks.
Tpa: MACSI device drives ABÐA and ABÐAD with the ad-dress, asserts ABÐAS, drives ABÐR/W and ABÐSIZ[2:0], and negates ABÐBR if another transaction is not required.
Td: MACSI device negates ABÐAS, asserts ABÐDEN, drives ABÐAD with the write data and starts sampling ABÐACK and ABÐERR. Slave captures ABÐAD data, as-serts ABÐACK, and drives ABÐERR. Tw states may occur after Td if the slave deasserts ABÐACK.
Tr: MACSI device negates ABÐR/W, ABÐDEN, and ABÐSIZ[2:0], and releases ABÐA, ABÐAD, and ABÐAS.
Slave deasserts ABÐACK and ABÐERR and stops driving ABÐAD with data.
TL/F/11705 – 10
FIGURE 6-5. ABus Single Write: Physical AddressingÐ0 w/s, 1 w/s
Obsolete
6.0 Functional Description (Service Engine)
(Continued)TL/F/11705 – 11
FIGURE 6-6. ABus Burst Read: Physical AddressingÐ16 Bytes, 1 w/s Burst Read
Tbr: MACSI device asserts ABÐBR to indicate it wishes to perform a transfer. Host asserts ABÐBG. The MACSI de-vice moves to Tpa within the next three clocks.
Tpa: MACSI device drives ABÐA and ABÐAD with the ad-dress, asserts ABÐAS, drives ABÐR/W and ABÐSIZ[2:0], and negates ABÐBR if another transaction is not required.
Td: MACSI device asserts ABÐDEN, samples ABÐACK and ABÐERR, and increments the address on ABÐA.
Slave asserts ABÐACK, drives ABÐERR, and drives ABÐAD (with data) when ready. MACSI device samples a valid ABÐACK to capture the read data. Tw states may occur after Td. Td state is repeated four or eight times (ac-cording to the burst size). If SIMR1.ASMe0, the MACSI device negates ABÐAS in the last Td cycle. If SIMR1.ASM e1, the MACSI device will negate ABÐAS in the first Td cycle.
Tr: MACSI device negates ABÐR/W, ABÐDEN, and ABÐSIZ[2:0], and releases ABÐA and ABÐAS. Slave deasserts ABÐACK and ABÐERR and releases ABÐAD.
Burst Write
Tbr: MACSI device asserts ABÐBR to indicate it wishes to perform a transfer. Host asserts ABÐBG. The MACSI de-vice moves to Tpa within the next three clocks.
Tpa: MACSI device drives ABÐA and ABÐAD with the ad-dress, asserts ABÐAS, drives ABÐR/W and ABÐSIZ[2:0], and negates ABÐBR if another transaction is not required.
Td: MACSI device asserts ABÐDEN, drives ABÐAD with the write data, samples ABÐACK and ABÐERR, and incre-ments the address on ABÐA. Slave captures ABÐAD data, asserts ABÐACK, drives ABÐERR. MACSI device samples a valid ABÐACK. Tw states may occur after Td. Td state is repeated as required for the complete burst. If SIMR1.ASM e0, the MACSI device negates ABÐAS in the last Td cy-cle. If SIMR1.ASMe1, the MACSI device will negate ABÐAS in the first Td cycle.
Tr: MACSI device negates ABÐR/W, ABÐDEN, and ABÐSIZ[2:0], releases ABÐA and ABÐAS, and stops driv-ing ABÐAD with data. Slave deasserts ABÐACK and ABÐERR.
Obsolete
6.0 Functional Description (Service Engine)
(Continued)TL/F/11705 – 12
FIGURE 6-7. ABus Burst Write: Physical AddressingÐ16 Bytes, 1 w/s 6.4.4 Virtual Addressing Bus Transactions
Single Read
Tbr: MACSI device asserts ABÐBR to indicate it wishes to perform a transfer. Host asserts ABÐBG. The MACSI de-vice moves to Tva within the next three clocks, and then drives ABÐA and ABÐAD.
Tva: MACSI device drives ABÐA and ABÐAD with the vir-tual address for one clock, negates ABÐAS, asserts ABÐR/W, drives ABÐSIZ[2:0], and negates ABÐBR if an-other transaction is not required.
Tmmu: Host MMU performs an address translation during this clock.
Tpa: Host MMU drives ABÐAD with the translated (physi-cal) address.
Td: MACSI device negates ABÐAS, asserts ABÐDEN, and samples ABÐACK and ABÐERR. Slave asserts ABÐACK, drives ABÐERR, and drives ABÐAD (with data) when ready. MACSI device samples a valid ABÐACK, and cap-tures the read data. Tw states may occur after Td.
Tr: MACSI device negates ABÐR/W, ABÐDEN, and ABÐSIZ[2:0], and releases ABÐA and ABÐAS. Slave deasserts ABÐACK and ABÐERR and releases ABÐAD.
Single Write
Tbr: MACSI device asserts ABÐBR to indicate it wishes to perform a transfer. Host asserts ABÐBG. The MACSI de-vice moves to Tva within the next three clocks, and then drives ABÐA and ABÐAD.
Tva: MACSI device drives ABÐA and ABÐAD with the vir-tual address for one clock, negates ABÐAS, negates ABÐR/W, and drives ABÐSIZ[2:0].