Hardware Implementation-Dependent Registers

Hardware implementation-dependent registers 0 and 1 (HID0 and HID1) are configuration registers to control various processor and system functions.

2.13.1 Hardware Implementation-Dependent Register 0 (HID0) HID0, shown in Figure 2-40, is used for various configuration and control functions.

HID0 fields are described in Table 2-25.

1 1 - - - - - - - - - - - - - - - - - 1

-1 1 - - - - - - - - - - - - - - - - - - 1 DBCR0[FT]

1 Note: DBSR[MRR] is always updated by p_reset_b, regardless of the value of DBCR0[EDM] or DBERC0[IDM]

2 Note that software is given write access to all counter 1 control events and triggers regardless of whether software owns these events. It is considered a programming error to enable counter or trigger events in DBCR3 which are not

"owned" by software, and operational results of the counter(s) are undefined if programmed.

3 Note that software is given write access to all counter 2 control events regardless of whether software owns these events. It is considered a programming error to enable counter events in DBCR3 which are not "owned" by software, and operational results of the counter(s) are undefined if programmed.

32 33 37 38 39 40 41 42 43 45 46 47

Field EMCP — BPRED DOZE NAP SLEEP — ICR NHR

Reset All zeros

R/W R/W

48 49 50 51 52 53 54 55 56 63

— TBEN SEL_TBCLK DCLREE DCLRCE CICLRDE MCCLRDE DAPUEN —

Reset All zeros

R/W R/W

SPR SPR 1008

Figure 2-40. Hardware Implementation-Dependent Register 0 (HID0)

Table 2-24. DBERC0 Resource Control (continued)

DBCR0[EDM] DBERC0[IDM] DBERC0[RST] DBERC0[ICMP] DBERC0[BRT] DBERC0[IRPT] DBERC0[TRAP] DBERC0[IAC1] DBERC0[IAC2] DBERC0[IAC3] DBERC0[IAC4] DBERC0[DAC1] DBERC0[DAC2] DBERC0[DEVT1] DBERC0[DEVT2] DBERC0[DCNT1] DBERC0[DCNT2] DBERC0[CIRPT] DBERC0[CRET] DBERC0[BKPT] DBERC0[FT]

Name

Software Accessible via mtspr,

affected by p_reset_b

Table 2-25. HID0 Field Descriptions

Bits Name Description

32 EMCP Enable machine check signal (p_mcp_b). Used to mask out further machine check exceptions caused by assertion of p_mcp_b.

0 p_mcp_b is disabled.

1 p_mcp_b is enabled. If MSR[ME] = 0, asserting p_mcp_b causes checkstop. If MSR[ME] = 1, asserting p_mcp_b causes a machine check interrupt.

33–37 — Reserved, should be cleared.

38–39 BPRED Branch prediction (acceleration) control. Controls BTB lookahead for branch acceleration. Note that for branches with AA = 1, the msb of the displacement field is still used to indicate forward/backward, even though the branch is absolute. Used in conjunction with BUCSR.

00 Branch acceleration is enabled.

01 Branch acceleration is disabled for backward branches.

10 Branch acceleration is disabled for forward branches.

11 Branch acceleration is disabled for both branch directions.

40 DOZE Doze power management mode. Doze mode is invoked by setting MSR[WE] while DOZE = 1.

0 Doze mode is disabled.

1 Doze mode is enabled.

41 NAP Nap power management mode. Nap mode is invoked by setting MSR[WE] while NAP=1.

0 Nap mode is disabled.

1 Nap mode is enabled.

42 SLEEP Sleep power management mode. Sleep mode is invoked by setting MSR[WE] while WE=1. Only one of DOZE, NAP, or SLEEP should be set for proper operation.

0 Sleep mode is disabled.

1 Sleep mode is enabled.

43–45 — Reserved, should be cleared.

46 ICR Interrupt inputs clear reservation.

0 External and critical input interrupts do not affect reservation status.

1 External and critical input interrupts clear an outstanding reservation.

47 NHR Not hardware reset. Provided for software use. Set anytime by software, cleared by reset.

0 Indicates a reset to a reset exception handler if software has previously set this bit.

1 Indicates to a reset exception handler that there was no reset if software has previously set this bit.

48 — Reserved, should be cleared.

49 TBEN Time base enable. Used to enable the time base and decrementer.

0 Time base is disabled.

1 Time base is enabled.

50 SEL_TBCLK Select time base clock. Selects the time base clock source. This bit must altered while the time base is disabled to prevent counter glitches. Timer interrupts should be disabled beforehand, and TBL and TBU are reinitialized after a change of time base clock source.

0 Time base is based on processor clock.

1 Time base is based on the p_tbclk input.

51 DCLREE Debug interrupt clears MSR[EE]. Controls whether debug interrupts force external input interrupts to be disabled, or whether they remain unaffected.

0 MSR[EE] unaffected by debug interrupt.

1 MSR[EE] cleared by debug interrupt.

2.13.2 Hardware Implementation-Dependent Register 1 (HID1)

The HID1 register is used for bus configuration and system control. HID1 is shown in Figure 2-41.

HID1 fields are described in Table 2-26.

52 DCLRCE Debug interrupt clears MSR[CE]. Controls whether debug interrupts force critical interrupts to be disabled, or whether they remain unaffected.

0 MSR[CE] unaffected by debug interrupt.

1 MSR[CE] cleared by debug Interrupt.

53 CICLRDE Critical interrupt clears MSR[DE]. Controls whether certain critical interrupts (critical input, watchdog timer) force debug interrupts to be disabled, or whether they remain unaffected. Machine check interrupts have a separate control bit.

0 MSR[DE] unaffected by critical class interrupt.

1 MSR[DE] cleared by critical class interrupt.

If critical interrupt debug events are enabled (DBCR0[CIRPT] is set, which should only be done when the debug APU is enabled), and MSR[DE] is set at the time of a critical interrupt (critical input, watchdog timer), a debug event is generated after the critical interrupt handler has been fetched, and the debug handler is executed first. In this case, DSRR0[DE] will have been cleared, such that after returning from the debug handler, the critical interrupt handler will not be run with MSR[DE] enabled.

54 MCCLRDE Machine check interrupt clears MSR[DE]. Controls whether machine check interrupts force debug interrupts to be disabled or are unaffected. If critical interrupt debug events are enabled (DBCR0[CIRPT]

is set, which should only be done when the debug APU is enabled), and MSR[DE] is set at the time of a machine check interrupt, a debug event is generated after the machine check interrupt handler is fetched, and the debug handler executes first. In this case, DSRR0[DE] is cleared so that after returning from the debug handler, the machine check handler cannot be run if MSR[DE] = 1.

0 MSR[DE] unaffected by machine check interrupt.

1 MSR[DE] cleared by machine check interrupt.

55 DAPUEN Debug APU enable. Controls whether the debug APU is enabled.

0 Debug APU disabled. Debug interrupts use the critical interrupt resources: CSRR0/CSRR1 and rfci;

rfdi is treated as an illegal instruction. DCLREE, DCLRCE, CICLRDE, and MCCLRDE settings are ignored and are assumed to be ones.

1 Debug APU enabled. Debug interrupts use DSRR0/DSRR1 for saving state and rfdi is available for returning from a debug interrupt.

Read and write access to DSRR0/DSRR1 via mfspr and mtspr is not affected by this bit.

56–63 — Reserved, should be cleared.

32 55 56 57 62 63

Field — ATS – ARD

Reset All zeros

R/W R/W

SPR SPR 1009

Figure 2-41. Hardware Implementation-Dependent Register 1 (HID1) Table 2-25. HID0 Field Descriptions (continued)

Bits Name Description

Table 2-26. HID1 Field Descriptions

Bits Name Description

32–55 — Reserved, should be cleared.

56 ATS Atomic status (read-only). Indicates state of the reservation bit in the load/store unit. See Section 3.7,

“Memory Synchronization and Reservation Instructions.”

57–62 — Reserved, should be cleared.

63 ARD Address retraction disable.

0 Address retraction enabled.

1 Address retraction disabled.

Controls Address Retraction operation. For details, see Section 7.5.3, “Address Retraction.”