The LERIC8 was tested for IEEE 802.3 conformance in a re-peater system. Without any resistive loading on the RTX and REQ pins, the repeater passed all conformance tests with the exception of Peak Differential Output Voltage (VOD into a resistive load). With only one twisted pair port loaded and transmitting a packet, with the system running at 5.25 V in a 0oC chamber, the output violated the Peak Differential Out-put Voltage (VOD into a resistive load) marginally at the upper limit. With all eight twisted pair ports loaded and transmitting, and with the system running at 4.75 V in a 80oC chamber, the output violated the Peak Differential Output Voltage (VOD into a resistive load) marginally at the lower limit. Perfor-mance is also dependent on PCB layout.
The violation of this specification under these conditions will not affect a normal network. The LERIC8 passes the IEEE Output Waveform with Scaling Voltage template and the in-verted template, both of which specify VOD at the end of a ca-ble. The LERIC8 has also undergone endurance testing in various platforms and has not shown any loss of data.
The RTX and REQ pins can be used to tune the internal transmit filter and wave shaping circuitry. The RTX input can be used to adjust the differential voltage (VOD) of all of the output drivers. By placing a resistor between RTX and VCC, the peak-to-peak voltage will be increased. Conversely, con-necting the resistor to GND will decrease VOD.
The REQ input can be used to adjust the shape of the wave-form for all outputs. By placing a resistor between REQ and VCC, the amplitude of the pre-emphasis waveform will be in-creased. Conversely, connecting the resistor to GND will de-crease the amplitude.
Caution should be taken when using RTX and REQ to make adjustments. The following IEEE parameters may be ad-versely affected by adjusting the amplitude or shape of the transmitted waveform, as well as PCB layout and design:
Peak Differential Output Voltage, Harmonic Content, Output waveform with Scaling of Voltage template, Output Waveform with Scaling of Voltage inverted template, TD circuit Differen-tial Output Impedance, Transmit Output Timing Jitter with Ca-ble Model, and Transmit Output Timing Jitter without CaCa-ble Model.
Figure 10. Connection Diagram for Cascading
/ACKI /ACKO
IRD /IRE IRC /COLN /ACTN /ANYXN /ACKI /ACKO
IRD /IRE IRC /COLN /ACTN /ANYXN /ACKI /ACKO
IRD /IRE IRC /COLN /ACTN /ANYXN
4.7K
N.C.
STATUS LEDS STATUS LEDS STATUS LEDS
680
PARTITION/LINK LEDS TRAFFIC LEDS GLOBAL LEDS
680
680 680
PARTITION/LINK LEDS
PARTITION/LINK LEDS
Obsolete
Absolute Maximum Ratings
DC Specifications
TA = 0°C to 70°C, V
CC = 5V± 5% unless otherwise specified
AUI (PORT 0)
10BASE-T (PORTS 1-8)
Note 1: This value is the absolute maximum, and not intended to be used to calculate case temperature. A value of 1.8W can be used for the purpose of device heat calculations.
Note 2: This parameter is guaranteed by design and is not tested.
Note 3: The operation in Reduced mode is not gauranteed below 300 mV.
Supply Voltage (V
CC) -0.5V to 7.0V
DC Input Voltage (VIN) -0.5V to VCC + 0.5V DC Output Voltage (VOUT) -0.5V to VCC + 0.5V Power Dissipation (PD) (Note 1) 4.5 W Storage Temperature Range (TSTG) -65°C to 150°C Lead Temp. (TL) (Soldering, 10 sec) 260°C ESD Rating
(RZAP = 1.5k, CZAP = 120 pF)
2.0 kV
Symbol Description Conditions Min Typ Max Units
PROCESSOR, LED, AND INTER-LERIC INTERFACES
VOH Minimum High Level Output Voltage I
OH= -8 mA 3.5 V
VOL Minimum Low Level Output Voltage I
OL = 8 mA 0.4 V
VIH Minimum High Level Input Voltage 2.0 V
VIL Maximum Low Level Input Voltage 0.8 V
IIN Input Current V
IN = V
CCor GND -1.0 1.0 µA
IOZ Maximum TRI-STATE Output Leakage Current
VOUT = V
CCor GND -10 10 µA
ICC Average supply current V
IN = V
CCor GND VCC= 5.25V
570 800 mA
VOD Differential Output Voltage (TX±) 78Ω Termination ±550 ±1200 mV VOB Differential Output Voltage Imbalance (TX ±)
(Note 2)
78Ω Termination 40 mV
VU Undershoot Voltage (TX±) (Note 2) 78Ω Termination 80 mV
VDS Differential Squelch Threshold (RX±, CD±) -175 -300 mV
VCM Differential Input Common Mode Voltage (RX±, CD±) (Note 2)
0 5.5 V
VRON Minimum Receive Squelch Threshold:
Normal Mode Reduced Mode
±300 (Note 3)
±585
±340
mV mV
Recommended Operating Conditions
Note: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits.
Supply Voltage (VCC) 5 Volts + 5%
Ambient Temperature (TA) 0 to 70°C
Obsolete
9.0 Switching Characteristics
9.1 PORT ARBITRATION
Note: Timing valid with no receive or collision activities.
9.2 RECEIVE - AUI PORT
Receive activity propagation start up and end delays for the AUI port.
Note: /ACKI assumed high.
Note 1: This time includes EOP.
Note 2: This parameter assumes squelch triggers on negative edge of RX data.
Number Symbol Parameter Min Max Units
T1 T2
ackilackol ackihackoh
/ACKI Low to /ACKO Low /ACKI High to /ACKO High
26 23
ns ns
/ A C K O
/ A C K I
T1 T2
Number Symbol Parameter Min Max Units
T3a T4a
rxaackol rxiackoh
RX Active to /ACKO Low (Note 2) RX Inactive to /ACKO High (Note 1)
66 235
ns ns T5a
T6a
rxaactnl rxiactnh
RX Active to /ACTN Low (Note 2) RX Inactive to /ACTN High (Note 1)
75 235
ns ns
R X
/ A C T N
/ A C K O
T3a
T5a T6a
T4a
Obsolete
9.3 RECEIVE - 10BASE-T PORTS
Receive activity propagation start up and end delays for 10BASE-T ports.
Note: /ACKI assumed high.
Note 1: This time includes EOP.
9.4 TRANSMIT - AUI PORT
Transmit activity propagation start up and end delays for the AUI port.
Note: /ACKI assumed high.
Number Symbol Parameter Min Max Units
T3t T4t
rxaackol rxiackoh
RX Active to /ACKO Low
RX Inactive to /ACKO High (Note 1)
300 280
ns ns T5t
T6t
rxaactnl rxiactnh
RX Active to /ACTN Low
RX Inactive to /ACTN High (Note 1)
300 280
ns ns
Number Symbol Parameter Min Max Units
T15a actnltxa /ACTN Low to TX Active 675 ns
T16a clkitxa CLOCK in to TX Active 45 ns
R X
/ A C T N
/ A C K O
T3t
T5t T6t
T4t
/ A C T N
T X
T15 a CLOCK
T16 a
Obsolete
9.0 Switching Characteristics
(Continued)9.5 TRANSMIT - 10BASE-T PORTS
Receive activity propagation start up and end delays 10BASE-T ports.
Note: /ACKI assumed high.
9.6 COLLISION - AUI PORT
Collision activity propagation start up and end delays for the AUI port.
9.6.1 Transmit Collisions
Note 1: TX collision extension has already been performed and no other port is driving /ANYXN.
Note 2: Includes TW2.
Number Symbol Parameter Min Max Units
T15t actnltxa /ACTN Low to TX Active 790 ns
T16t clkitxa CLOCK in to TX Active 45 ns
Number Symbol Parameter Min Max Units
T30a T31a
cdaanyxnl cdianyxnh
CD Active to /ANYXN Low
CD Inactive to /ANYXN High (Note 1,2)
85 285
ns ns
/ A C T N
T X
T15 t T16 t CLOCK
/ A N Y X N
T30a T31a
C D
Obsolete
9.6.2 Receive Collisions
Note 1: Reception ended before /COLN goes high.
9.7 COLLISION - 10BASE-T PORTS
Collision activity propagation start up and end delays for 10BASE-T ports
Note 1: TX collision extension has already been performed and no other port is asserting /ANYXN.
Number Symbol Parameter Min Max Units
T32a T33a
cdacolna cdicolni
CD Active to /COLN Low CD Inactive to /COLN High
75 215
ns ns T39
T40
colnljs colnhje
/COLN Low to Start of JAM /COLN High toEnd of JAM (Note 1)
400 585
ns ns
Number Symbol Parameter Min Max Units
T30t T31t
colaanyl colianyh
Collision Active to /ANYXN Low
Collision Inactive to /ANYXN High (Note 1)
800 450
ns ns
/ C O L N
T32 a T33 a
C D
T X DATA JAM
T39 T40
/ A N Y X N
T30 t T31 t
T X
R X Obsolete
9.0 Switching Characteristics
(Continued)9.8 COLLISION - ALL PORTS - INTER-LERIC BUS
9.9 COLLISION - ALL PORTS - ONE PORT LEFT
Note: 96 bits of JAM have already been propagated.
Number Symbol Parameter Min Max Units
T34 T35 T38
anylmin anyhtxai anylsj
/ANYXN Low time
/ANYXN High to TX to all Inactive /ANYXN Low to Start of JAM
960
20 370
565
ns ns ns
Number Symbol Parameter Min Max Units
T36 T37
actnhtxi anyhtxoi
/ACTN High to TX Inactive
/ANYXN High to TX 'One Port Left' Inactive 20
410 200
ns ns
/ A N Y X N
T34 / A C T N
T X
T35
DATA JAM
T38
/ A N Y X N / A C T N
T X
T36
T X one port left
Obsolete
T379.10 RESET
** /MLOAD_INT is the internal signal which is delayed 5 cycles from the external /MLOAD signal
9.11 LED STROBE
Number Symbol Parameter Min Max Units
T61 resdats Data Setup 20 ns
T62 resdath Data Hold 20 ns
T63 reslbufl /MLOAD Low to /BUFEN Low 35 ns
T64 reshbufh /MLOAD High to /BUFEN High 35 ns
T65 resw /MLOAD Width 800 ns
D( 7 : 0 )
T65
T61
T62 / MLOAD
T63 T64 / B U F E N
** / MLOAD_INT
Number Symbol Parameter Min Max Units
T66 stradrs Strobe Address Setup 70 100 ns
T67 strdats Strobe DATA SETUP 35 55 ns
T68 strdath Strobe Data Hold 145 165 ns
T69 strw Strobe Width 30 65 ns
RA( 4:1 ) (address)
D( 3: 0 ) (data) / S T R
T66
T67 T68
T69 RA( 0 )
Obsolete
9.0 Switching Characteristics
(Continued)9.12 REGISTER READ
Note: Minimum high time between read/write cycles is 100 ns.
Number Symbol Parameter Min Max Units
T80 T81
rdadrs rdadrh
Address Setup from /BUFEN Low Address Hold after /RD High
0 0
85 ns
ns T82
T83
rdlbufl rdhbufh
/RD Low to /BUFEN Low /RD High to /BUFEN High
80 355
35
ns ns T84
T85
bufldatv rddath
/BUFEN Low to Data Valid
Data Hold After /RD High 60
190 ns
ns T86
T87
rdlrdyl rdhrdyh
/RD Low to /RDY Low /RD High to /RDY High
340 585
30
ns ns
T88 rdw /RD Width 650 ns
T89 rdtr /RD Low to D(3:0) TRI-STATE 80 355 ns
/ R D
/ B U F E N
T81
T82 T83
T88
T85 D( 3: 0 )
(data)
T84 RA( 4:0 )
(address) T89 T80
/ R DY T86
T87
Obsolete
9.13 REGISTER WRITE
Note: Minimum high time between read/write cycles is 100 ns.
Number Symbol Parameter Min Max Units
T90 T91
wradrs wradrh
Address Setup from /BUFEN Low Address Hold after /WR High
0 0
14 ns
ns T92
T93
wrlbufl wrhbufh
/WR Low to /BUFEN Low /WR High to /BUFEN High
80 355
35
ns ns T94
T95
wradatv wrdath
/BUFEN Low to Data Valid
Data Hold After /WR High 0
160 ns
ns T96
T97
wrlrdyl wrhrdyh
/WR Low to /RDY Low /WR High to /RDY High
340 585
30
ns ns
T98 wrw /WR Width 650 ns
T99 wrtr /WR Low to D(3:0) TRI-STATE 80 355 ns
T96 / W R
/ B U F E N
T91
T92 T93
T98
T95 D( 3:0 )
(data)
T94 RA( 4:0 )
(address) T99 T90
/ R DY T96
T97
Obsolete
9.0 Switching Characteristics
(Continued)9.14 INTER-LERIC BUS (PACKET OUTPUT)
9.15 INTER-LERIC BUS (PACKET INPUT)
Number Symbol Parameter Min Max Units
T101 ircoh IRC Output Duty Cycle High Time 40 60 %
T102 ircol IRC Output Duty Cycle Low Time 40 60 %
T103 ircoc IRC Output Cycle Time 90 110 ns
T105 actnolireol /ACTN Output Low to /IRE Output Low 500 ns
T106 ireolirca /IRE Output Low to IRC Active 1.8 µs
T107 irdov IRD Output Valid from IRC 10 ns
T108 irdos IRD Output Stable Valid Time 90 ns
T109 ircohireh IRC Output High to /IRE High 30 70 ns
T110 ircclks Number of IRCs after /IRE high 5 clks
T103 T108 T101
T107
T110 //
//
//
//
/ I R E
I R C
I R D
T102 //
//
//
//
//
/ A C T N //
//
//
T106 T105
T109
Number Symbol Parameter Min Max Units
T111 ircih IRC Input High Time 20 ns
T112 ircil IRC Input Low Time 20 ns
T114 irdisirc IRD Input Setup to IRC 5 ns
T115 irdihirc IRD Input Hold from IRC 10 ns
T116 ircihireh Set Up Time of the Rising Edge of IRE to the Rising Edge of IRC for End of Packet Generation
25 75 ns
T111 / I R E
I R C
I R D
T114 T112
T115
T116 //
//
// //
//
//
//
//
Obsolete //
10.1 GENERAL TEST CONDITIONS
All AUI specifications are valid only if the mandatory isolation transformer is employed and all differential signals are mea-sured at the AUI connector (not at the DP83959 LERIC8 di-rectly).
Note 1: 100 pF, includes scope and test jig capacitance.
Note 2: S1 = Open during timing tests for push pull outputs.
S1 = VCC for VOL test.
S1 = GND for VOH test.
S1 = VCC for High Impedance to active low, and active low to High Impedance measurements.
S1 = GND for High Impedance to active high, and active high to High Impedance measurements.
10.2 CAPACITANCE
TA = 25°C, f = 1 MHz Input Pulse Levels (TTL/CMOS) GND to 3.0VInput Rise and Fall Times (TTL/CMOS)
5 ns
Input and Output
Reference Levels (TTL/CMOS)
1.5V
Input Pulse Levels (Differential) -350 to -1315 mV Input and Output
Reference Levels (Diff.)
50% Point of the Differential TRI-STATE Reference Levels Float (∆V)±0.5V Output Load (SeeFigure below)
Symbol Parameter Typ Units
CIN Input Capacitance 7 pF
COUT Output Capacitance 7 pF
DEVICE UNDER TEST
C (Note 1) R = 2.2 kΩ 0.1µF
S (Note 2) VCC
Obsolete
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to per-form, when properly used in accordance with instructions for use provided in the labeling, can be reasonably ex-pected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor Corporation
Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com
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Customer Response Group Tel: 65-254-4466
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Email: sea.support@nsc.com www.national.com
DP83959 8-P or t Lite Ethernet Repeater Interface Contr oller 11.0 Physical Dimensions
inches (millimeters) unless otherwise notedMolded Plastic Quad Flat Package, JEDEC Order Number DP83959VUL NS Package Number VUL160A
Obsolete
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