Interrupt Registers Defined by Book E This section describes the following registers and their fields:

• Section 2.8.1.1, “Save/Restore Register 0 (SRR0)”

• Section 2.8.1.2, “Save/Restore Register 1 (SRR1)”

• Section 2.8.1.3, “Critical Save/Restore Register 0 (CSRR0)”

• Section 2.8.1.4, “Critical Save/Restore Register 1 (CSRR1)”

• Section 2.8.1.5, “Data Exception Address Register (DEAR)”

• Section 2.8.1.6, “Interrupt Vector Prefix Register (IVPR)”

• Section 2.8.1.7, “Interrupt Vector Offset Registers (IVORs)”

• Section 2.9, “Exception Syndrome Register (ESR)”

60 FUNFE Embedded floating-point underflow exception enable.

0 Exception disabled.

1 Exception enabled. A floating-point data exception is taken if FUNF or FUNFH is set by a floating-point instruction.

61 FOVFE Embedded floating-point overflow exception enable.

0 Exception disabled.

1 Exception enabled. If the exception is enabled, a floating-point data exception is taken if FOVF or FOVFH is set by a floating-point instruction.

62–63 FRMC Embedded floating-point rounding mode control.

00 Round to nearest.

01 Round toward zero.

10 Round toward +infinity.

11 Round toward -infinity.

Table 2-9. SPEFSCR Field Descriptions (continued)

Bits Name Description

2.8.1.1 Save/Restore Register 0 (SRR0)

During a non-critical interrupt, SRR0, shown in Figure 2-11, holds the address of the instruction where the interrupted process should resume. The instruction is interrupt-specific, although for instruction-caused exceptions, the address of the instruction typically causes the interrupt. When rfi executes, instruction execution continues at the address in SRR0. SRR0 and SRR1 are not affected by rfci or rfdi.

2.8.1.2 Save/Restore Register 1 (SRR1)

SRR1, shown in Figure 2-12, is used to save and restore machine state during non-critical interrupts. When a non-critical interrupt is taken, MSR contents are placed into SRR1. When rfi executes, the contents of SRR1 are restored into MSR. SRR1 bits that correspond to reserved MSR bits are also reserved. (See Section 2.4.1, “Machine State Register (MSR)”.) SRR0 and SRR1 are not affected by rfci or rfdi.

Reserved MSR bits can be altered by rfi, rfci, or rfdi.

2.8.1.3 Critical Save/Restore Register 0 (CSRR0)

CSRR0 is used to save and restore machine state during critical interrupts in the same way SRR0 is used for non-critical interrupts: to hold the address of the instruction to which control is passed at the end of the interrupt handler. CSRR0, shown in Figure 2-13, holds the address of the instruction where the interrupted process should resume. The instruction is interrupt-specific; for details, see Chapter 4, “Interrupts and Exceptions.” When rfci executes, instruction execution continues at the address in CSRR0. CSRR0 and CSRR1 are not affected by rfi or rfdi.

32 63

Field Next instruction address

Reset Undefined on m_por assertion, unchanged on p_reset_b assertion

R/W R/W

SPR SPR 26

Figure 2-11. Save/Restore Register 0 (SRR0)

32 63

Field MSR state information

Reset Undefined on m_por assertion, unchanged on p_reset_b assertion

R/W R/W

SPR SPR 27

Figure 2-12. Save/Restore Register 1 (SRR1)

2.8.1.4 Critical Save/Restore Register 1 (CSRR1)

CSRR1, shown in Figure 2-14, is used to save and restore machine state during critical interrupts. MSR contents are placed into CSRR1. When rfci executes, the contents of CSRR1 are restored into MSR.

CSRR1 bits that correspond to reserved MSR bits are also reserved. (See Section 2.4.1, “Machine State Register (MSR).”) CSRR0 and CSRR1 are not affected by rfi or rfdi. Reserved MSR bits can be altered by rfi, rfci, or rfdi.

2.8.1.5 Data Exception Address Register (DEAR)

DEAR, shown in Figure 2-15, is loaded with the effective address of a data access (caused by a load, store, or cache management instruction) that results in an alignment, data TLB miss, or data storage interrupt.

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2.8.1.6 Interrupt Vector Prefix Register (IVPR)

The IVPR, shown in Figure 2-16, is used during interrupt processing to determine the starting address for the software interrupt handler. The value contained in the vector offset field of the IVOR selected for a particular interrupt type is concatenated with the value in the IVPR to form an instruction address from which execution is to begin.

32 63

Field Next instruction address

Reset Undefined on m_por assertion, unchanged on p_reset_b assertion

R/W R/W

SPR SPR 58

Figure 2-13. Critical Save/Restore Register 0 (CSRR0)

32 63

Field MSR state information

Reset Undefined on m_por assertion, unchanged on p_reset_b assertion

R/W R/W

SPR SPR 59

Figure 2-14. Critical Save/Restore Register 1 (CSRR1)

32 63

Field Exception address

Reset Undefined on m_por assertion, unchanged on p_reset_b assertion

R/W R/W

SPR SPR 61

Figure 2-15. Data Exception Address Register (DEAR)

IVPR fields are defined in Table 2-10.

2.8.1.7 Interrupt Vector Offset Registers (IVORs)

IVORs, shown in Figure 2-17, hold the quad-word index from the base address provided by the IVPR for each interrupt type.

The IVOR fields are defined in Table 2-11.

32 47 48 63

Field Vector Base —

Reset Undefined on m_por assertion, unchanged on p_reset_b assertion

R/W R/W

SPR SPR 63

Figure 2-16. Interrupt Vector Prefix Register (IVPR)

Table 2-10. IVPR Field Descriptions

Bits Name Description

32–47 Vector Base

Defines the base location of the vector table, aligned to a 64-Kbyte boundary. Provides the high-order 16 bits of the location of all interrupt handlers. IVPR || IVORn values are concatenated to form the address of the handler in memory.

48–63 — Reserved, should be cleared.

32 47 48 59 60 61 63

Field — Vector offset — CS

Reset Undefined on m_por assertion, unchanged on p_reset_b assertion

R/W R/W

SPR (See Table 2-12.)

Figure 2-17. Interrupt Vector Offset Registers (IVOR)

Table 2-11. IVOR Field Descriptions

Bits Name Setting Description

32–47 — Reserved, should be cleared.

48–59 Vector offset Provides a quad-word index from the base address provided by the IVPR to locate an interrupt handler.

60 — Reserved, should be cleared.

61–63 CS Context selector (e200z3-specific). When multiple hardware contexts are supported, this field is used to select an operating context for the interrupt handler. This value is loaded into the CURCTX field of the context control register (CTXCR) as part of the interrupt vectoring process. When multiple hardware contexts are not supported, CS is not implemented and is read as zero.

SPR numbers corresponding to IVOR16–IVOR31 are reserved. IVOR32–IVOR47 and IVOR60–IVOR63 are reserved. SPR numbers for IVOR32–IVOR63 are allocated for implementation-dependent use (IVOR32–IVOR34 (SPR 528–530) are defined by the EIS). IVOR assignments are shown in Table 2-12.