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Interrupt Types

W dokumencie E200Z4 (Stron 162-167)

Store Multiple Volatile MCSRR Word

4.10 Operand Placement On Performance

5.1.2 Interrupt Types

The e200z4 core processes all interrupts as either debug, machine check, critical, or noncritical types.

Separate control and status register sets are provided for each type of interrupt. Table 5-1 describes the interrupt types.

Table 5-1. Interrupt Types

Category Description Programming Resources

Noncritical interrupts

First-level interrupts that let the processor change program flow to handle conditions generated by external signals, errors, or unusual conditions arising from program execution or from programmable timer-related events. These interrupts are largely identical to those defined by the OEA.

SRR0/SRR1 SPRs and rfi instruction.

Asynchronous noncritical interrupts can be masked by the external interrupt enable bit, MSR[EE].

Critical interrupts

Critical input, watchdog timer, and debug interrupts. These interrupts can be taken during a noncritical interrupt or during regular program flow. The critical input and watchdog timer interrupts are treated as critical interrupts. If the debug interrupt is not enabled, it is also treated as a critical interrupt.

Critical save and restore SPRs (CSRR0/CSRR1) and rfci. Critical input and watchdog timer critical interrupts can be masked by the critical enable bit, MSR[CE]. Debug events can be masked by the debug enable bit MSR[DE].

Because save/restore register pairs are serially reusable, care must be taken to preserve program state that may be lost when an unordered interrupt is taken.

As specified by the Power ISA embedded category architecture, interrupts can be either precise or imprecise, synchronous or asynchronous, and critical or non-critical. A precise interrupt architecturally guarantees that no instruction beyond the instruction causing the exception has (visibly) executed.

Asynchronous exceptions are caused by events external to the processor’s instruction execution;

synchronous exceptions are directly caused by instructions or an event somehow synchronous to the program flow, such as a context switch. Critical interrupts are provided with a separate save/restore register pair (CSRR0/CSRR1) to allow certain critical exceptions to be handled within a non-critical interrupt handler. Machine check interrupts are also provided with a separate save/restore register pair

(MCSRR0/MCSRR1) to allow machine check exceptions to be handled within a non-critical or critical interrupt handler.

The types of interrupts handled are shown in Table 5-2. Refer to the interrupt chapter in the EREF for exact details of each interrupt type.

Machine check interrupt

Provides a separate set of resources for the machine check interrupt. See Section 5.7.2, “Machine Check Interrupt (IVOR1).”

Machine check save and restore SPRs

(MCSRR0/MCSRR1) and rfmci. Maskable with the machine check enable bit, MSR[ME].

Includes the machine check syndrome register (MCSR).

Debug interrupt

Provides a separate set of resources for the debug interrupt. See Section 5.7.16, “Debug Interrupt (IVOR15).”

Debug save and restore SPRs (DSRR0/DSRR1) and rfdi. Can be masked by the machine check enable bit, MSR[DE]. Includes the debug syndrome register (DBSR).

Table 5-2. Interrupt Classifications

Interrupt Types Synchronous/Asynchronous Precise/Imprecise

Critical/Non-critical/

Debug/Machine Check

System Reset Asynchronous, non-maskable Imprecise

Machine Check Machine Check

Non-Maskable Input Interrupt Asynchronous, non-maskable Imprecise Machine Check Critical Input Interrupt

Watchdog Timer Interrupt

Asynchronous, maskable Imprecise Critical

External Input Interrupt Fixed-Interval Timer Interrupt Decrementer Interrupt

Asynchronous, maskable Imprecise Non-critical

Instruction-based Debug Interrupts Synchronous Precise Critical/Debug Table 5-1. Interrupt Types

Category Description Programming Resources

These classifications are discussed in greater detail in Section 5.7, “Interrupt Definitions.” Interrupts implemented in the e200 and the exception conditions that cause them are listed in Table 5-3.

Debug Interrupt (UDE)

Table 5-3. Exceptions and Conditions

Interrupt Type

Interrupt Vector Offset Register

Causing Conditions

System reset none,

vector to [p_rstbase[0:29]] ||

2’b00

Reset by assertion of p_reset_b.

Critical Input IVOR 01 p_critint_b is asserted and MSRCE= 1.

Machine check IVOR 1 • p_mcp_b transitions from negated to asserted

• ISI, ITLB Error on first instruction fetch for an exception handler • Parity Error signaled on cache access

• External bus error Machine check

(NMI)

IVOR 1 p_nmi_b transitions from negated to asserted.

Data Storage IVOR 2 • Access control.

• Byte ordering due to misaligned access across page boundary to pages with mismatched E bits

• Cache locking exception Instruction Storage IVOR 3 • Access control.

• Byte ordering due to misaligned instruction across page boundary to pages with mismatched VLE bits, or access to page with VLE set, and E indicating little-endian.

• Misaligned Instruction fetch due to a change of flow to an odd half-word instruction boundary on a Power ISA (non-VLE) instruction page External Input IVOR 41 p_extint_b is asserted and MSREE=1.

Alignment IVOR 5 • lmw, stmw not word aligned

• lwarx or stwcx. not word aligned, lharx or sthcx. not half-word aligned • dcbz with disabled cache, or to W or I storage

• SPE ld and st instructions not properly aligned

Program IVOR 6 Illegal, Privileged, Trap, FP enabled, AP enabled, Unimplemented Operation.

Floating-point unavailable

IVOR 7 MSRFP= 0 and attempt to execute a Book E floating point operation Table 5-2. Interrupt Classifications (Continued)

Interrupt Types Synchronous/Asynchronous Precise/Imprecise

Critical/Non-critical/

Debug/Machine Check

5.2 Exception Syndrome Register

The exception syndrome register (ESR) provides a syndrome to differentiate between exceptions that can generate the same interrupt type. The e200 adds some implementation specific bits to this register, as seen in Figure 5-1.

System call IVOR 8 Execution of the System Call (sc, se_sc) instruction AP unavailable IVOR 9

Decrementer IVOR 10 As specified in the EREF Fixed Interval Timer IVOR 11 As specified in the EREF Watchdog Timer IVOR 12 As specified in the EREF

Data TLB Error IVOR 13 Data translation lookup did not match a valid entry in the TLB Instruction TLB

Error

IVOR 14 Instruction translation lookup did not match a valid entry in the TLB

Debug IVOR 15 Trap, instruction address compare, data address compare, instruction complete, branch taken, return from interrupt, interrupt taken, debug counter, external debug event, unconditional debug event

Reserved IVOR 16–31

SPE Unavailable Exception

IVOR 32 See Section 7.2.6.1, “SPE Unavailable Exception

EFP Data Exception IVOR 33 See Section 6.2.5.2, “Embedded Floating-point Data Exception EFP Round

Exception

IVOR 34 See Section 6.2.5.3, “Embedded Floating-Point Round Exception

1 Autovectored external and critical input interrupts use this IVOR. Vectored interrupts supply an interrupt vector offset directly.

0

PIL PPR PTR FP ST 0

DLK ILK AP PUO BO PIE 0

SPE

0

VLEMI

0

MI

F 0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 62; Read/Write; Reset - 0x0

Figure 5-1. Exception Syndrome Register (ESR) Table 5-3. Exceptions and Conditions (Continued)

Interrupt Type

Interrupt Vector Offset Register

Causing Conditions

The ESR bits are defined in Table 5-4.

Table 5-4. ESR Bit Settings

Bit(s) Name Description Associated Interrupt Type

0–3 (32–35)

Allocated1

4 (36)

PIL Illegal Instruction exception Program

5 (37)

PPR Privileged Instruction exception Program

6 (38)

PTR Trap exception Program

7 (39)

FP Floating-point operation Alignment (not on the e200)

Data Storage (not on the e200) Data TLB (not on the e200)

Program 8

(40)

ST Store operation Alignment

Data Storage

DLK Data Cache Locking3 Data Storage

11 (43)

ILK Instruction Cache Locking Data Storage

12 (44)

AP Auxiliary Processor operation (Not used by the e200)

Alignment (not on the e200) Data Storage (not on the e200)

Data TLB (not on the e200) Program (not on the e200) 13

(45)

PUO Unimplemented Operation exception Program

14 (46)

BO Byte Ordering exception

Mismatched Instruction Storage exception

Data Storage Instruction Storage 15

(47)

PIE Program Imprecise exception (Reserved)

Currently unused by the e200

16–23 (48–55)

Reserved2

24 (56)

SPE SPE APU Operation SPE Unavailable

SPE Floating-point Data Exception

SPE Floating-point Round Exception

Alignment Data Storage

Data TLB

W dokumencie E200Z4 (Stron 162-167)