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Interrupts and Exception Handling

W dokumencie E200Z3 (Stron 40-44)

e200z335 Core Complex Overview

1.5 Interrupts and Exception Handling

The core supports an extended exception handling model, with nested interrupt capability and extensive interrupt vector programmability. The following sections define the interrupt model, including an overview of interrupt handling as implemented on the e200z3 core, a brief description of the interrupt classes, and an overview of the registers involved in the processes.

Convert Floating Point to Unsigned Integer with Round Toward Zero efsctuiz evfsctuiz rD,rB

Floating-Point Absolute Value efsabs evfsabs rD,rA

Floating-Point Add efsadd evfsadd rD,rA,rB

Floating-Point Compare Equal efscmpeq evfscmpeq crD,rA,rB

Floating-Point Compare Greater Than efscmpgt evfscmpgt crD,rA,rB

Floating-Point Compare Less Than efscmplt evfscmplt crD,rA,rB

Floating-Point Divide efsdiv evfsdiv rD,rA,rB

Floating-Point Multiply efsmul evfsmul rD,rA,rB

Floating-Point Negate efsneg evfsneg rD,rA

Floating-Point Negative Absolute Value efsnabs evfsnabs rD,rA

Floating-Point Subtract efssub evfssub rD,rA,rB

Floating-Point Test Equal efststeq evfststeq crD,rA,rB

Floating-Point Test Greater Than efststgt evfststgt crD,rA,rB

Floating-Point Test Less Than efststlt evfststlt crD,rA,rB

Floating-Point Single-Precision Multiply-Add efsmadd evfsmadd rD,rA,rB Floating-Point Single-Precision Negative Multiply-Add efsnmadd evfsnmadd rD,rA,rB Floating-Point Single-Precision Multiply-Subtract efsmsub evfsmsub rD,rA,rB Floating-Point Single-Precision Negative Multiply-Subtract efsnmsub evfsnmsub rD,rA,rB

Table 1-1. Scalar and Vector Embedded Floating-Point Instructions (continued)

Instruction

Mnemonic

Syntax Scalar Vector

1.5.1 Interrupt Handling

In general, interrupt processing begins with an exception that occurs due to external conditions, errors, or program execution problems. When an exception occurs, the processor checks whether interrupt

processing is enabled for that particular exception. If enabled, the interrupt causes the state of the processor to be saved in the appropriate registers and prepares to begin execution of the handler located at the associated vector address for that particular exception.

Once the handler is executing, the implementation may need to check bits in the exception syndrome register (ESR), the machine check syndrome register (MCSR), or the signal processing and embedded floating-point status and control register (SPEFSCR), depending on the exception type, to verify the specific cause of the exception and take appropriate action.

The core complex supports the interrupts described in Section 1.5.4, “Interrupt Registers.”

1.5.2 Interrupt Classes

All interrupts may be categorized as asynchronous/synchronous and critical/noncritical.

• Asynchronous interrupts (such as machine check, critical input, and external interrupts) are caused by events that are independent of instruction execution. For asynchronous interrupts, the address reported in a save/restore register is the address of the instruction that would have executed next had the asynchronous interrupt not occurred.

• Synchronous interrupts are those that are caused directly by the execution or attempted execution of instructions. Synchronous inputs are further divided into precise and imprecise types.

— Synchronous precise interrupts are those that precisely indicate the address of the instruction causing the exception that generated the interrupt or, in some cases, the address of the immediately following instruction. The interrupt type and status bits allow determination of which of the two instructions has been addressed in the appropriate save/restore register.

— Synchronous imprecise interrupts are those that may indicate the address of the instruction causing the exception that generated the interrupt, or some instruction after the instruction causing the interrupt. If the interrupt was caused by either the context synchronizing mechanism or the execution synchronizing mechanism, the address in the appropriate

save/restore register is the address of the interrupt-forcing instruction. If the interrupt was not caused by either of those mechanisms, the address in the save/restore register is the last instruction to start execution and may not have completed. No instruction following the instruction in the save/restore register has executed.

1.5.3 Interrupt Types

The e200z3 core processes all interrupts as either debug, critical, or noncritical types. Separate control and status register sets are provided for each type of interrupt. The core handles interrupts from these three categories in the following order of priority:

1. Debug interrupt—The EIS defines a separate set of resources for the debug interrupt. The debug save and restore registers (DSRR0/DSRR1) are used to save state when a debug interrupt is taken;

the rfdi instruction restores state when interrupt handling completes.The debug enable bit, HID0[DAPUEN], determines what interrupt is taken when a debug exception occurs, as follows:

— If DAPUEN = 0, the debug interrupt is disabled. Debug interrupts use the critical interrupt resources: CSRR0/CSRR1 and rfci; rfdi is treated as an illegal instruction. DCLREE, DCLRCE, CICLRDE, and MCCLRDE settings are ignored and are assumed to be ones.

— If DAPUEN = 1, debug is enabled. Debug interrupts use DSRR0/DSRR1 for saving state, and rfdi is available for returning from a debug interrupt.

2. Noncritical interrupts—First-level interrupts that allow the processor to change program flow to handle conditions generated by external signals, errors, or unusual conditions arising from program execution or from programmable timer events. These interrupts are largely identical to those defined by the OEA portion of the architecture. They use the save and restore registers

(SRR0/SRR1) to save state when they are taken, and they use the rfi instruction to restore state.

Asynchronous noncritical interrupts can be masked by the external interrupt enable bit, MSR[EE].

3. Critical interrupts—Critical interrupts can be taken during a noncritical interrupt or during regular program flow. They use the critical save and restore registers (CSRR0/CSRR1) to save state when they are taken, and they use the rfci instruction to restore state. These interrupts can be masked by the critical enable bit, MSR[CE]. The Power ISA defines the critical input, watchdog timer, and machine check interrupts as critical interrupts, but the e200z3 core defines a third set of resources for the debug interrupt, as described in Table 1-2.

All interrupts except debug interrupts are ordered within the two categories of noncritical and critical, such that only one interrupt of each category is reported, and when it is processed (taken), no program state is lost. Because save/restore register pairs are serially reusable, program state may be lost when an unordered interrupt is taken.

1.5.4 Interrupt Registers

The registers associated with interrupt handling are described in Table 1-2.

Table 1-2. Interrupt Registers

Register Description

Noncritical Interrupt Registers

SRR0 Save/restore register 0—Stores the address of the instruction causing the exception or the address of the instruction that will execute after the rfi instruction.

SRR1 Save/restore register 1—Saves machine state on noncritical interrupts and restores machine state after an rfi instruction is executed.

Critical Interrupt Registers

Each interrupt has an associated interrupt vector address, obtained by concatenating IVPR[32–47] with the address index in the associated IVOR (that is, IVPR[32–47] || IVORn[48–59] || 0b0000). The resulting address is that of the instruction to be executed when that interrupt occurs. IVPR and IVOR values are indeterminate on reset and must be initialized by the system software using mtspr. Table 1-2 lists IVOR registers implemented on the e200z335 core and the associated interrupts.

CSRR0 Critical save/restore register 0—On critical interrupts, stores either the address of the instruction causing the exception or the address of the instruction that executes after the rfci.

CSRR1 Critical save/restore register 1—Saves machine state on critical interrupts and restores machine state after an rfci instruction is executed.

Debug Interrupt Registers

DSRR0 Debug save/restore register 0—Used to store the address of the instruction that will execute after an rfdi instruction is executed.

DSRR1 Debug save/restore register 1—Stores machine state on debug interrupts and restores machine state after an rfdi instruction is executed.

Syndrome Registers

MCSR Machine check syndrome register—Saves machine check syndrome information on machine check interrupts.

ESR Exception syndrome register—Provides a syndrome to differentiate among the different kinds of exceptions that generate the same interrupt type. Upon generation of a specific exception type, the associated bits are set and all other bits are cleared.

SPE Interrupt Registers

SPEFSCR Signal processing and embedded floating-point status and control register—Provides interrupt control and status as well as various condition bits associated with the operations performed by the SPE.

Other Interrupt Registers

DEAR Data exception address register—Contains the address that was referenced by a load, store, or cache management instruction that caused an alignment, data TLB miss, or data storage interrupt.

IVPR IVORs

Together, IVPR[32–47] || IVORn [48–59] || 0b0000 define the address of an interrupt-processing routine. See Table 1-3 and Chapter 4, “Interrupts and Exceptions,” for more information.

Table 1-3. Exceptions and Conditions

IVORn Interrupt Type IVORn Interrupt Type

None1 System reset (not an interrupt) 10 Decrementer

02 Critical input 11 Fixed-interval timer

1 Machine check 12 Watchdog timer

2 Data storage 13 Data TLB error

3 Instruction storage 14 Instruction TLB error

42 External input 15 Debug

5 Alignment 6–31 Reserved

6 Program 32 SPE unavailable

7 Floating-point unavailable 33 SPE data exception

Table 1-2. Interrupt Registers (continued)

Register Description

W dokumencie E200Z3 (Stron 40-44)