Machine Check Causes

Machine check causes are divided into different types:

• Error report machine check conditions

• Non-maskable interrupt (NMI) machine check exceptions

• Asynchronous machine check exceptions

This division is intended to facilitate machine check handling in uniprocessor, multiprocessor, and multithreaded systems. Although the initial implementation of the e200z4 does not implement

multithreading, future versions are expected to, and the machine check model will remain compatible. In addition, the model is equally applicable to a single-threaded design.

5.7.2.1.1 Error Report Machine Check Exceptions

Error report machine check exceptions are directly associated with the current instruction execution stream, and are presented to the interrupt mechanism in a manner analogous to an instruction storage or data storage interrupt. Since the execution stream cannot continue execution without suffering from corruption of architectural state, these exceptions are not masked by MSR[ME]. Error report machine check exceptions are not necessarily recoverable if they occur during the initial portion of a machine check handler. The MSR[RI] and MCSRR1[RI] bits are provided to assist software in determining recoverability.

For error report machine check exceptions, the MCSR is updated only when the machine check interrupt is actually taken. The MCAR is not updated for error report machine check exceptions.

Error report machine check exceptions encountered by program execution can be flushed if an older exception exists or if an asynchronous interrupt or machine check is taken before the instruction that encountered the error becomes the oldest instruction in the machine. In this case the corresponding MCSR bit is not set due to the flushed exception condition (although the corresponding bit may have already been set by a previous instruction’s exception). Note that an asynchronous machine check condition may occur for the same error condition prior to the error report machine check, and the error report machine check may be discarded.

Depending on the type of error, the MCSR IF, LD, G, or ST bits are set by hardware to reflect the error being reported. Software is responsible for clearing these syndrome bits by writing a ‘1’ to the bits to be cleared. Hardware will not clear an error report bit once it is set.

• MCSR[IF] is set if the error occurred during an instruction fetch

• MCSR[LD] is set if the error occurred for a load instruction. If the error occurred for a guarded load and the error source was from the external bus, MCSR[G] will also be set.

• MCSR[ST] is set if the error occurred in the MMU (DTLB Error or DSI) for a store type

instruction, if an external termination error was received on a cache-inhibited guarded store or on a store conditional instruction. If an external termination error occurred on a cache-inhibited guarded store, or on a guarded store conditional, MCSR[G] is also set.

Note that most (if not all) error report machine check exceptions are accompanied by an associated asynchronous machine check exception on a single-threaded e200z446n3, although this may not generally

Table 5-10 lists the error report machine check exceptions.

5.7.2.1.2 Non-Maskable Interrupt Machine Check Exceptions

Non-maskable interrupt exceptions are reported by means of the p_nmi_b input pin, which is transition sensitive. NMI exceptions are not gated by MSR[ME], thus they are not necessarily recoverable if an NMI exception occurs during the initial part of a machine check exception handler. The MSR[RI] and

MCSRR1[RI] bits are provide to assist software in determining recoverability.

Table 5-10. Error Report Machine Check Exceptions Synchronous Machine

Check Source Error Type MCSR Updates Precise¹

1 MCSRR0 will point to the instruction associated with the machine check condition Instruction Fetch (Icache tag array parity error or data array

parity error) & L1CSR1_ICEA=’00’

IF yes

Icache uncorrectable tag array parity error L1CSR1_ICEA=’01’ & and locked line was invalidated

yes

External termination error yes

Load instruction External termination error on load LD, [G]²

2 G will be set if the load was a guarded load.

yes Load and reserve instruction External termination error on load LD, [G]² yes

Store instruction External termination error on unbuffered store³

3 Store may be unbuffered if the store buffer is disabled

ST, [G]⁵ yes

External termination error on CI+G store⁴

4 Only reported if the store was a cache-inhibited guarded store

ST, G yes

Store conditional instruction External termination error on store conditional

ST, [G]⁵

5 Only reported if the store was a guarded store.

yes

icblc instruction Icache tag array parity error & at least one line locked & L1CSR1_ICEA=‘00’

IF yes

Icache tag array uncorrectable parity error &

L1CSR1_ICEA=‘01’ & locked line was invalidated

yes

icbtls instruction Icache tag array parity error &

L1CSR1_ICEA=‘00’

IF yes

Icache tag array uncorrectable parity error &

L1CSR1_ICEA=‘01’ & locked line was invalidated

yes

External termination error on linefill IF yes

Exception Vectoring ISI, ITLB, or Bus Error on first instruction fetch for an exception handler

IF yes

For NMI machine check exceptions, MCSR[NMI] is updated (set) only when the machine check interrupt is actually taken. Hardware does not clear the MCSR[NMI] syndrome bit. Software is responsible for clearing this syndrome bit by writing a ‘1’ to the bits to be cleared. Hardware will not clear an NMI bit once it is set.

The MCAR is not updated for NMI machine check exceptions.

5.7.2.1.3 Asynchronous Machine Check Exceptions

The remainder of machine check exceptions are classified as asynchronous machine check exceptions, as they are reported directly by the subsystem or resource that detected the condition. For many cases, the asynchronous condition will be reported simultaneously with a corresponding error report condition.

These conditions are reported by immediately setting the corresponding MCSR “async mchk” syndrome bit, regardless of the state of MSR[ME]. Interrupts due to asynchronous machine check exceptions are gated by MSR[ME]. If MSR[ME] = 0 at the time an asynchronous machine check bit is set, the interrupt is postponed until MSR[ME] is later set to ‘1,’ although a machine check interrupt may occur at the time of the event due to an error report exception. Asynchronous events are cumulative; hardware does not clear an asynchronous machine check syndrome bit. Software is responsible for clearing these syndrome bits by writing a ‘1’ to the bit or bits to be cleared. Hardware will not clear an asynchronous machine check bit once it is set.

If MCSR[MAV] is cleared at the time an asynchronous machine check exception occurs that has a corresponding address (either an effective or real address) to log in the MCAR, then the MCAR and the MCSR[MEA] bit are updated and the MCSR[MAV] bit is set. If MCSR[MAV]was previously set, the MCAR and the MCSR[MEA] bit are not affected.

Table 5-11 details all asynchronous machine check sources.

Table 5-11. Asynchronous Machine Check Exceptions Asynchronous

Machine Check Source

Transaction

Source Error Type MCSR Update¹ MCAR

Update²

External n/a Machine Check Input Pin³ MCP none

Table 5-12 details the priority of asynchronous machine check updates to the MCAR when multiple simultaneous asynchronous machine check conditions occur. Note that because a higher priority condition can occur after a lower priority condition occurs but before the machine check interrupt handler reads the

Instruction Cache Instruction Fetch Tag array parity error and L1CSR1[ICEA] = 00

MAV IC_TPERR RA

Icache hit, data array parity error and L1CSR1[ICEA] = 00

IC_DPERR RA

L1CSR1[ICEA] = 01 and Auto-invalidation of locked line due to uncorrectable tag parity error

IC_TPERR, IC_LKERR

RA

icblc Tag array parity error and L1CSR1[ICEA] = 00 and at least one line locked

IC_TPERR RA

icbtls Tag array parity error and L1CSR1[ICEA] = 00

IC_TPERR RA

icblc icbtls

L1CSR1[ICEA] = 01 and Auto-invalidation of locked line due to uncorrectable tag parity error

IC_TPERR, IC_LKERR

RA

BIU store Bus error on write MAV BUS_WRERR RA

load Bus error MAV BUS_DRERR RA

icbtls CI or cache disabled

Ifetch

Bus error on linefill Bus error on CI Ifetch Bus error on cache disabled Ifetch

MAV BUS_IRERR RA

instruction fetch or icbtls

Bus error on locked line error recovery refill

MAV BUS_IRERR,

IC_LKERR

RA

Exception Vectoring

first instruction fetch for an exception

handler

ISI or Bus Error on first instruction fetch for an exception handler

MAV EXCP_ERR RA

first instruction fetch for an exception

handler

ITLB Error on first instruction fetch for an exception handler

MAV EXCP_ERR EA

1 The MCSR update column indicates which bits in the MCSR will be updated when the exception is logged.

2 The MCAR update column indicates whether or not the error will provide either a real address (RA), effective address (EA), or no address (none) which is associated with the error.

3 The machine check input pin is used by the platform logic to indicate machine check type errors which are detected by the platform. Software must query error logging information within the platform logic to determine the specific error condition and source.

Table 5-11. Asynchronous Machine Check Exceptions (Continued) Asynchronous

Machine Check Source

Transaction

Source Error Type MCSR Update¹ MCAR

Update²

MCSR and MCAR, the interrupt handler may not necessarily see the higher priority MCAR value, even though multiple MCSR bits are set.

W dokumencie E200Z4 (Stron 175-179)