Store Multiple Volatile MCSRR Word
5.3 Machine State Register
The machine state register defines the state of the processor. It is shown in Figure 5-2.
The MSR bits are defined in Table 5-5.
25 (57)
— Allocated1 —
26 (58)
VLEMI VLE Mode Instruction SPE Unavailable
SPE Floating-point Data Exception
SPE Floating-point Round Exception
MIF Misaligned Instruction Fetch Instruction Storage
Instruction TLB 31
(63)
— Allocated1 —
1 These bits are not implemented and should be written with zero for future compatibility.
2 These bits are not implemented, and should be written with zero for future compatibility.
3 This bit is implemented, but not set by hardware
0
Figure 5-2. Machine State Register (MSR)
Table 5-5. MSR Bit Settings
Bit(s) Name Description
UCLE User Cache Lock Enable
0 Execution of the cache locking instructions in user mode (MSRPR=1) disabled; DSI Table 5-4. ESR Bit Settings (Continued)
Bit(s) Name Description Associated Interrupt Type
6 (38)
SPE SPE Available
0 Execution of SPE and EFP APU vector instructions is disabled; SPE Unavailable exception taken instead, and SPE bit is set in ESR.
1 Execution of SPE and EFP APU vector instructions is enabled.
7–12 (39–44)
— Reserved1
13 (45)
WE Wait State (Power management) enable. This bit is defined as optional in the Power ISA embedded category architecture.
0 Power management is disabled.
1 Power management is enabled. The processor can enter a power-saving mode when additional conditions are present. The mode chosen is determined by the DOZE, NAP, and SLEEP bits in the HID0 register, described in Section 2.4.11, “Hardware Implementation Dependent Register 0 (HID0).”
14 (46)
CE Critical Interrupt Enable
0 Critical Input and Watchdog Timer interrupts are disabled.
1 Critical Input and Watchdog Timer interrupts are enabled.
15 (47)
— Reserved1
16 (48)
EE External Interrupt Enable
0 External Input, Decrementer, and Fixed-Interval Timer interrupts are disabled.
1 External Input, Decrementer, and Fixed-Interval Timer interrupts are enabled.
17 (49)
PR Problem State
0 The processor is in supervisor mode, can execute any instruction, and can access any resource (e.g. GPRs, SPRs, MSR, etc.).
1 The processor is in user mode, cannot execute any privileged instruction, and cannot access any privileged resource.
18 (50)
FP Floating-Point Available
0 Floating-point unit is unavailable. The processor cannot execute floating-point instructions, including floating-point loads, stores, and moves. (An FP Unavailable interrupt will be generated on attempted execution of floating point instructions).
1 Floating-point unit is available. The processor can execute floating-point instructions. (Note that for e200, the floating point unit is not supported, and an Unimplemented Operation exception will be generated for attempted execution of floating-point instructions when FP is set).
19 (51)
ME Machine Check Enable
0 Asynchronous Machine Check interrupts are disabled.
1 Asynchronous Machine Check interrupts are enabled.
20 (52)
FE0 Floating-point exception mode 0 (not used by the e200)
21 (53)
— Reserved1
22 (54)
DE Debug Interrupt Enable
0 Debug interrupts are disabled.
1 Debug interrupts are enabled.
23 (55)
FE1 Floating-point exception mode 1 (not used by the e200) Table 5-5. MSR Bit Settings (Continued)
Bit(s) Name Description
5.4 Machine Check Syndrome Register (MCSR)
When the processor takes a machine check interrupt, it updates the machine check syndrome register (MCSR) to differentiate between machine check conditions. The MCSR is shown in Figure 5-3.
Table 5-6 describes MCSR fields. The MCSR indicates the source of a machine check condition. When an
“Async Mchk” or “Error Report” syndrome bit in the MCSR is set, the core complex asserts p_mcp_out for system information.
All bits in the MCSR are implemented as “write ‘1’ to clear”. Software in the machine check handler is
24
IS Instruction Address Space
0 The processor directs all instruction fetches to address space 0 (TS=0 in the relevant TLB entry).
1 The processor directs all instruction fetches to address space 1 (TS=1 in the relevant TLB entry).
27 (59)
DS Data Address Space
0 The processor directs all data storage accesses to address space 0 (TS=0 in the relevant TLB entry).
1 The processor directs all data storage accesses to address space 1 (TS=1 in the relevant TLB entry).
This bit is provided for software use to detect nested exception conditions. This bit is cleared by hardware when a Machine Check interrupt is taken
31 (63)
— Reserved1
1 These bits are not implemented, will be read as zero, and writes are ignored.
MCP IC_DPERR
BUS_IRERR BUS_DRERR BUS_WRERR 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 572; Read/Clear; Reset - 0x0
Figure 5-3. Machine Check Syndrome Register (MCSR) Table 5-5. MSR Bit Settings (Continued)
Bit(s) Name Description
check exception and to prepare for updated status bit information on the next machine check interrupt.
Hardware will not clear a bit in the MCSR other than at reset. Software will typically sample MCSR early in the machine check handler, and will use the sampled value to clear those bits which were set at the time of sampling. Note that additional bits may become set during the handler after sampling if an asynchronous event occurs. By writing back only the originally sampled bits, another machine check can be generated to process the new conditions after the original handler re-enables MSRME either explicitly, or by restoring the MSR from MSRR1 at the return.
Note that any set bit in the MCSR other than status-type bits will cause a subsequent machine check interrupt once MSRME=1.
Table 5-6. Machine Check Syndrome Register (MCSR)
Bit Name Description Exception
Type1 Recoverable 0
(32)
MCP Machine check input pin Async Mchk Maybe
1 (33)
IC_DPERR Instruction Cache data array parity error Async Mchk Precise
2–3 (34–35)
— Reserved, should be cleared. — —
4 (36)
EXCP_ERR ISI, ITLB, or Bus Error on first instruction fetch for an exception handler
Async Mchk Precise
5 (37)
IC_TPERR Instruction Cache Tag parity error Async Mchk Precise
6 (38)
— Reserved, should be cleared. —
7 (39)
IC_LKERR Instruction Cache Lock error
Indicates a cache control operation or invalidation operation invalidated one or more locked lines in the Icache
Status —
8–10 (40–42)
— Reserved, should be cleared. —
11 (43)
NMI NMI input pin NMI —
12 (44)
MAV MCAR Address Valid
Indicates that the address contained in the MCAR was updated by hardware to correspond to the first detected Async Mchk error condition
Status —
13 (45)
MEA MCAR holds Effective Address
If MAV=1,MEA=1 indicates that the MCAR contains an effective address and MEA=0 indicates that the MCAR contains a physical address
Status —
14 (46)
— Reserved, should be cleared. —
15 (47)
IF Instruction Fetch Error Report
An error occurred during the attempt to fetch an instruction. This could be due to a parity error, or an external bus error. MCSRR0 contains the instruction address.
LD Load type instruction Error Report
An error occurred during the attempt to execute the load type instruction located at the address stored in MCSRR0.
ST Store type instruction Error Report
An error occurred during the attempt to execute the store type instruction located at the address stored in MCSRR0.
G Guarded Load or Store instruction Error Report An error occurred during the attempt to execute the load or store type instruction located at the address stored in MCSRR0 and the guarded access encountered an error on the external bus.
Error Report
Precise
19–26 (51–58)
— Reserved, should be cleared. —
27 (59)
BUS_IRERR Read bus error on Instruction fetch or linefill Async Mchk Precise if data used 28
(60)
BUS_DRERR Read bus error on data load Async Mchk Precise if data used 29
(61)
BUS_WRERR Write bus error on store Async Mchk Unlikely
30–31 (62–63)
— Reserved, should be cleared. —
1 The Exception Type indicates the exception type associated with a given syndrome bit
“Error Report” indicates that this bit is only set for error report exceptions which cause machine check interrupts. These bits are only updated when the machine check interrupt is actually taken. Error report exceptions are not gated by MSR[ME]. These are synchronous exceptions. These bits will remain set until cleared by software writing a “1” to the bit position(s) to be cleared.
“Status” indicates that this bit is provides additional status information regarding the logging of an asynchronous machine check exception. These bits will remain set until cleared by software writing a “1” to the bit position(s) to be cleared.
“NMI” indicates that this bit is only set for the non-maskable interrupt type exception which causes a machine check interrupt. This bit is only updated when the machine check interrupt is actually taken. NMI exceptions are not gated by MSRME. This is an asynchronous exception. This bit will remain set until cleared by software writing a “1” to the bit position.
“Async Mchk” indicates that this bit is set for an asynchronous machine check exception. These bits are set immediately upon detection of the error. Once any “Async Mchk” bit is set in the MCSR, a machine check interrupt will occur if MSR[ME] = 1. If MSR[ME] = 0, the machine check exception will remain pending. These bits will remain set until cleared by software writing a “1” to the bit position(s) to be cleared.
Table 5-6. Machine Check Syndrome Register (MCSR) (Continued)
Bit Name Description Exception
Type1 Recoverable