Register Model
2.16 MMU Registers
2.16.4 MMU Assist Registers (MAS0–MAS4, MAS6)
The e200z3 uses six special-purpose registers (MAS0–MAS4, and MAS6) for reading, writing, and searching the TLBs. The MAS registers can be read or written using the mfspr and mtspr instructions.
The e200z3 does not implement the MAS5 register, which is present in other Freescale Book E designs, because the tlbsx instruction only searches based on a single SPID value.
For details on the MASn registers, see Section 5.6.5, “MMU Assist Registers (MAS).” The MAS0 register is shown in Figure 2-47.
MAS0 fields are defined in Table 2-32.
The MAS1 register is shown in Figure 2-48.
32 33 34 35 36 42 43 47 48 58 59 60 63
Field — TLBSEL — ESEL — NV
Reset Undefined on m_por assertion, unchanged on p_reset_b assertion
R/W R/W
SPR SPR 624
Figure 2-47. MAS Register 0 (MAS0) Format
Table 2-32. MAS0—MMU Read/Write and Replacement Control
Bits Name Description
32–33 — Reserved, should be cleared.
34–35 TLBSEL Selects TLB for access.
01 TLB1 (ignored by the e200z3, should be written to 01 for future compatibility).
36–42 — Reserved, should be cleared.
43–47 ESEL Entry select for TLB1.
Bit 43 is reserved on e200z335, so ESEL includes only bits 44–47 for e200z335.
48–59 — Reserved, should be cleared.
60–63 NV Next replacement victim for TLB1 (software managed). Software updates this field; it is copied to the ESEL field on a TLB error (See Table 5-6).
Bit 60 is reserved on e200z335, so NV includes only bits 61–63 for e200z335.
32 33 34 39 40 47 48 50 51 52 55 56 63
Field VALID IPROT — TID — TS TSIZE —
Reset Undefined on m_por assertion, unchanged on p_reset_b assertion
R/W R/W
SPR SPR 625
Figure 2-48. MMU Assist Register 1 (MAS1)
MAS1 fields are defined in Table 2-33.
The MAS2 register is shown in Figure 2-49.
Table 2-33. MAS1—Descriptor Context and Configuration Control
Bits Name Description
32 VALID TLB entry valid.
0 This TLB entry is invalid.
1 This TLB entry is valid.
33 IPROT Invalidation protect. Protects TLB entry from invalidation by tlbivax (TLB1 only), or flash invalidates through MMUCSR0[TLB1_FI].
0 Entry is not protected from invalidation.
1 Entry is protected from invalidation as described in Section 5.3.1, “IPROT Invalidation Protection in TLB1.”
34–39 — Reserved, should be cleared.
40–47 TID Translation ID. Compared with the current process IDs of the effective address to be translated. A TID value of 0 defines an entry as global and matches with all process IDs.
48–50 — Reserved, should be cleared.
51 TS Translation address space. Compared with MSR[IS] or MSR[DS] (depending on the type of access) to determine if this TLB entry may be used for translation.
52–55 TSIZE Entry page size.
Supported page sizes are:
0001 4KB 0010 16KB 0011 64k 0100 256k 0101 1MB 0110 4MB 0111 16MB 1000 64MB 1001 256MB
1010 1 GB (e200z335 only) 1011 4 GB (e200z335 only) All other values are undefined 56–63 — Reserved, should be cleared.
SPR 626 Access: Supervisor read/write
0 32
R
EPN W
Reset Undefined
32 51 52 54 55 56 57 58 59 60 61 62 63
R
EPN — VLE W I M G E
W
Figure 2-49. MMU Assist Register 2 (MAS2)
MAS2 fields are defined in Table 2-34.
The MAS3 register is shown in Figure 2-50.
Table 2-34. MAS2—EPN and Page Attributes
Bits Name Description
32–51 EPN Effective page number.
52–57 — Reserved, should be cleared.
58 VLE VLE mode.
Identifies pages that contain instructions from the VLE APU. VLE is implemented only if the processor supports the VLE APU. Setting both the VLE and E fields is a programming error; an attempt to fetch instructions from a page so marked produces an ISI byte ordering exception and sets ESR[BO].
0 Instructions fetched from the page are decoded and executed as PowerPC or EIS instructions.
1 Instructions fetched from the page are decoded and executed as VLE or EIS instructions.
Implementation-dependent page attribute.
59 W Write-through required.
0 This page is a write-back with respect to the caches in the system.
1 All stores performed to this page are written through to main memory.
60 I Cache inhibited.
0 This page is cacheable.
1 This page is cache-inhibited.
61 M Memory coherence required.The e200z3 does not support the memory coherence required attribute, and thus it is ignored.
0 Memory coherence is not required.
1 Memory coherence is required.
62 G Guarded. The e200z3ignores the guarded attribute (other than for generation of the p_hprot[4:2] attributes on an external access), since no speculative or out-of-order processing is performed.
0 Access to this page are not guarded, and can be performed before it is known if they are required by the sequential execution model.
1 All loads and stores to this page are performed without speculation (that is, they are known to be required).
63 E Endianness. Determines endianness for the corresponding page.
0 The page is accessed in big-endian byte order.
1 The page is accessed in true little-endian byte order.
Permission bits
32 51 52 53 54 55 56 57 58 59 60 61 62 63
Field RPN — U0 U1 U2 U3 UX SX UW SW UR SR
Reset Undefined on m_por assertion, unchanged on p_reset_b assertion
R/W R/W
SPR SPR 627
Figure 2-50. MMU Assist Register 3 (MAS3)
MAS3 fields are defined in Table 2-35.
The MAS4 register, shown in Figure 2-51, contains fields for specifying default information to be pre-loaded on certain MMU related exceptions.
The MAS4 fields are defined in Table 2-36.
Table 2-35. MAS3—RPN and Access Control
Bits Name Description
32–51 RPN Real page number.
Only bits that correspond to a page number are valid. Bits that represent offsets within a page are ignored and should be zero.
52–53 — Reserved, should be cleared.
54–57 U0–U3 User bits.
58–63 PERMIS Permission bits (UX, SX, UW, SW, UR, SR).
SPR 628 Access: Supervisor read/write
32 33 34 35 36 39 40 47 48 51 52 55 56 57 58 59 60 61 62 63
R
— TLBSELD — TIDSELD — TSIZED — VLED WD ID MD GD ED
W
Reset All zeros
Figure 2-51. MMU Assist Register 4 (MAS4)
Table 2-36. MAS4—Hardware Replacement Assist Configuration Register
Bits Name Description
32–33 — Reserved, should be cleared.
34–35 TLBSELD Default TLB selected.
01 TLB1 (ignored by the e200z3, should be written to 01 for future compatibility) 36–43 — Reserved, should be cleared.
44–47 TIDSELD TID default selection value. 4-bit field that specifies which of the current PID registers should be used to load the MAS1[TID] field on a TLB miss exception.
The PID registers are addressed as follows:
0000 = PID0 (PID).
0001 = PID1.
...
1110 = PID14.
A value that references a non-implemented PID register causes a value of 0 to be placed in MAS1[TID].
48–51 — Reserved, should be cleared.
52–55 TSIZED Default TSIZE value.
56–57 — Reserved, should be cleared.
58 VLED Default VLE value. Specifies the default value loaded into MAS2[VLE] on a TLB miss exception.
59–63 DWIMGE Default WIMGE values.
The MAS6 register is shown in Figure 2-52.
MAS6 fields are defined in Table 2-37.