Therefore, it is recommended to perform thermal simulations at the system level with the worst case device power consumption
5.8.1 Package Thermal Characteristics
Table 5-20 provides the thermal resistance characteristics for the package used on this device.
NOTE
Power dissipation of 1.5 W and an ambient temperature of 85ºC is assumed for ABC package.
Table 5-20. Thermal Resistance Characteristics
NO. PARAMETER DESCRIPTION °C/W(1) AIR FLOW (m/s)(2)
T1 RΘJC Junction-to-case 0.41 N/A
T2 RΘJB Junction-to-board 4.74 N/A
T3
RΘJA
Junction-to-free air 11.9 0
T4
Junction-to-moving air
8.9 1
T5 8.0 2
T6 7.4 3
T7
ΨJT Junction-to-package top
0.22 0
T8 0.22 1
T9 0.22 2
T10 0.23 3
T11
ΨJB Junction-to-board
4.12 0
T12 3.73 1
T13 3.59 2
T14 3.48 3
(1) These measurements were conducted in a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] measurement, which was conducted in a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:
– JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) – JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
– JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages – JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second
compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. Refer to the Section 4.2, Ball Characteristics of the Section 4, Terminal Configuration and Functions to determine which power supplies are applicable.
Figure 5-2 and Figure 5-3 describe the device Power Sequencing when RTC-mode is used.
SPRS906_ELCH_01
vdds18v, vdds_mlbp, vdds18v_ddr1
vdda_per, vdda_ddr, vdda_debug, vdda_core_gmac, vdda_gpu, vdda_dsp_iva, vdda_video, vdda_mpu_abe, vdda_osc
vdd
vdd_mpu
vdd_iva
vdd_gpu
vdda33v_usb1, vdda33v_usb2
vddshv8
xi_osc0
rtc_porz
porz
sysboot[15:0]
rstoutn
Note 12 Note 13
Note 14 Note 9
Note 6
Note 7 VD_CORE BOOT voltage
VD_MPU BOOT voltage
VD_IVA BOOT voltage
VD_GPU BOOT voltage
VD_DSPEVE BOOT voltage
Valid Config
Note 11 vddshv5(3)
vdd_rtc(3)
vdds_ddr1, ddr1_vref0
vdd_dsp
vddshv1, vddshv2, vddshv3, vddshv4, vddshv6, vddshv7, vddshv9, vddshv10, vddshv11 vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie, vdda_pcie1, vdda_sata, vdda_usb3, vdda_csi
Figure 5-2. Power-Up Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn rails but vddshv8 must ramp after vdd.
(8) vdds and vdda rails must not be combined together.
(9) Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
(10) The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.
(11) Pulse duration: porz must remain low a minimum of 12P(15)after xi_osc0 is stable and at a valid frequency. porz must also remain low until all supply rails are valid and stable. resetn must be high prior to, or simultaneous with, porz rising. During initial power-up, resetn can rise any time after, or concurrently with, its supply voltage, vddshv3 rising.
(12) Setup time: sysboot[15:0] pins must be valid 2P(15)before porz is de-asserted high.
(13) Hold time: sysboot[15:0] pins must be valid 15P(15)after porz is de-asserted high.
(14) porz to rstoutn delay is 2ms.
(15) P = 1/(SYS_CLK1/610) frequency in ns.
vdds18v, vdds_mlbp, vdds18v_ddr1 vdda_per, vdda_ddr, vdda_debug, vdda_dsp_iva, , vdda_gpu, vdda_video, vdda_mpu_abe, vdda_osc vdda_core_gmac
vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_sata, vdda_usb3, vdda_csi
vdds_ddr1, ddr1_vref0 vdd vdd_mpu vdd_gpu vdd_dsp
vdd_iva vddshv8
vddshv1, vddshv2, vddshv3, vddshv4, vddshv6, vddshv7, vddshv9, vddshv10, vddshv11 vdda33v_usb1, vdda33v_usb2
xi_osc0 vddshv5(4)
vdd_rtc(4)
vdda_rtc(4)
SPRS906_ELCH_02
Note 8
Note 7
Figure 5-3. Power-Down Sequencing
(1) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
(2) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(3) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(4) If RTC-mode is supported then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot be combined with other rails.
never higher than 2.0 V above the vdds18v rail.
(8) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
vdds18v, vdds_mlbp, vdds18v_ddr1
vdda_per, vdda_ddr, vdda_debug, vdda_dsp_iva, vdda_core_gmac, vdda_gpu, vdda_video, vdda_mpu, vdda_osc
vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_sata, vdda_usb3, vdda_csi vdds_ddr1, ddr1_vref0
vdd
vdd_mpu
vdd_gpu
vdd_dsp vdd_iva
vddshv8 vddshv1, vddshv2, vddshv3, vddshv4, vddshv6, vddshv7, vddshv9, vddshv10, vddshv11 vdda_rtc
vdd_rtc
vddshv5
vdda33v_usb1, vdda33v_usb2
SPRS906_ELCH_03
R T C
M O D E
Note 8 Note 6
Note 9
Note 7
rtc_porz
resetn/porz
Figure 5-4. RTC Mode Sequencing
(5) vdd must ramp up before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn rails but vddshv8 must ramp down before vdd and must ramp up after vdd.
(8) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshvn rail is never higher than 2.0 V above the vdds18v rail.
(9) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
Note 6 vdds18v, vdds_mlbp, vdds18v_ddr1, vdda_rtc(3)
vdda_per, vdda_ddr, vdda_debug, vdda_dsp_iva, vdda_core_gmac, vdda_gpu, vdda_video, vdda_mpu, vdda_osc
vdds_ddr1, ddr1_vref0
vdd, vdd_rtc(3)
VD_CORE BOOT voltage
VD_MPU BOOT voltage
VD_IVA BOOT voltage
VD_GPU BOOT voltage
VD_DSP BOOT voltage vdd_mpu
vdd_iva
vdd_gpu
vdd_dsp
vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_sata, vdda_usb3, vdda_csi
vddshv1, vddshv2, vddshv3, vddshv4, vddshv5 , vddshv6, vddshv7, vddshv9, vddshv10, vddshv11
(3)
vdda33v_usb1, vdda33v_usb2
vddshv8
xi_osc0
rtc_porz
porz
sysboot[15:0]
rstoutn
Valid Config
Note 11
Note 12 Note 13
Note 14 Note 9
Note 7
SPRS906_ELCH_04
Figure 5-5. Power-Up Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(4) vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn rails but vddshv8 must ramp after vdd.
(8) vdds and vdda rails must not be combined together, with the one exception of vdda_rtc when RTC-mode is not supported.
(9) Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
(10) The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.
(11) Pulse duration: porz must remain low a minimum of 12P(15)after xi_osc0 is stable and at a valid frequency. porz must also remain low until all supply rails are valid and stable. resetn must be high prior to, or simultaneous with, porz rising. During initial power-up, resetn can rise any time after, or concurrently with, its supply voltage, vddshv3 rising.
(12) Setup time: sysboot[15:0] pins must be valid 2P(15)before porz is de-asserted high.
(13) Hold time: sysboot[15:0] pins must be valid 15P(15)after porz is de-asserted high.
(14) porz to rstoutn delay is 2ms.
(15) P = 1/(SYS_CLK1/610) frequency in ns.
vdda_per, vdda_ddr, vdda_debug,
vdda_dsp_iva, ,
vdda_gpu, vdda_video, vdda_mpu, vdda_osc vdda_core_gmac vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_sata, vdda_usb3, vdda_csi
vdds_ddr1, ddr1_vref0 vdd, vdd_rtc(4) vdd_mpu vdd_gpu vdd_dsp
vdd_iva vddshv8
vdda33v_usb1, vdda33v_usb2
xi_osc0
SPRS906_ELCH_05
Note 8
Note 7
vdds18v, vdds_mlbp, vdds18v_ddr1, vdda_rtc(4)
Figure 5-6. Power-Down Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
(4) If RTC-mode is not used then the following combinations are approved:
- vdda_rtc can be combined with vdds18v - vdd_rtc can be combined with vdd
- vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails
If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(6) vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(7) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshv[1-7,9-11] rail is
Figure 5-7 describes vddshv[1-7,9-11] Supplies Falling Before vdds18v Supplies Delta.
Figure 5-7. vddshv* Supplies Falling After vdds18v Supplies Delta
(1) Vdelta MAX = 2V
(2) If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.
For more information, see Power Reset and Clock Management / PRCM Environment / External Clock Signal and Power Reset / PRCM Functional Description / PRCM Clock Manager Functional Description section of the Device TRM.
NOTE
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is still present in some clock or DPLL names.
