Parallel Signature Unit Registers

To support applications requiring system integrity checking during operation, the e200z3 provides a Parallel Signature unit to monitor the CPU data read and data write AHB buses and to accumulate a pair of 32-bit MISR signatures of the data values transferred over these buses.

The primitive polynomial used is P(X)=1+X¹⁰+X³⁰+X³¹+X³². Values are accumulated based on an initially programmed seed value and are qualified based on active byte lanes of the data read and data write buses (p_d_hrdata[63:0], p_d_hwdata[63:0]) as indicated via the p_d_hbstrb[7:0] signals. Inactive byte lanes use a value of all zeros as input data to the MISRs. Refer to Table 7-6 for active byte lane

information. If a transfer error occurs on any accumulated read data, the returned read data is ignored, a value of all zeros is used instead, and the error is logged. Errors occurring on data writes are not logged, since the data driven by the CPU is valid.

The unit can be independently enabled for read cycles and write cycles, allowing for flexible usage.

Software can also control accumulation of software-provided values via a pair of update registers. In addition, there is a counter for software to monitor the number of beats of data compressed.

Updates are performed when the parallel signature registers are initialized, when a qualified bus cycle is terminated, when a software update is performed via a high or low update register, and when the parallel signature high or low registers are written with an mtdcr instruction.

NOTE

Updates due to qualified bus transfers are suppressed for the duration of a debug session.

SPRG0–SPRG7 Unaffected ¹

SRR0 Unaffected ¹

SRR1 Unaffected ¹

SVR ³ —

TBL Unaffected ¹

TBU Unaffected ¹

TCR 0x0000_0000

TLB0CFG–

TLB1CFG

—

TSR Undefined on power-on reset; otherwise, 0x(0b00||WRS)000_0000

USPRG0 Unaffected ¹

XER 0x0000_0000

1 Undefined on m_por assertion, unchanged on p_reset_b assertion.

2 For CTXCR 0 only, others unaffected.

3 Read-only register.

Table 2-41. Reset Settings for e200z3 Resources (continued)

Resource System Reset Setting

The parallel signature unit consists of seven registers as described in this section. Access to these registers is privileged. No user-mode access is allowed.

NOTE

Proper access of the PSU registers requires an mfdcr that reads a PSU register to be proceeded by either mbar or msync. To ensure that the effects of an mtdcr to one of the PSU registers takes effect, the mtdcr is followed by a context synchronizing instruction (sc, isync, rfi, rfci, rfdi).

2.19.1 Parallel Signature Control Register (PSCR) PSCR, shown in Figure 2-55, controls operation of the parallel signature unit.

Figure 2-55. Parallel Signature Control Register (PSCR)

32 57 58 59 60 61 62 63

Field — CNTEN — RDEN WREN INIT

Reset All zeros

R/W R/W

DCR DCR 272

+ d q

+ d q

+ d q

+ d q + d q

+ d q

+ d q

... ...

D31 (D63) D30 (D62) D29 (D61) D28 (D60) D21 (D53) D1 (D33) D0 (D32)

+ d q D20 (D52)

+ d q D22 (D54)

Data Bus (p_d_hrdata, p_d_hwdata)

PSHR, (PSLR)

PSCR field descriptions are shown in Table 2-42.

.

2.19.2 Parallel Signature Status Register (PSSR)

PSSR, shown in Figure 2-56, provides status relative to operation of the parallel signature unit.

Figure 2-56. Parallel Signature Status Register (PSSR)

The PSSR register fields are described in Table 2-43.

.

2.19.3 Parallel Signature High Register (PSHR)

The PSHR, shown in Figure 2-57, provides signature information for the high word (bits 63–32) of the AHB data read and data write buses. Writing PSHR initializes a seed value before enabling signature

Table 2-42. PSCR Field Descriptions

Bits Name Description

32–57 — Reserved, should be cleared.

58 CNTEN Counter enable.

0 Counter is disabled.

1 Counter is enabled. Counter is incremented on every accumulated transfer or on an mtdcr psulr,rS.

59–60 — Reserved, should be cleared.

61 RDEN Read enable.

0 Processor data read cycles are ignored.

1 Processor data reads cycles are accumulated. For inactive byte lanes, zeros are used for the data values.

62 WREN Write enable.

0 Processor write cycles are ignored.

1 Processor write cycles are accumulated. For inactive byte lanes, zeros are used for the data values.

63 INIT This bit can be written with a 1 to set the values in the PSHR, PSLR, and PSCTR registers to all 0s.

(0x00000000). This bit always reads as 0.

32 62 63

Field — TERR

Reset Unaffected

R/W — w1c

DCR DCR 273

Table 2-43. PSSR Field Descriptions

Bits Name Description

32–62 — Reserved, should be cleared.

63 TERR Transfer error status. Indicates whether a transfer error occurs on accumulated read data and that the read data values returned are ignored and 0s are used instead. Hardware does not clear TERR; only a software write of 1 to TERR clears it.

0 No transfer error on accumulated read data since software last cleared this bit.

1 A transfer error occurred on accumulated read data since software last cleared this bit.

accumulation. PSCR[INIT] may also be used to clear the PSHR. PSHR is unaffected by system reset, thus should be initialized by software before performing parallel signature operations.

Figure 2-57. Parallel Signature High Register (PSHR)

2.19.4 Parallel Signature Low Register (PSLR)

PSLR, shown in Figure 2-58, provides signature information for the low word (bits 31-0) of the AHB data read and data write buses. Writing PSLR initializes a seed value prior to enabling signature accumulation.

PSCR[INIT] can also be used to clear the PSLR. PSLR is unaffected by system reset, thus should be initialized by software prior to performing parallel signature operations.

Figure 2-58. Parallel Signature Low Register (PSLR)

2.19.5 Parallel Signature Counter Register (PSCTR)

PSCTR, shown in Figure 2-59, provides count information for signature accumulation. It is incremented on every accumulated transfer or on an mtdcr psulr,rS. Writing to PSCTR initializes a value before enabling signature accumulation. PSCR[INIT] can also be used to clear PSCTR. PSCTR is unaffected by system reset, thus should be initialized by software before performing parallel signature operations.

.

Figure 2-59. Parallel Signature Counter Register (PSCTR)

32 63

Field High signature

Reset Unaffected

R/W R/W

DCR DCR 274

32 63

Field Low signature

Reset Unaffected

R/W R/W

DCR DCR 275

32 63

Field Counter

Reset Unaffected

R/W R/W

DCR DCR 276

2.19.6 Parallel Signature Update High Register (PSUHR)

PSUHR, shown in Figure 2-60, updates the high signature value via software. It can be written via an mtdcr psuhr, rS instruction to cause signature accumulation to occur in the PSHR using the data value written. Writing to this register does not cause the PSCTR to increment.

Figure 2-60. Parallel Signature Update High Register (PSUHR)

2.19.7 Parallel Signature Update Low Register (PSULR)

PSULR, shown in Figure 2-61, updates the low signature value via software. Writing to PSULR causes signature accumulation in the parallel signature low register (PSLR) using the data value written. Writing to this register causes PSCTR to increment.

Figure 2-61. Parallel Signature Update Low Register (PSULR)

32 63

Field High signature update data

Reset Unaffected

R/W Write only

DCR DCR 277

32 63

Field Low signature update data

Reset Unaffected

R/W Write only

DCR DCR 278

Chapter 3

Instruction Model

This chapter provides additional information about the Book E architecture as it relates specifically to the e200z3 and e200z335 cores.

The e200z3 is a 32-bit implementation of the Book E architecture. The Book E architecture specification includes a recognition that different processor implementations may require clarifications, extensions, or deviations from the architectural descriptions. Book E instructions are described in the EREF: A

Programmer's Reference Manual for Freescale Book E Processors.

In document E200Z3 (Page 124-129)