Power ISA Embedded Category Registers

The core supports most of the registers defined by Power ISA embedded category architecture. Notable exceptions are the floating-point registers FPR0–FPR31 and FPSCR. The e200z4 does not support the Power ISA floating-point architecture in hardware. The general-purpose registers have been extended to 64-bits. e200-specific registers are described in Section 2.2, “e200-Specific Special Purpose Registers,”

and the Power ISA embedded registers are described in the following sections. For complete descriptions, see the EREF.

2.1.1 User-level Registers

The user-level registers can be accessed by all software with either user- or supervisor-privileges. They include the following:

• General-purpose registers (GPRs).

— The thirty-two 64-bit GPRs (GPR0–GPR31) serve as data source or destination registers for

Timers (Read only)

SPE Status and Control Register

instructions affect only the lower 32 bits of the GPRs. SPE and EFP instructions are provided that operate on the entire 64-bit register.

• Condition register (CR).

— The 32-bit CR consists of eight 4-bit fields, CR0–CR7, that reflect results of certain arithmetic operations and provide a mechanism for testing and branching. See “Condition Register (CR),”

in Chapter 3, “Branch and Condition Register Operations of the EREF.

The remaining user-level registers are SPRs. Note that the Power ISA embedded category architecture provides the mtspr and mfspr instructions for accessing SPRs.

• Integer exception register (XER).

— The XER indicates overflow and carries for integer operations. See “XER Register (XER),” in Chapter 4, “Integer Operations” of the EREF for more information.

• Link register (LR).

— The LR provides the branch target address for the branch [conditional] to link register instructions (bclr, bclrl, se_blr, se_blrl). It holds the address of the instruction that follows a branch and link instruction, typically used for linking to subroutines. See “Link Register (LR)”, in Chapter 3, “Branch and Condition Register Operations” of the EREF.

• Count register (CTR).

— The CTR holds a loop count that can be decremented during execution of appropriately coded branch instructions. The CTR also provides the branch target address for the branch

[conditional] to count register instructions (bcctr, bcctrl, se_bctr, se_bctrl). See “Count Register (CTR)”, in Chapter 3, “Branch and Condition Register Operations” of the EREF.

• Time base upper (TBU) and time base lower (TBL)

— The time base facility (TB) consists of two 32-bit registers. These two registers are accessible in a read-only fashion to user-level software. See “Time Base”, in Chapter 8, “Timer Facilities”

of the EREF.

• SPRG4—SPRG7

— The Power ISA embedded category architecture defines software-use special purpose registers (SPRGs). SPRG4 through SPRG7 are accessible in a read-only fashion by user-level software.

e200 does not allow user mode access to the SPRG3 register (defined as implementation dependent by Power ISA).

• USPRG0

— The Power ISA embedded category architecture defines user software-use special purpose register USPRG0, which is accessible in a read-write fashion by user-level software.

2.1.2 Supervisor-level Registers

Supervisor-level software has access to additional control and status registers used for configuration, exception handling, and other operating system functions in addition to the registers accessible in user-mode. The Power ISA embedded category architecture defines the following supervisor-level registers:

• Processor Control registers

— Machine state register (MSR)

The MSR defines the state of the processor. The MSR can be modified by the move to machine state register instruction (mtmsr), system call instructions (sc, se_sc), and return from

exception instructions (rfi, rfci, rfdi, rfmci, se_rfi, se_rfci, se_rfdi, se_rfmci). It can be read by the move from machine state register instruction (mfmsr) . When an interrupt occurs, the contents of the MSR are saved to one of the machine state save/restore registers: SRR1, CSRR1, DSRR1, MCSRR1.

— Processor version register (PVR)

This register is a read-only register that identifies the version (model) and revision level of the processor.

— Processor Identification Register (PIR)

This read/write register is provided to distinguish the processor from other processors in the system.

• Storage Control register

— Process ID Register (PID, also referred to as PID0).

This register is provided to indicate the current process or task identifier. It is used by the MMU as an extension to the effective address, and by external Nexus 2/3 modules for ownership trace message generation. The Power ISA allows multiple PIDs; the e200z4 implements only one.

• Interrupt Registers

— Data exception address register (DEAR)

After most Data Storage Interrupts (DSI), or on an Alignment Interrupt or Data TLB Miss Interrupt, the DEAR is set to the effective address (EA) generated by the faulting instruction.

— SPRG0–SPRG7, USPRG0

The SPRG0–SPRG7 and USPRG0 registers are provided for operating system use. The e200 does not allow user-mode access to the SPRG3 register (defined as implementation dependent by Power ISA embedded category architecture).

— Exception syndrome register (ESR)

The ESR register provides a syndrome to differentiate between the different kinds of exceptions which can generate the same interrupt.

— Interrupt vector prefix register (IVPR) and the interrupt vector offset registers (IVOR0-IVOR15, IVOR32-IVOR34)

These registers together provide the address of the interrupt handler for different classes of interrupts.

— Save/restore register 0 (SRR0)

The SRR0 register is used to save machine state on a non-critical interrupt. It contains the address of the instruction at which execution resumes when an rfi or se_rfi instruction is executed at the end of a non-critical class interrupt handler routine.

— Critical save/restore register 0 (CSRR0)

The CSRR0 register is used to save machine state on a critical interrupt. It contains the address

— Save/restore register 1 (SRR1)

The SRR1 register is used to save machine state from the MSR on non-critical interrupts and to restore machine state when an rfi or se_rfi executes.

— Critical save/restore register 1 (CSRR1)

The CSRR1 register is used to save machine state from the MSR on critical interrupts and to restore machine state when rfci or se_rfci executes.

• Debug facility registers

— Debug control registers (DBCR0–DBCR2)

These registers provide control for enabling and configuring debug events.

— Debug status register (DBSR)

This register contains debug event status.

— Instruction address compare registers (IAC1–IAC4)

These registers contain addresses and/or masks which are used to specify instruction address compare debug events.

— Data address compare registers (DAC1–2)

These registers contain addresses and/or masks which are used to specify data address compare debug events.

— Data value compare registers (DVC1–2)

These registers contain data values which are used to specify data value compare debug events.

• Timer Registers

— Time base (TB)

The TB is a 64-bit structure provided for maintaining the time of day and operating interval timers. The TB consists of two 32-bit registers: TBU and TBL. The time base registers can be written to only by supervisor-level software, but can be read by both user and supervisor-level software.

— Decrementer register (DEC)

This register is a 32-bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay.

— Decrementer auto-reload (DECAR)

This register is provided to support the auto-reload feature of the decrementer.

— Timer control register (TCR)

This register controls decrementer, fixed-interval timer, and watchdog timer options.

— Timer status register (TSR)

This register contains status on timer events and the most recent watchdog timer-initiated processor reset.