REGISTER BITS

In document DP83261-2 (Page 41-47)

DP8326 6.0 Control Information (Continued)Option Register (Continued)

REGISTER BITS

D7 D6 D5 D4 D3 D2 D1 DO

RLVD TKPASS TKCAPT CBERR DUPTOK TRTEXP TVXEXP ENTRMD

Bit Symbol Description

DO ENTRMD Enter Restricted Mode Mask: This bit is used to mask TELRO.ENTRMD.

D1 TVXEXP TVX Expired Mask: This bit is used to mask TELRO.TVXEXP.

D2 TRTEXP TRT Expired and Set Late_Flag Mask: This bit is used to mask TELRO.TRTEXP.

D3 DUPTOK Duplicated Token Received Mask: This bit is used to mask TELRO.DUPTOK.

D4 CBERR Claim/Beacon Error Mask: This bit is used to mask TELRO.CBERR.

D5 TKCAPT Token Captured Mask: This bit is used to mask TELRO.TKCAPT.

D6 TKPASS Token Passed Mask: This bit is used to mask TELRO.TKPASS.

D7 RLVD Ring Latency Valid Mask: This bit is used to mask TELRO.RLVD.

2-170

Counter Increment Latch Register (CILR)

The Counter Increment Latch Register (CILR) records the occurrence of any increment to the Event Counters. Each bit corresponds to a counter and is set when the corresponding counter is incremented. Each bit may be masked via the Counter Increment Mask Register (CIMR).

ACCESS RULES

6.0 Control Information

(Continued)

Address Read Write

18h Always Condition

REGISTER BITS

D7 D6 D5 D4 D3 D2 D1 DO

RES TKRCVD FRTRX FRNCOP FRCOP FRLST FREI FRRCV

Bit Symbol Description

DO FRRCV Frame Received: Is set when the Frame Received Counter (FRCT) is incremented, indicating the reception of a frame.

D1 FREI Frame Error Isolated: Is set when the Error Isolated Counter (EICT) is incremented, indicating an error has been insolated.

D2 FRLST Frame Lost Isolated: Is set when the Lost Frame Counter (LFCT) is incremented, indicating a format error has been detected in the frame.

D3 FRCOP Frame Copied: Is set when the Frame Copied Counter (FCCT) is incremented, indicating a frame has been copied.

D4 FRNCOP Frame Not Copied: Is set when the Frame Not Copied Counter (FNCT) is incremented, indicating a frame could not be copied.

D5 FRTRX Frame Transmitted: Is set when the Frame Transmitted Counter (FTCT) is incremented, indicating a frame has been transmitted.

D6 TKRCVD Token Received: Is set when the Token Received Counter (TKCT) is incremented, indicating that a token has been received.

D7 RES Reserved

83 26 1

D P 83 26

Counter Increment Mask Register (CIMR)

The Counter Increment Mask Register (CIMR) is used to mask bits from the Counter Increment Latch Register (CILR). If a bit in Register CIMR is set to One, the corresponding bit in Register CILR will be applied to the Interrupt Condition Register, which can then be used to generate an interrupt.

All bits in this register are set to Zero upon reset.

ACCESS RULES

6.0 Control Information

(Continued)

Address Read Write

19h Always Always

REGISTER BITS

D7 D6 D5 D4 D3 D2 D1 DO

RES TKRCVD FRTRX FRNCOP FRCOP FRLST FREI FRRCV

Bit Symbol Description

DO FRRCV Frame Received Counter Increment Mask: This bit is used to mask CILR.FRRCV.

D1 FREI Error Isolated Counter Increment Mask: This bit is used to mask CILR.FREI.

D2 FRLST Lost Frame Counter Increment Mask: This bit is used to mask CILR.FRLST.

D3 FRCOP Frame Copied Counter Increment Mask: This bit is used to mask CILR.FRCOP.

D4 FRNCOP Frame Not Copied Counter Increment Mask: This bit is used to mask CILR.FRNCOP.

D5 FRTRX Frame Transmitted Counter Increment Mask: This bit is used to mask CILR.FRTRX.

D6 TKRCVD Token Received Counter Increment Mask: This bit is used to mask CILR.TKRCVD.

D7 RES Reserved

2-172

Counter Overflow Latch Register (COLR)

The Counter Overflow Latch Register (COLR) records carry events from the 20th bit of the Event Counters. Each bit in the COLR corresponds to an individual counter. Each bit may be masked via the Counter Overflow Mask Register (COMR).

ACCESS RULES

6.0 Control Information

(Continued)

Address Read Write

1Ch Always Condition

REGISTER BITS

D7 D6 D5 D4 D3 D2 D1 DO

RES TKRCVD FRTRX FRNCOP FRCOP FRLST FREI FRRCV

Bit Symbol Description

DO FRRCV Frame Received: Is set to One when the Frame Received Counter (FRCT) overflows.

D1 FREI Frame Error Isolated: Is set to One when the Error Isolated Counter (EICT) overflows.

D2 FRLST Frame Lost Isolated: Is set to One when the Lost Frame Counter (LFCT) overflows.

D3 FRCOP Frame Copied: Is set to One when the Frame Copied Counter (FCCT) overflows.

D4 FRNCOP Frame Not Copied: Is set to One when the Frame Not Copied Counter (FNCT) overflows.

D5 FRTRX Frame Transmitted: Is set to One when the Frame Transmitted Counter (FTCT) overflows.

D6 TKRCVD Token Received: Is set to One when the Token Received Counter (TKCT) overflows.

D7 RES Reserved

83 26 1

D P 83 26

Counter Overflow Mask Register (COMR)

The Counter Overflow Mask Register (COMR) is used to mask bits from the Counter Overflow Latch Register (COLR). If a bit in Register COMR is set to One, the corresponding bit in Register COLR will be applied to the Interrupt Condition Register, which can then be used to generate an interrupt.

All bits in this register are set to Zero upon reset.

ACCESS RULES

6.0 Control Information

(Continued)

Address Read Write

1Dh Always Always

REGISTER BITS

D7 D6 D5 D4 D3 D2 D1 DO

RES TKRCVD FRTRX FRNCOP FRCOP FRLST FREI FRRCV

Bit Symbol Description

DO FRRCV Frame Received Counter Overflow Mask: This bit is used to mask COLR.FRRCV.

D1 FREI Error Isolated Counter Overflow Mask: This bit is used to mask COLR.FREI.

D2 FRLST Lost Frame Counter Overflow Mask: This bit is used to mask COLR.FRLST.

D3 FRCOP Frame Copied Counter Overflow Mask: This bit is used to mask COLR.FRCOP.

D4 FRNCOP Frame Not Copied Counter Overflow Mask: This bit is used to mask COLR.FRNCOP.

D5 FRTRX Frame Transmitted Counter Overflow Mask: This bit is used to mask COLR.FRTRX.

D6 TKRCVD Token Received Counter Overflow Mask: This bit is used to mask COLR.TKRCVD.

D7 RES Reserved

2-174

Internal Event Latch Register (IELR)

The Internal Event Latch Register (IELR) reports internal errors in the BMAC device. These errors include MAC Parity errors and inconsistencies in the Receiver and Transmitter state machines.

After an internal state machine is detected and reported (bit RSMERR for the receiver and TSMERR for the transmitter), the Current Receive Status Register (CRSO) and Current Transmit Status Register (CTSO) continue to be updated as normal.

Errors internal to the BMAC device cause a MAC_Reset.

ACCESS RULES

Address Read Write

6.0 Control Information

(Continued)

28h Always Condition

REGISTER BITS

D7 D6 D5 D4 D3 D2 D1 DO

RES RES RES RES TSMERR RSMERR RES MPE

Bit Symbol Description

DO MPE MAC Interface Parity Error: Indicates a Parity Error on the MAC Request Data pins (MRD7-0) when parity is enabled on the MA_Request Interface (bits MRP of the Mode Register is set and pin TXACK is asserted).

D1 RES Reserved

D2 RSMERR Receive State Machine Error: Indicates inconsistency in the Receiver state machine. When set, causes bit MCRST of the Function Register to be set.

D3 TSMERR Transmit State Machine Error: Indicates inconsistency in the Transmitter state machine. When set, causes bit MCRST of the Function Register to be set.

D4-7 RES Reserved

83 26 1

D P 83 26 6.0 Control Information

(continued)

In document DP83261-2 (Page 41-47)