Remote Interface and Arbitration System (RIAS) (Continued) In addition, WAIT can delay the rising edge of XACK

In document DP8344B (Page 69-72)

indefi-nitely. One T-state after XACK rises,ÀRICÓwill once again be active on AD. Timing is similar for a Remote Write. AD is in TRI-STATE while LCL is high. LCL is asserted for a mini-mum of three T-states, but can be extended by instruction wait states and the WAIT pin. IWR clocks the instruction into memory during the write of the high byte. The Instruc-tion Address (PC) is incremented about one T-state after LCL falls on a high byte access for both Remote Reads and Writes.

Soft-loading Instruction Memory is accomplished by first setting the BCP Program Counter to the starting address of the program to be loaded. The Memory Select bits are then set to IMEM. BCP instructions can then be moved from the Remote Processor to the BCPÐlow byte, high byteÐuntil the entire program is loaded.

4.1.3 Interface Modes

The Remote Interface and Arbitration System will support TRI-STATE buffers or latches between the Remote Proces-sor and the BCP. The choice between buffers and latches depends on the type of system that is being interfaced to.

Latches will help prevent the faster system from slowing to the speed of the slower system. Buffers can be used if the Remote Processor (RP) requires that data be handshaked between the systems.

Figure 4-9 shows the timing of Remote Reads via a buffer (a) and a latch (b) (called a Buffered Read and Latched Read). The main difference in these modes is in the Termi-nation Phase. The Buffered Read handshakes the data back to the RP. When the BCP deasserts XACK, data is valid and the RP can deassert REM-RD. Only after REM-RD goes high is LCL removed. In the Latched ReadFigure 4-9(b) XACK rises at the same time, but the Termination Phase completes without waiting for the rising edge of REM-RD. One half T-state after XACK rises, INT-READ

ris-es and one half T-state later LCL falls. The BCP can use the buses one T-state after LCL falls. The minimum time (no wait states, no arbitration delay) the BCP CPU could be pre-vented from using the bus is four T-states in the Latched Read Mode.

A Buffered Read prevents the BCP CPU from using the bus during the time RP is allocated the buses. This time period begins when LCL rises and ends when REM-RD is re-moved. If the REM-RD is asserted longer than the minimum Buffered Read execution time (four T-states), then the BCP may be unnecessarily prevented from using the buses.

Therefore, if there are no overriding reasons to use the Buff-ered Read Mode, the Latched Read Mode is preferable.

There are three Remote Write ModesÐtwo require buffers and one requires latches. The timing for the writes utilizing buffers is shown inFigure 4-10 . The Slow Buffered Write (a) is handshaked in the same manner as the Buffered Read and thus has the same timing. The Fast Buffered Write has similar timing to the Latched Read. This timing similarity ex-ists because the BCP terminates the remote access without waiting for the RP to deassert REM-WR.

In both cases, XACK falls a short delay after REM-WR falls and LCL rises when the RP is given the buses. One T-state after LCL rises, INT-WRITE falls. The termination in the Slow Buffered Write mode keys off REM-WR rising, as shown inFigure 4-10(a) . INT-WRITE rises a prop-delay later and LCL falls one T-state later. The Fast Buffered Write, shown inFigure 4-10(b) , begins the Termination Phase with the rising edge of XACK. INT-WRITE rises at the same time as XACK, and LCL falls one T-state later. The BCP can begin a local access one T-state after LCL transitions.

A Fast Buffered Write is preferable to the Slow Buffered Write if RP’s write cycles are slow compared to the mini-mum Fast Buffered Write execution time. The Fast Buffered Write assumes, though, that data is available to the BCP by the time INT-WRITE rises.

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(a) Buffered Read TL/F/9336 – 92

(b) Latched Read FIGURE 4-9. Read from Remote Processor

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(a) Slow Buffered Write

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(b) Fast Buffered Write

FIGURE 4-10. Buffered Write from Remote Processor In both Buffered Write Modes, XACK is asserted to wait the

RP. The Latched Write Mode makes it possible for the RP to write to the BCP without getting waited. The timing for the Latched Write Mode is shown inFigure 4-11 . When the Re-mote Processor writes to the BCP, its address and data buses are externally latched on the rising edge of REM-WR.

Even though REM-WR has been asserted XACK does not

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FIGURE 4-11. Latched Write from Remote Processor

switch. The BCP only begins remote access execution after the trailing edge of REM-WR. Since the RP is not requesting data back from the BCP, it can continue execution without waiting for the BCP to complete the remote access. After REM-WR is deasserted, WR-PEND is taken low to prevent overwrite of the latches. A minimum of two T-states later LCL switches and AD, A, and the external address latch go into TRI-STATE, allowing the latches which contain the re-mote address and data to become active. If the RP attempts to initiate another access before the current write is com-plete, XACK is taken low to wait the RP and the address and the data are safe because WR-PEND prevents the latches from opening. The Access Phase ends when INT-WRITE rises and the data is written. One T-state later, LCL falls and one T-state after that WR-PEND rises. If an-other access is pending, it can begin in the next T-state.

This is indicated by XACK rising when WR-PEND rises.

A minimum BCP/RP interface utilizes four TRI-STATE buff-ers or latches. A block diagram of this interface is shown in Figure 4-12 . The blocks A, B, C, and D indicate the location of buffers or latches. Blocks A and B isolate 16 bits of the RP’s address bus from the BCP’s Data Address bus. Two more blocks, C and D, bidirectionally isolate 8 bits of the RP’s data bus from the BCP AD bus.

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FIGURE 4-12. Minimum BCP/Remote Processor Interface The BCP Remote Arbitrator State Machine (RASM) must

know what hardware interfaces to the RP in order to time the remote accesses correctly. To accomplish this, three Interface Mode bits inÀRICÓare used to define the hard-ware interface. These bits are the Latched Write bit [LW], the Latched Read bit [LR] and the Fast Buffered Write bit [FBW]. See Figure 4-13 .

7 6 5 4 3 2 1 0

BIS SS FBW LR LW ST MS1 MS0

X ä Y

Interface Mode Bits – 0 – - Buffered Read – 1 – - Latched Read 0 – 0 - Slow Buffered Write 1 – 0 - Fast Buffered Write X – 1 - Latched Write FIGURE 4-13. Interface Mode Bits

All combinations of Remote Reads or Writes with buffers or latches can be configured via the Interface Mode bits. A Buffered Read is accomplished by using a buffer for block D and setting [LR]e0. Conversely, using a latch for block D and setting [LR] e 1 configures the RASM for Latched Reads. Using buffers for blocks A, B, and C and setting [LW]e0 allows either a Slow or Fast Buffered Write. Set-ting [FBW]e0 configures RASM for a Slow Buffered Write

and [FBW] e 1 designates a Fast Buffered Write. A Latched Write is accomplished by using latches for blocks A, B, and C and setting [LW]e1.

4.1.4 Execution Control

The BCP can be started and stopped in two ways. If the BCP is not interfaced to another processor, it can be started by pulsing RESET low while both REM-RD and REM-WR are low. Execution then begins at location zero. If there is a Remote Processor interfaced to the BCP, a write toÀRICÓ which sets the start bit [STRT] high will begin execution at the current PC location. Writing a zero to [STRT] stops exe-cution after the current instruction is completed. A Single-Step is accomplished by writing a one to the Single-Single-Step bit [SS] inÀRICÓ. This will execute the instruction at the current PC, increment the PC, and then return to idle. [SS] returns low after the single-stepped instruction has completed. [SS]

is a write only bit and will always appear low whenÀRICÓis read.

Two pins (WAIT and LOCK), and one register bit, [LOR], can also affect the BCP CPU or RIAS execution. The WAIT pin can be used to add wait states to a remote access.

When WAIT must be asserted low to add wait states is de-pendent on which remote access mode is being used. The information needed to calculate when WAIT must be assert-ed to add wait states, is containassert-ed within the individual de-scriptions of the modes in the next section (4.2 RIAS Func-tional Description).

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In document DP8344B (Page 69-72)