This mode executes a write without waiting the Remote ProcessorÐXACK isn’t normally taken low. The complete flow chart for the Latched Write mode is shown inFigure 4-22 . Until a Remote Write is initiated (RAE*REM-WR true), the state machine (RASM) loops in state RSA. If the BCP CPU needs to access Data Memory at this time (and LOCK is high), it can still do so. A local access is requested by the Timing Control Unit asserting the Local Bus Request (LCL-BREQ) signal. A local bus grant will be given by RASM if the buses are not being used (as is the case in RSA).
RASM will move into RSB on the next clock after RAE*REM-WR is asserted. XACK is not taken low and therefore the RP is not waited. The state machine will loop in RSBuntil the RP terminates its write cycleÐuntil RAE*REM-WR is no longer true. The external address and data latches are typically latched on the trailing edge of REM-WR. A local bus request will still be serviced in this state.
Next, RASM enters RSCand WR-PEND is asserted to pre-vent overwrite of the external latches. Since the RP has completed its write cycle, another write or read can happen at any time. Any Remote Read cycle (RAE*REM-RD) or Remote Write cycle (RAE*REM-WR) occurring after the state machine enters RSCwill take XACK low. A local ac-cess initiated before or during this state must be completed before RASM can move to RSD. Once RSD is entered, though, no further local bus requests will be granted until RASM enters the Termination Phase. If the BCP CPU initi-ates a Data Memory access after RSC, the Timing Control Unit will be waited and the BCP CPU will remain in state TWr until the RASM enters RSH. Half a T-state after entering RSBthe A and AD buses go into TRI-STATE.
On the next clock, the state machine enters RSEand LCL is taken high. WR-PEND continues to be asserted low in this state and the data and instruction wait state counters, iDW and iIW, are loaded from [DW2 – 0] and [IW1 – 0], respective-ly, inÀDCRÓ. The A and AD buses remain in TRI-STATE and the Access Phase begins. Any remote accesses now occurring will take XACK low and wait the Remote Proces-sor. If the Remote Access is to IMEM and the high instruc-tion byte flag is set (i.e., HIBe1), then IWR is asserted low in RSE.
The state machine will move into one of several states on the next clock, depending on the state of CMD and [MS1 – 0]. WR-PEND remains low and LCL remains high in all the possible next states. If CMD is high, the access is to ÀRICÓand the next state will be RSF1. The path from AD to ÀRICÓopens in this state. Any remote access mode chang-es made by this write will not take effect until one T-state after the completion of the present write.
The five other next states all have CMD low and depend on the Memory Select bits. If [MS1 – 0] is 10 or 11 the state machine will enter either RSF2or RSF3and the low or high bytes of the Program Counter, respectively, will be loaded.
[MS1 – 0] e 00 designates a Data Memory access and moves RASM into RSF4. WRITE will be asserted low in this state and A and AD continue to be tri-stated. This allows the Remote Processor to drive the Data Memory address and data for the write. Since DMEM is subject to wait states, RSF4is looped upon until all the programmed Data Memory wait states have been inserted.
The last possible Memory Selection is Instruction Memory, [MS1 – 0]e01. The two possible next states for IMEM de-pend on if RASM is expecting the low byte or high byte.
Instruction words are accessed low byte then high byte and RASM powers up expecting the low Instruction byte. The internal flag that keeps track of the next expected Instruc-tion byte is called the High InstrucInstruc-tion Byte flag (HIB). If HIB is low, the next state is RSF5and the low instruction byte is written into the holding register, ILAT. If HIB is high, the high instruction byte is moved to I15 – 8 and the value in ILAT is moved to I7 – 0. At the same time, IWR is asserted low and the write to Instruction Memory is begun. An IMEM access, like a DMEM access, is subject to wait states and these states will be looped on until all programmed instruction memory wait states have been inserted.
Note:Resetting the BCP will reset HIB (i.e., HIBe0). Writing 01 to the Memory Select bits inÀRICÓ(i.e., [MS1–0]e01, pointing to IMEM) will also force HIB to zero. This way the instruction word boundary can be reset without resetting the BCP.
All the RSFstates converge to a single decision box that tests WAIT. If WAIT is low then the state machine loops back to RSF, otherwise RASM will move on to RSG. LCL remains high and WR-PEND remains low in this state but the actions specific to the RSF states have ended (i.e.
WRITE will no longer be asserted low).
The next CPU-CLK moves RASM into RSH, the last state in the state machine. LCL returns low but WR-PEND is still low. The A and AD buses remain in TRI-STATE for the first half of RSH. XACK will be taken low if a Remote Access is initiated. If the just completed access was to IMEM, HIB will be switched. Also, the PC will be incremented if the high byte was written. A local access will be granted if LCL-BREQ is asserted in this state.
If another Remote Write is pending, the state machine takes the path to RSBwhere that write will be processed. A pend-ing Remote Read will return to the RSAin either the Buff-ered or Latched Read sections (not shown inFigure 4-22 ) of the state machine. And if no Remote Access is pending, the machine will loop in RSAuntil the next access is initiat-ed.
InFigure 4-23 , the BCP is executing the first of two Data Memory writes when REM-WR goes low. The BCP takes no action until REM-WR goes back high, latching the data and making a remote access request. The BCP responds to this by taking WR-PEND low. At the end of the first instruction, although the BCP begins its second write by taking ALE high, RASM now takes control of the bus and deasserts LCL high at the end of T1. A one T-state delay is built into this transfer to ensure that WRITE has been deasserted high before the data bus is switched. Timing Control Unit is now waited, inserting remote access wait states, TWr, as RASM takes over.
The remote address is permitted one T-state to settle on the BCP address bus before WRITE goes low. WRITE then re-turns high one T-state plus the programmed Data Memory wait state, TWdlater, having satisfied the memory access time, and one T-state later LCL is reasserted low, transfer-ring bus control back to the BCP.
In this example, REM-WR goes low again during the remote write cycle which, since WR-PEND is still low, causes XACK to go low to wait the Remote Processor. Then LCL goes low, allowing the second data byte to be latched on the next trailing edge of REM-WR. One T-state later. XACK and WR-PEND go back high at the same time.
Obsolete
4.0 Remote Interface and Arbitration System (RIAS)
(Continued)TL/F/9336–A1 FIGURE4-22.FlowChartofLatchedWriteMode
Obsolete
4.0 Remote Interface and Arbitration System (RIAS)
(Continued)TL/F/9336–31 RegisterConfiguration:OtherBCPControlSignals: ÐOneWait-StateProgrammedforData-MemoryRAEe0 ÐZeroWait-StatesProgrammedforInstruction-MemoryCMDe0 ÐÀRICÓContents:XXXX1100REM-RDe1 Ð
[LOR ]e0LOCKe1 FIGURE4-23.LatchedWritetoDataMemorybyRemoteProcessor