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Remote Interface and Arbitration System (RIAS) (Continued) Until a Remote Read is initiated (RAE*REM-RD true), the

W dokumencie DP8344B-2 (Stron 75-78)

KEY TO REGISTERS

4.0 Remote Interface and Arbitration System (RIAS) (Continued) Until a Remote Read is initiated (RAE*REM-RD true), the

state machine (RASM) loops in state RSa i- If a Remote Read is initiated and [LOR] is set high, RASM will move to state RSa2- Likewise, if a Remote Read is initiated while the buses have been granted locally (i.e., Local Bus Grant = 1 ), RASM will move to state RSa2- The state machine will loop in state RSa2. as long as [LOR] is set high or the buses are granted locally. If the BCP CPU needs to access Data Mem­

ory while in either RSa state (and LOCK is high), it can still do so. A local access is requested by the Timing Control Unit asserting the Local Bus Request (LCL-BREQ) signal. A local bus grant will be given by RASM if the buses are not being used (as is the case in RSa).

XACK is taken low as soon as RAE*REM-RD is true, re­

gardless of an ongoing local access. If [LOR] is low, RASM will move into RSg on the next clock after RAE*REM-RD is asserted and there is no local bus request. No further local bus requests will be granted until RASM enters the Termina­

tion Phase. If the BCP CPU initiates a Data Memory access after RSa, the Timing Control Unit will be waited and the BCP CPU will remain in state Twr until the remote access reaches the Termination Phase. Half a T-state after entering RSg the A bus (and AD bus if the access is to Data Memory) goes into TRI-STATE.

On the next clock, RASM enters RSg and LCL is taken high while XACK remains low. The wait state counters, ijyv and ipw. are loaded in this state from [IW 1-0] and [DW2-0], respectively, in [DCR]. The A bus (and AD if the access is to Data Memory) now remains TRI-STATE and the Access Phase begins. Program Counter, respectively, will be read.

[MS1-0] = 00 designates a Data Memory access and moves RASM into RSp4. READ will be asserted low in this state and A and AD continue to be tri-stated. This allows the Remote Processor to drive the Data Memory address for the read. Since DMEM is subject to wait states, RSp4 is looped upon until all the wait states have been inserted.

The last possible Memory Selection is Instruction Memory, [MS1-0] = 01. The two possible next states for the IMEM access depend on if RASM is expecting the low byte or high byte. Instruction words are accessed low byte then high byte and RASM powers up expecting the low Instruction byte. The internal flag that keeps track of the next expected Instruction byte is called the High Instruction Byte flag (HIB).

If HIB is low, the next state is RSqs and the low instruction byte is MUXed to the AD bus. If HIB is high, the high instruc­

tion byte is MUXed to AD and RSpe is entered. An IMEM access, like a DMEM access, is subject to wait states and these states will be looped on until all programmed instruc­

tion memory wait states have been inserted.

Note: Resetting the BCP will reset HIB (i.e., HIB = 0). Writing 01 to the Memory Select bits in (RIC) (i.e.. [MS1-0] = 01, pointing to IMEM) will also force HIB to zero. This way the instruction word boundary can be reset without resetting the BCP.

After all of the programmed wait states are inserted in the RSp states, more wait states may be added by asserting WAIT low a half T-state before the end of the last pro­

grammed wait state. If there are no programmed wait states WAIT must be asserted low a half T-state before the end of RSp to add wait states. If WAIT remains low, the remote access is extended indefinitely. All the RSp states move to their corresponding RSg states on the CPU-CLK after the programmed wait state conditions are met and WAIT is high. LCL remains high in all RSg states and A remains in TRI-STATE (and AD if the access is to Data Memory).

XACK returns high in this state, indicating that data is valid so that it can be externally latched. The action specific to each RSp state remains in effect during the first half of the RSg cycle (i.e. READ is asserted in the first half of RSg4).

This half T-state of hold time is provided to guarantee data is latched when XACK goes high. This state begins the Ter­

mination Phase.

P 8 3 4 4 B

D P 8 3 4 4 B

On the next clock the state machine will enter RSp and LCL will return low. The A bus (and AD bus if the access is to data memory) remains in TRI-STATE for the first half T-state of RSp. After the first half of RSp, the Re­

mote Processor is no longer using the buses and the BCP CPU will be granted the buses if LCL-BREQ is asserted. If a local bus request is made, a local bus grant will be given to the Timing Control Unit. If the preceding access was a read of IMEM, then HIB is switched and if the access was to the high byte of IMEM then the PC is incremented. If RAE*

REM-RD is deasserted at this point, the next clock will bring RASM back to RS^ where it will loop until another Remote Access is initiated. RSq is entered if RAE*REM-RD is still true. RASM will loop in RSq until RAE*REM-RD is no longer active at which time the state machine will return to RSa. In Figure 4-17, the BCP is executing the first of two Data Memory reads when REM-RD goes low. In response, XACK goes low, waiting the Remote Processor. At the end of the first instruction, although the BCP begins its second write by taking ALE high, the RASM now takes control of the bus and deasserts LCL high at the end of T-|. A one T-state delay is built into this transfer to ensure that READ has been deasserted high before the data bus is switched. The Timing Control Unit is now waited, inserting remote access wait states, Twr, as RASM takes over.

The remote address is permitted one T-state to settle on the BCP address bus before READ goes low, XACK then re­

turns high one T-state plus the programmed Data Memory wait state, Tyyj later, having satisfied the memory access time. READ returns high a half T-state later, ensuring suffi­

cient hold time, followed by LCL being reasserted low after an additional half T-state, transferring bus control back to the BCP. The Remote Processor responds to XACK return­

ing high by deasserting REM-RD high, although by this time the BCP is well into its own memory read.

4.2.3 Slow Buffered Write

The timing for this mode is the same as the Buffered Read mode. The complete flow chart for the Slow Buffered Write mode is shown in Figure 4-18. Until a Remote Write is initiat­

ed (RAE*REM-WR true), the state machine (RASM) loops in state RSa p If a Remote Write is initiated and [LOR] is set high, RASM will move to state RSa2- Likewise, if a Remote Write is initiated while the buses have been granted locally (i.e., Local Bus Grant = 1 ) , RASM will move to state RSa2- The state machine will loop in state RSa2 as long as [LOR]

is set high or the buses are granted locally. If the BCP CPU needs to access Data Memory while in either RSa state (and LOCK is high), it can still do so. A local access is re­

quested by the Timing Control Unit asserting the Local Bus Request (LCL-BREQ) signal. A local bus grant will be given by RASM if the buses are not being used (as is the case in the RSa state).

XACK is taken low as soon as RAE*REM-WR is true, re­

gardless of an ongoing local access. RASM will move into RSb on the next clock after RAE*REM-WR is asserted and there is no local bus request and [LOR] = 0. No further local bus requests will be granted until the remote access is complete and RASM returns to RSa- If the BCP CPU initi­

ates a Data Memory access after RSa, the Timing Control Unit will be waited and the BCP CPU will remain in state Twr until completion of the remote access. Half a T-state after entering RSb the A and AD buses go into TRI-STATE.

On the next CPU-CLK, RASM enters RSc and LCL is taken high while XACK remains low. The wait state counters, iiw

W dokumencie DP8344B-2 (Stron 75-78)