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RIAS FUNCTIONAL DESCRIPTION

W dokumencie DP8344B (Stron 72-75)

In this section, the operation of the Remote Arbitration State Machine (RASM), is described in detail. Discussed, among other things, are the sequence of events in a remote ac-cess, arbitration of the data buses, timing of external sig-nals, when inputs are sampled, and when wait states are added. Each of the five Interface Modes is described in functional state machine form. Although each interface mode is broken out in a separate flow chart, they are all part of a single state machine (RASM). Thus the first state in each flow chart is actually the same state.

The functional state machine form is similar to a flow chart, except that transitions to a new state (states are denoted as rectangular boxes) can only occur on the rising edge of the internal CPU clock (CPU-CLK). CPU-CLK is high during the first half of its cycle. A state box can specify several actions, and each action is separated by a horizontal line. A signal name listed in a state box indicates that that pin will be asserted high when RASM has entered that state. Signals not listed are assumed low.

Note:This sometimes necessitates using the inversion of the external pin name.

This same rule applies to the A and AD buses. By default, these buses are active. The A bus will have the upper byte of the last used data address. The AD bus will display ÀRICÓ. When one of these buses appears in a state box, the condition specified will be in effect only during that state.

Decision blocks are shown as diamonds and their meaning is the same as in a flow chart. The hexagon box is used to denote a conditional stateÐnot synchronous with the clock.

When the path following a decision block encounters a con-ditional state, the action specified inside the hexagon box is executed immediately.

Also provided is a memory arbitration example in the form of a timing diagram for each of the five modes. These exam-ples show back to back local accesses punctuated by a remote access. Both the state of RASM and the Timing Control Unit are listed for every clock at the top of each timing diagram. The RASM states listed correspond to the flow charts. The Timing Control Unit states are described in Section 2.2.2, Timing portion of the data sheet.

4.2.1 Buffered Read

The unique feature of this mode is the extension of the read until REM-RD is deasserted high. The complete flow chart for the Buffered Read mode is shown inFigure 4-14. Until a Remote Read is initiated (RAE*REM-RD true), the state ma-chine (RASM) loops in state RSA1. If a Remote Read is initiated and [LOR] is set high, RASM will move to state RSA2. Likewise, if a Remote Read is initiated while the bus-es have been granted locally (i.e., Local Bus Requbus-este1), RASM will move to state RSA2. The state machine will loop in state RSA2as long as [LOR] is set high or the buses are granted locally. If the BCP CPU needs to access Data Mem-ory while in either RSAstate (and LOCK is high), it can still do so. A local access is requested by the Timing Control Unit asserting the Local Bus Request (LCL-BREQ) signal. A local bus grant will be given by RASM if the buses are not being used (as is the case in the RSAstates).

XACK is taken low as soon as RAE*REM-RD is true, re-gardless of an ongoing local access. If [LOR] is low, RASM will move into RSBon the next clock after RAE*REM-RD is true and there is no local bus request. No further local bus requests will be granted until the remote access is complete and RASM returns to RSA. Half a T-state after entering RSB the A bus (and AD bus if the access is to Data Memory) goes into TRI-STATE.

On the next CPU-CLK, RASM enters RSCand LCL is taken high while XACK remains low. The wait state counters, iIW and iDW, are loaded in this state from [IW1 – 0] and [DW2 – 0], respectively, inÀDCRÓ. The A bus (and AD if the access is to Data Memory) remains in TRI-STATE and the Access Phase begins.

The state machine can move into one of several states, depending on the state of CMD and [MS1 – 0], on the next clock. XACK remains low and LCL remains high in all the possible next states. If CMD is high, the access is toÀRICÓ and the next state will be RSD1. Since the default state of AD isÀRICÓ, it will not transition in this state.

The five other next states all have CMD low and depend on the Memory Select bits. If [MS1 – 0] is 10 or 11 the state machine will enter either RSD2or RSD3and the low or high bytes of the Program Counter, respectively, will be read.

[MS1 – 0] e 00 designates a Data Memory access and moves RASM into RSD4. READ will be asserted in this state and A and AD continue to be in TRI-STATE. This allows the Remote Processor to drive the Data Memory address for the read. Since DMEM is subject to wait states, RSD4is looped upon until all the wait states have been inserted.

Obsolete

4.0 Remote Interface and Arbitration System (RIAS)

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TL/F/933697 FIGURE4-14.FlowChartofBufferedReadMode

Obsolete

4.0 Remote Interface and Arbitration System (RIAS)

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TL/F/933627 RegisterConfiguration:OtherBCPControlSignals: ÐOneWait-StateProgrammedforData-MemoryRAEe0 ÐZeroWait-StatesProgrammedforInstruction-MemoryCMDe0 ÐÀRICÓContents:XXX0X100REM-WRe1 Ð

[LOR ]e0LOCKe1 FIGURE4-15.BufferedReadofDataMemorybyRemoteProcessor

Obsolete

4.0 Remote Interface and Arbitration System (RIAS)

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W dokumencie DP8344B (Stron 72-75)