Signal Processing/Embedded Floating-Point Status and Control Register (SPEFSCR)

SPEFSCR, shown in Figure 2-10, is used for status and control of SPE and embedded floating-point instructions.

32 63

Field Link address

Reset Undefined on m_por assertion, unchanged on p_reset_b assertion

R/W R/W

SPR SPR 8

Figure 2-9. Link Register (LR)

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Field SOVH OVH FGH FXH FINVH FDBZH FUNFH FOVFH — FINXS FINVS FDBZS FUNFS FOVFS MODE

Reset 0000_0000_0000_0000

R/W R/W

48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Field SOV OV FG FX FINV FDBZ FUNF FOVF — FINXE FINVE FDBZE FUNFE FOVFE FRMC

Reset 0000_0000_0000_0000

R/W R/W

SPR SPR 512

Figure 2-10. Signal Processing and Embedded Floating-Point Status and Control Register (SPEFSCR)

High-Word Error Bits Status Bits

Enable Bits

Table 2-9 describes SPEFSCR fields.

Table 2-9. SPEFSCR Field Descriptions

Bits Name Description

32 SOVH Summary integer overflow high. Set whenever an instruction sets OVH and remains set until it is cleared by an mtspr specifying the SPEFSCR.

33 OVH Integer overflow high. Set whenever an integer or fractional SPE instruction signals an overflow in the upper half of the result.

34 FGH Embedded floating-point guard bit high. For use by the floating-point round exception handler. It is cleared by a floating-point data exception for the high elements. FGH corresponds to the high element result. FGH is cleared by a scalar floating-point instruction.

35 FXH Embedded floating-point sticky bit high. Supplied for use by the floating-point round exception handler.

Zeroed if a floating-point data exception occurred for the high elements. FXH corresponds to the high element result. FXH is cleared by a scalar floating point instruction.

36 FINVH Embedded floating-point invalid operation/input error high.

In mode 0, set if the A or B high element operand of a floating-point instruction is Infinity, NaN, or Denorm, or if the operation is a divide and the high element dividend and divisor are both 0.

In mode 1, FINVH is set on an IEEE754 invalid operation (IEEE754-1985 sec7.1) in the high element. Cleared by a scalar floating-point instruction.

37 FDBZH Embedded floating-point divide by zero high. Set when a floating-point divide instruction executes with a high element divisor of 0 and the high element dividend is a finite non-zero number. Cleared by a scalar floating-point instruction.

38 FUNFH Embedded floating-point underflow high. Set when the execution of a floating-point instruction results in an underflow in the high element. FUNFH is cleared by a scalar floating-point instruction.

39 FOVFH Embedded floating-point overflow high. Set when the execution of a floating-point instruction results in an overflow in the high element. Cleared by a scalar floating point instruction.

40–41 — Reserved, should be cleared.

42 FINXS Embedded floating-point inexact sticky flag. Set under one of the following conditions:

• The execution of a floating-point instruction delivers an inexact result for either the low or high element and no floating-point data exception is taken for either element

• A floating-point instruction causes overflow (FOVF=1 or FOVFH=1), but floating-point overflow exceptions are disabled (FOVFE=0)

• A floating-point instruction results in underflow (FUNF=1 or FUNFH=1), but floating-point underflow exceptions are disabled (FUNFE=0) and no floating-point data exception occurs.

FINXS remains set until it is cleared by an mtspr specifying SPEFSCR.

43 FINVS Embedded floating-point invalid operation sticky flag. Set when a floating-point instruction sets FINVH or FINV. FINVS remains set until it is cleared by an mtspr instruction specifying SPEFSCR.

44 FDBZS Embedded floating-point divide by zero sticky flag. Set when a floating-point divide instruction sets FDBZH or FDBZ. FDBZS remains set until it is cleared by an mtspr specifying SPEFSCR.

45 FUNFS Embedded floating-point underflow sticky flag. Set when a floating-point instruction sets FUNFH or FUNF.

FUNFS remains set until it is cleared by an mtspr specifying SPEFSCR.

46 FOVFS Embedded floating-point overflow sticky flag. Set when a floating-point instruction sets FOVFH or FOVF.

FOVFS remains set until it is cleared by an mtspr specifying SPEFSCR.

47 MODE Embedded floating-point operating mode.

0 Default hardware results operating mode. The e200z3 supports only mode 0.

1 IEEE754 hardware results operating mode (not supported by the e200z3).

Controls the operating mode of the embedded floating-point APU. Software should read the value of this bit after writing it to determine whether the implementation supports the selected mode. Implementations return the value written if the selected mode is supported. Otherwise, the value read indicates the

hardware-supported mode.

48 SOV Summary integer overflow. Set when an instruction sets OV. SOV remains set until it is cleared by an mtspr specifying SPEFSCR.

49 OV Integer overflow. Set whenever an integer or fractional SPE instruction signals an overflow in the low element result.

50 FG Embedded floating-point guard bit. Used by the floating-point round exception handler. Cleared if a floating-point data exception occurs for the low elements. Corresponds to the low element result.

51 FX Embedded floating-point sticky bit. For use by the floating-point round exception handler. FX is cleared if a floating-point data exception occurs for the low elements. FX corresponds to the low element result.

52 FINV Embedded floating-point invalid operation/input error. In mode 0, FINV is set if the A or B low element operand of a floating-point instruction is Infinity, NaN, or Denorm, or if the operation is a divide and the low element dividend and divisor are both 0. In mode 1, FINV is set on an IEEE754 invalid operation (IEEE754-1985 sec7.1) in the low element.

53 FDBZ Embedded floating-point divide by zero. Set when a floating-point divide instruction executes with a low element divisor of 0 and the low element dividend is a finite non-zero number.

54 FUNF Embedded floating-point underflow. Set when the execution of a floating-point instruction results in an underflow in the low element.

55 FOVF Embedded floating-point overflow. Set when the execution of a floating-point instruction results in an overflow in the low element.

56 — Reserved, should be cleared.

57 FINXE Embedded floating-point inexact exception enable. If the exception is enabled, a floating-point round exception is taken under one of the following conditions:

• For both elements, the result of a floating-point instruction does not result in overflow or underflow, and the result for either element is inexact (FG | FX = 1.

• FGH | FXH =1)

• The result of a floating-point instruction does result in overflow (FOVF=1 or FOVFH=1) for either element, but floating-point overflow exceptions are disabled (FOVFE=0)

• The result of a floating-point instruction results in underflow (FUNF=1 or FUNFH=1), but floating-point underflow exceptions are disabled (FUNFE=0), and no floating-point data exception occurs.

0 Exception disabled.

1 Exception enabled.

58 FINVE Embedded floating-point invalid operation/input error exception enable.

0 Exception disabled.

1 Exception enabled. A floating-point data exception is taken if FINV or FINVH is set by a floating-point instruction.

59 FDBZE Embedded floating-point divide by zero exception enable.

0 Exception disabled.

1 Exception enabled. A floating-point data exception is taken if FDBZ or FDBZH is set by a floating-point instruction.

Table 2-9. SPEFSCR Field Descriptions (continued)

Bits Name Description

2.7.2 Accumulator (ACC)

The 64-bit architectural accumulator register holds the results of the multiply accumulate (MAC) forms of SPE integer instructions. The accumulator allows back-to-back execution of dependent MAC instructions, as in the inner loops of DSP code such as finite impulse response (FIR) filters. The accumulator is partially visible to the programmer in that its results do not have to be explicitly read to use them. Instead, they are always copied into a 64-bit destination GPR specified as part of the instruction. However, the accumulator must be explicitly initialized when a new MAC loop starts. Based upon the type of instruction, an accumulator can hold either a single 64-bit value or a vector of two 32-bit elements.

The Initialize Accumulator instruction (evmra) initializes the accumulator. This instruction is described in the EREF.

2.8 Interrupt Registers

This section describes the registers for interrupt handling.

2.8.1 Interrupt Registers Defined by Book E