The imaging subsystem deals with the processing of the pixel data coming from an external image sensor or from video and graphics digitizer. It is a key component for the following multimedia applications: video

preview, camera viewfinder, video record and still image capture. It supports RAW, RGB, and YUV data processing.

Table 6-24 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 6-23 and Figure 6-24).

Table 6-23. CPI Timing Conditions—Video and Graphics Digitizer 1.8-V Mode

TIMING CONDITION PARAMETER VALUE UNIT

MIN MAX

Input Conditions

tR Input signal rise time 80 1800 ps

tF Input signal fall time 80 1800 ps

Table 6-24. CPI Timing Requirements—Video and Graphics Digitizer 1.8-V Mode

^{(4) (6)}

NO. PARAMETER OPP100 UNIT

MIN MAX

ISP1 1 / tc(pclk) Frequency⁽¹⁾, input pixel clock cam_pclk 148.5 MHz

ISP2 t_w(pclkL) Typical pulse duration, input pixel clock cam_pclk low 0.5P⁽²⁾ ns

ISP3 t_w(pclkH) Typical pulse duration, input pixel clock cam_pclk high 0.5P⁽²⁾ ns

t_dc(pclk) Duty cycle error, input pixel clock cam_pclk 0.5*P⁽²⁾- ns

3.247

t_J(pclk) Cycle jitter⁽³⁾, input pixel clock cam_pclk 0.06P⁽²⁾ ns

ISP4 tsu(vsV-pclkH) Setup time, input vertical synchronization cam_vs valid before input 0.75 ns pixel clock cam_pclk rising/falling edge

ISP5 th(pclkH-vsV) Hold time, input vertical synchronization cam_vs valid after input pixel 0.96 ns clock cam_pclk rising/falling edge

ISP6 tsu(hsV-pclkH) Setup time, input horizontal synchronization cam_hs valid before input 0.75 ns pixel clock cam_pclk rising/falling edge

ISP7 th(pclkH-hsV) Hold time, input horizontal synchronization cam_hs valid after input 0.96 ns pixel clock cam_pclk rising/falling edge

ISP8 tsu(dV-pclkH) Setup time, input data cam_d[n:0]⁽⁵⁾valid before input pixel clock 0.75 ns cam_pclk rising/falling edge

ISP9 th(pclkH-dV) Hold time, input data cam_d[n:0]⁽⁵⁾valid after input pixel clock 0.96 ns cam_pclk rising/falling edge

ISP10 tsu(wenV-pclkH) Setup time, input write enable cam_wen valid before input pixel clock 0.75 ns cam_pclk rising/falling edge

ISP11 th(pclkH-wenV) Hold time, input write enable cam_wen valid after input pixel clock 0.96 ns cam_pclk rising/falling edge

ISP12 tsu(fldV-pclkH) Setup time, input field identification cam_fld valid before input pixel 0.75 ns clock cam_pclk rising/falling edge

ISP13 th(pclkH-fldV) Hold time, input field identification cam_fld valid after input pixel clock 0.96 ns cam_pclk rising/falling edge

(1) Related with the input maximum frequency supported by the ISP module in 8-bit mode with 8 to 16 data bits conversion bridge enabled.

(2) P = cam_pclk period in ns

(3) Maximum cycle jitter supported by cam_pclk input clock

(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.

(5) n = 11 (Data bus size is limited to 8 bits. So the bits configuration is either cam_d[7:0] or cam_d[11:4]). Lines not connected must be tied low.

(6) SeeSection 4.3.4, Processor Clocks.

D(n-2) cam_vs

cam_hs

cam_d[N:0]

cam_wen

cam_fld

D(0) D(n-2) D(n-1) D(0) D(n-1)

ISP4 ISP5

ISP6 ISP7

ISP9 ISP8

ISP10 ISP11

SWPS038-048

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are software configurable. Optionally, the cam_wen signal can be used as an external memory write-enable signal. For further details, see the AM/DM37x Multimedia Device Technical Reference Manual (literature numberSPRUGN4).

(2) N = 11 (Data bus size is limited to 8 bits. So the bits configuration is either cam_d[7:0] or cam_d[11:4]). When the number of data lines is less than cam_d[N:0], data lines can be connected to the upper or lower lines of cam_d[N:0]. Lines not connected must be tied low. For more information about video port mapping, see the AM/DM37x Multimedia Device Technical Reference Manual (literature numberSPRUGN4).

Figure 6-23. CPI—Video and Graphics Digitizer—1.8-V Progressive Mode

cam_pclk

cam_vs

cam_hs

cam_d[N:0]

cam_wen

cam_fld

D(n–1) D(0) D(n–1) D(0) D(n–1)

EVEN ODD

ISP4 ISP5

ISP6 ISP7

ISP9 ISP8

ISP10 ISP11

ISP12 ISP13

SWPS038-049

D(0) D(0) D(n–1)

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are software configurable. Optionally, the cam_wen signal can be used as an external memory write-enable signal. For further details, see the AM/DM37x Multimedia Device Technical Reference Manual (literature numberSPRUGN4).

(2) N = 11 (Data bus size is limited to 8 bits. So the bits configuration is either cam_d[7:0] or cam_d[11:4]). When the number of data lines is less than cam_d[N:0], data lines can be connected to the upper or lower lines of cam_d[N:0]. Lines not connected must be tied low. For more information about video port mapping, see the AM/DM37x Multimedia Device Technical Reference Manual (literature numberSPRUGN4).

Figure 6-24. CPI—Video and Graphics Digitizer—1.8-V Interlaced Mode 6.5.1.2.2 CPI—12-Bit SYNC Normal Progressive Mode

Table 6-26 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 6-25).

Table 6-25. CPI Timing Conditions—12-Bit SYNC Normal Progressive Mode

⁽¹⁾

TIMING CONDITION PARAMETER VALUE UNIT

Input Conditions

t_R Input signal rise time 2.7 ns

tF Input signal fall time 2.7 ns

Output Condition

C_LOAD Output load capacitance 8.6 pF

(1) The load setting of the IO buffer: LB0 = 1.

MIN MAX MIN MAX

ISP17 1 / t_c(pclk) Frequency⁽¹⁾, input pixel clock cam_pclk 75 45 MHz

ISP18 tw(pclkH) Typical pulse duration, input pixel clock cam_pclk high 0.5P⁽²⁾ 0.5P⁽²⁾ ns ISP18 tw(pclkL) Typical pulse duration, input pixel clock cam_pclk low 0.5P⁽²⁾ 0.5P⁽²⁾ ns

t_dc(pclk) Duty cycle error, input pixel clock cam_pclk 0.5P⁽²⁾- 0.5P⁽²⁾- ns

3.465 6.93

tJ(pclk) Cycle jitter⁽³⁾, input pixel clock cam_pclk 0.0649*P 0.0649*P ns

(2) (2)

ISP19 tsu(dV-pclkH) Setup time, input data cam_d[11:0] valid before input 1.82 3.25 ns pixel clock cam_pclk rising edge

ISP20 th(pclkH-dV) Hold time, input data cam_d[11:0] valid after input 1.82 3.25 ns pixel clock cam_pclk rising edge

ISP21 tsu(dV-vsH) Setup time, input vertical synchronization cam_vs valid 1.82 3.25 ns before input pixel clock cam_pclk rising edge

ISP22 th(pclkH-vsV) Hold time, input vertical synchronization cam_vs valid 1.82 3.25 ns after input pixel clock cam_pclk rising edge

ISP23 t_su(dV-hsH) Setup time, input horizontal synchronization cam_hs 1.82 3.25 ns

valid before input pixel clock cam_pclk rising edge

ISP24 th(pclkH-hsV) Hold time, input horizontal synchronization cam_hs 1.82 3.25 ns valid after input pixel clock cam_pclk rising edge

ISP25 tsu(dV-hsH) Setup time, input write enable cam_wen valid before 1.82 3.25 ns

input pixel clock cam_pclk rising edge

ISP26 th(pclkH-hsV) Hold time, input write enable cam_wen valid after input 1.82 3.25 ns pixel clock cam_pclk rising edge

(1) Related with the input maximum frequency supported by the ISP module.

(2) P = cam_pclk period in ns

(3) Maximum cycle jitter supported by cam_pclk input clock.

(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.

(5) SeeSection 4.3.4, Processor Clocks.

cam_xclki

cam_pclk

cam_vs

cam_hs

cam_d[11:0]

cam_wen

cam_fld

D(0) D(n–3) D(n–2) D(n–1) D(0) D(1)

ISP17 ISP18

ISP19 ISP20

ISP21 ISP22

ISP24 ISP23

ISP25 ISP26

ISP18

SWPS038-050

D(n–1)

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the signal length can be set.

(2) The parallel camera in SYNC mode supports progressive image sensor modules and 8-, 10-, 11-, or 12-bit data.

(3) When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be grounded.

(4) However, it is possible to shift the data to 0, 2, or 4 data internal lanes.

(5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit mode and cam_d[11:0] in 12-bit mode.

(6) Optionally, the data write to memory can be qualified by the external cam_wen signal.

(7) The cam_wen signal can be used as an external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted.

(8) In cam_xclki, i can be equal to a or b. SeeTable 6-22for ISP15 and ISP16 parameters.

Figure 6-25. CPI—12-Bit SYNC Normal Progressive Mode 6.5.1.2.3 CPI—8-Bit SYNC Packed Progressive Mode

Table 6-28 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 6-26).

Table 6-27. CPI Timing Conditions—8-Bit SYNC Packed Progressive Mode

⁽¹⁾

TIMING CONDITION PARAMETER VALUE UNIT

Input Conditions

tR Input signal rise time 2.5 ns

t_F Input signal fall time 2.5 ns

Output Condition

C_LOAD Output load capacitance 8.6 pF

NO. PARAMETER OPP100 OPP50 UNIT

MIN MAX MIN MAX

ISP3 1 / t_c(pclk) Frequency⁽¹⁾, input pixel clock cam_pclk 130 65 MHz

ISP4 tw(pclkH) Typical pulse duration, input pixel clock 0.5*P⁽²⁾ 0.5*P⁽²⁾ ns

cam_pclk high

ISP4 t_w(pclkL) Typical pulse duration, input pixel clock 0.5*P⁽²⁾ 0.5*P⁽²⁾ ns

cam_pclk low

t_dc(pclk) Duty cycle error, input pixel clock cam_pclk 0.5*P⁽²⁾- 0.5*P⁽²⁾- ns

3.465 6.93

tJ(pclk) Cycle jitter⁽³⁾, input pixel clock cam_pclk 0.0649*P⁽²⁾ 0.0649*P⁽²⁾ ns

ISP5 tsu(dV-pclkH) Setup time, input data cam_d[7:0] valid before 1.08 2.27 ns

input pixel clock cam_pclk rising edge

ISP6 th(pclkH-dV) Hold time, input data cam_d[7:0] valid after input 1.08 2.27 ns

pixel clock cam_pclk rising edge

ISP7 t_su(dV-vsH) Setup time, input vertical synchronization 1.08 2.27 ns

cam_vs valid before input pixel clock cam_pclk rising edge

ISP8 th(pclkH-vsV) Hold time, input vertical synchronization cam_vs 1.08 2.27 ns

valid after input pixel clock cam_pclk rising edge

ISP9 t_su(dV-hsH) Setup time, input horizontal synchronization 1.08 2.27 ns

cam_hs valid before input pixel clock cam_pclk rising edge

ISP10 th(pclkH-hsV) Hold time, input horizontal synchronization 1.08 2.27 ns

cam_hs valid after input pixel clock cam_pclk rising edge

ISP11 tsu(dV-hsH) Setup time, input write enable cam_wen valid 1.08 2.27 ns

before input pixel clock cam_pclk rising edge

ISP12 th(pclkH-hsV) Hold time, input write enable cam_wen valid 1.08 2.27 ns

after input pixel clock cam_pclk rising edge (1) Related with the input maximum frequency supported by the ISP module.

(2) P = cam_pclk period in ns

(3) Maximum cycle jitter supported by cam_pclk input clock.

(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.

(5) SeeSection 4.3.4, Processor Clocks.

cam_xclki

cam_pclk

cam_vs

cam_hs

cam_d[7:0]

cam_wen cam_fld

D(0) D(n-3) D(n-2) D(n-1) D(0) D(1) D(n-1)

ISP3 ISP4

ISP5 ISP6

ISP7 ISP8

ISP10 ISP4

ISP9

ISP11 ISP12

SWPS038-051

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.

(2) The image sensor is connected to the lower data lines and the unused lines are grounded. However, it is possible to shift the data to 0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode.

(3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. The polarity of cam_fld is programmable.

(4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to transfer an YCbCr data stream or compressed stream to memory at very high speed.

(5) In cam_xclki, i can be equal to a or b. SeeTable 6-22for ISP15 and ISP16 parameters.

Figure 6-26. CPI—8-Bit SYNC Packed Progressive Mode 6.5.1.2.4 CPI—12-Bit SYNC Normal Interlaced Mode

Table 6-30 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 6-27).

Table 6-29. CPI Timing Conditions—12-Bit SYNC Normal Interlaced Mode

TIMING CONDITION PARAMETER VALUE UNIT

Input Conditions

t_R Input signal rise time 2.7 ns

t_F Input signal fall time 2.7 ns

Output Condition

CLOAD Output load capacitance⁽¹⁾ 8.6 pF

(1) The load setting of the IO buffer: LB0 = 1.

MIN MAX MIN MAX

ISP17 1 / t_c(pclk) Frequency⁽¹⁾, input pixel clock cam_pclk 75 45 MHz

ISP18 tw(pclkH) Typical pulse duration, input pixel clock cam_pclk high 0.5P⁽²⁾ 0.5P⁽²⁾ ns ISP18 tw(pclkL) Typical pulse duration, input pixel clock cam_pclk low 0.5P⁽²⁾ 0.5P⁽²⁾ ns

t_dc(pclk) Duty cycle error, input pixel clock cam_pclk 0.5*P⁽²⁾- 0.5*P⁽²⁾- ns

3.465 6.93

tJ(pclk) Cycle jitter⁽³⁾, input pixel clock cam_pclk 0.0649*P 0.0649*P ns

(2) (2)

ISP19 tsu(dV-pclkH) Setup time, input data cam_d[11:0] valid before input 1.82 3.25 ns pixel clock cam_pclk rising edge

ISP20 th(pclkH-dV) Hold time, input data cam_d[11:0] valid after input 1.82 3.25 ns pixel clock cam_pclk rising edge

ISP21 tsu(dV-vsH) Setup time, input vertical synchronization cam_vs valid 1.82 3.25 ns before input pixel clock cam_pclk rising edge

ISP22 th(pclkH-vsV) Hold time, input vertical synchronization cam_vs valid 1.82 3.25 ns after input pixel clock cam_pclk rising edge

ISP23 t_su(dV-hsH) Setup time, input horizontal synchronization cam_hs 1.82 3.25 ns

valid before input pixel clock cam_pclk rising edge

ISP24 th(pclkH-hsV) Hold time, input horizontal synchronization cam_hs 1.82 3.25 ns valid after input pixel clock cam_pclk rising edge

ISP25 tsu(dV-hsH) Setup time, input write enable cam_wen valid before 1.82 3.25 ns

input pixel clock cam_pclk rising edge

ISP26 th(pclkH-hsV) Hold time, input write enable cam_wen valid after input 1.82 3.25 ns pixel clock cam_pclk rising edge

ISP27 tsu(dV-fldH) Setup time, input field identification cam_fld valid 1.82 3.25 ns before input pixel clock cam_pclk rising edge

ISP28 th(pclkH-fldV) Hold time, input field identification cam_fld valid after 1.82 3.25 ns input pixel clock cam_pclk rising edge

(1) Related with the input maximum frequency supported by the ISP module.

(2) P = cam_pclk period in ns

(3) Maximum cycle jitter supported by cam_pclk input clock.

(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.

(5) SeeSection 4.3.4, Processor Clocks.

cam_xclki

cam_pclk

cam_vs

cam_hs

cam_d[11:0]

cam_wen

cam_fld

FRAME(0)

L(0) L(0)

D(0) D(n-3) D(n-2) D(n-1) D(0) D(1) D(2) D(n-1)

PAIR IMPAIR

ISP17

ISP18

ISP27 ISP19

ISP21 ISP22

ISP23 ISP20

ISP28

ISP25 ISP26

SWPS038-052

FRAME(0)

L(n-1) ISP18

ISP24

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the signal length can be set.

(2) The parallel camera in SYNC mode supports interlaced image sensor modules and 8-, 10-, 11-, or 12-bit data.

(3) When the image sensor has fewer than 12 data lines, it is connected to the lower data lines and the unused lines are grounded.

(4) It is possible to shift the data to 0, 2, or 4 data internal lanes.

(5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit mode and cam_d[11:0] in 12-bit mode.

(6) Optionally, the data write to memory can be qualified by the external cam_wen signal.

(7) The cam_wen signal can be used as an external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted.

(8) In cam_xclki, i can be equal to a or b. SeeTable 6-22for ISP15 and ISP16 parameters.

Figure 6-27. CPI—12-bit SYNC Normal Interlaced ModeSection 5.3

W dokumencie DM3725 (Stron 191-200)