Figure 22-1. RECEIVE SIDE TIMING
Figure 22-2. RECEIVE SIDE BOUNDARY TIMING (With Elastic Store Disabled)
1. There is a 6 RCLK delay from RPOS, RNEG to RSER 2. RCHBLK is programmed to block channel 2
3. RLINK is programmed to output the Sa4 bit 4. Shown is a non-align frame boundary
5. RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel 1 Sa4 Sa5 Sa6 Sa7 Sa8 LSB
Sa5 Sa6 Sa7 Sa8
D
CHANNEL 2 RSIG
CHANNEL 32 CHANNEL 1
Sa5
Sa5 Sa6 Sa7 Sa8
RPOS, RNEG 1 LSB 2. RSYNC in the multiframe mode (RCR1.6 = 1) 3. RLCLK is programmed to output just the Sa4 bit
4. RLINK will always output all five Sa bits as well as the rest of the receive data stream 5. This diagram assumes the CAS MF begins with the FAS word
4
Figure 22-3. RECEIVE SIDE 1.544MHz BOUNDARY TIMING (With Elastic Store Enabled)
Figure 22-4. RECEIVE SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled)
RSER LSB MSB LSB F MSB
RCHCLK RSYNC / RMSYNC
RCHBLK RSYSCLK
RSYNC 1
2
3
CHANNEL 23/31 CHANNEL 24/32 CHANNEL 1/2
4
Notes:
1. Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to one)
2. RSYNC is in the output mode (RCR1.5 = 0) 3. RSYNC is in the input mode (RCR1.5 = 1) 4. RCHBLK is programmed to block channel 24
RSER LSB MSB LSB
CHANNEL 1
RCHCLK RSYNC / RMSYNC
RCHBLK RSYSCLK
RSYNC
CHANNEL 31 CHANNEL 32
1
2
3
MSB
Notes:
1. RSYNC is in the output mode (RCR1.5 = 0) 2. RSYNC is in the input mode (RCR1.5 = 1) 3. RCHBLK is programmed to block channel 1
4. RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel 1
RSIG D
CHANNEL 1
CHANNEL 31 CHANNEL 32
Note 4
A B C A B C D
Figure 22-5. RECEIVE SIDE, INTERLEAVED BUS OPERATION BYTE MODE TIMING
RSER LSB
SYSCLK
RSYNC
FRAMER 3, CHANNEL 32
MSB LSB
FRAMER 0, CHANNEL 1
RSIG B C/A D/B A B C/D D/B
FRAMER 3, CHANNEL 32 A
FRAMER 0, CHANNEL 1
MSB LSB
FRAMER 1, CHANNEL 1
C/D D/B A B
FRAMER 1, CHANNEL 1
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. RSYNC is in the input mode (RCR1.5 = 1).
3 RSER RSYNC
RSIG
FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2
RSER
RSIG FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2
1
1
2
2
BIT DETAIL
Figure 22-6. RECEIVE SIDE, INTERLEAVED BUS OPERATION FRAME MODE TIMING
Figure 22-7. TRANSMIT SIDE TIMING
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2. TSYNC in the multiframe mode (TCR1.1 = 1) 3. TLINK is programmed to source just the Sa4 bit
4. This diagram assumes both the CAS MF and the CRC4 begin with the align frame
RSER LSB
SYSCLK
RSYNC
FRAMER 3, CHANNEL 32
MSB LSB
FRAMER 0, CHANNEL 1
RSIG B C/A D/B A B C/D D/B
FRAMER 3, CHANNEL 32
A
FRAMER 0, CHANNEL 1
MSB LSB
FRAMER 0, CHANNEL 2
D/B C/D A B
FRAMER 0, CHANNEL 2
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. RSYNC is in the input mode (RCR1.5 = 1).
3
RSER RSYNC
RSIG
FR1 CH1-32 FR0 CH1-32 FR1 CH1-32
RSER
RSIG
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
FR0 CH1-32 FR1 CH1-32
FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32
1
1
2
2
BIT DETAIL
Figure 22-8. TRANSMIT SIDE BOUNDARY TIMING (With Elastic Store Disabled)
Figure 22-9. TRANSMIT SIDE 1.544MHz BOUNDARY TIMING (With Elastic Store Enabled)
1. There is a 5 TCLK delay from TSER to TPOS and TNEG 2. TSYNC is in the input mode (TCR1.0 = 0)
3. TSYNC is in the output mode (TCR1.0 = 1) 4. TCHBLK is programmed to block channel 2 5. TLINK is programmed to source the Sa4 bits
6. The signaling data at TSIG during channel 1 is normally overwritten in the transmit formatter with the CAS multiframe alignment nibble (0000)
7. Shown is a non-align frame boundary
TPOS, TNEG Si 1
CHANNEL 23 CHANNEL 24
Notes:
1. TCHBLK is programmed to block channel 23 2. The F-bit position is ignored by the DS2154 1
MSB F-Bit
Figure 22-10. TRANSMIT SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled)
Figure 22-11. G.802 TIMING
TSER LSB MSB LSB
CHANNEL 1
TCHCLK
TCHBLK TSYSCLK
TSSYNC
CHANNEL 31 CHANNEL 32
Notes:
1. TCHBLK is programmed to block channel 31
TSIG D D
CHANNEL 1
CHANNEL 31 CHANNEL 32
B C C A
A B
1
MSB
A
LSB MSB
Timeslot 25 Timeslot 26 1
1
0 2 3 4 5 6 7 8 910 31
TIMESLOT # 30 111213141516171819202122232425262728293031 0 1 2 3 4
RCHCLK/TCHCLK
RCHBLK/TCHBLK
RSER/TSER
RCHCLK/TCHCLK
RCHBLK/TCHBLK RCLK / RSYSCLK TCLK / TSYSCLK RSYNC/TSYNC
Notes:
1. RCHBLK or TCHBLK is programmed to pulse high during timeslots 1 to 15, 17 to 25, and during bit 1 of timeslot 26
detail
Figure 22-12. TRANSMIT SIDE, INTERLEAVED BUS OPERATION BYTE MODE TIMING
TSER LSB
SYSCLK
TSSYNC
FRAMER 3, CHANNEL 32
MSB LSB
FRAMER 0, CHANNEL 1
TSIG B C/A D/B A B C/D D/B
FRAMER 3, CHANNEL 32
A
FRAMER 0, CHANNEL 1
MSB LSB
FRAMER 1, CHANNEL 1
C/D D/B A B
FRAMER 1, CHANNEL 1
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
TSER TSSYNC
TSIG
TSER
TSIG FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 1
1
2
2
BIT DETAIL
FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2
FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2
Figure 22-13. TRANSMIT SIDE INTERLEAVED BUS OPERATION FRAME MODE TIMING
TSER LSB
SYSCLK
TSSYNC
FRAMER 3, CHANNEL 32
MSB LSB
FRAMER 0, CHANNEL 1
TSIG B C/A D/B A B C/D D/B
FRAMER 3, CHANNEL 32
A
FRAMER 0, CHANNEL 1
MSB LSB
FRAMER 0, CHANNEL 2
D/B C/D A B
FRAMER 0, CHANNEL 2
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
TSER TSSYNC
TSIG
FR1 CH1-32 FR0 CH1-32 FR1 CH1-32
TSER
TSIG
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32
FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32
1
1
2
2
BIT DETAIL
Figure 22-14. DS21Q44 FRAMER SYNCHRONIZATION FLOWCHART
(if enabled via CCR1.3)CASSA = 1 CRC4 Multiframe Search
(if enabled via CCR1.0) CRC4SA = 1 Resync if
RCR1.0 = 0
Check for FAS Framing Error (depends on RCR1.2)
Figure 22-15. DS21Q44 TRANSMIT DATA FLOW
Idle Code / Channel Insertion Control via
1. TCLK should be tied to RCLK and TSYNC should be tied to RFSYNC for data to be properly sourced from RSER.
2. Auto Remote Alarm if enabled will only overwrite bit 3 of timeslot 0 in the Not Align Frames if the alarm needs to be sent.