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VIDEO INTERFACES (TV)

W dokumencie AM3871 (Stron 136-142)

3 Device Pins

VIDEO INTERFACES (TV)

Composite/S-Video (Luminance) Amplifier Output.

In Normal mode (internal amplifier used), this pin drives the 75-ΩTV load. An external resistor (Rout) should be connected between this pin and the TV_VFB0 pin and be placed as close to the pins as possible.

– The nominal value of Rout is 2700Ω.

TV_OUT0 AH24 O

VDDA_VDAC_1P8

In TVOUT Bypass mode (internal amplifier not used), this pin is not used.

When this pin is not used or the TV output is powered-down, this pin should be left unconnected.

S-Video (Chrominance) Amplifier Output.

In Normal mode (internal amplifier used), this pin drives the 75-ΩTV load.

An external resistor (Rout) should be connected between this pin and the TV_VFB1 pin and be placed as close to the pins as possible. The TV_OUT1 AH22 O VDDA_VDAC_1P8– nominal value of Rout is 2700Ω.

In TVOUT Bypass mode (internal amplifier not used), this pin is not used.

When this pin is not used or the TV output is powered-down, this pin should be left unconnected.

Composite/S-Video (Luminance) Feedback.

In Normal mode (internal amplifier used), this pin acts as the buffer feedback node.

An external resistor (Rout) should be connected between this pin and the TV_OUT0 pin.

TV_VFB0 AG23 A O VDDA_VDAC_1P8– In TVOUT Bypass mode (internal amplifier not used), this pin acts as the direct Video DAC output and should be connected to ground through a load resistor (Rload) and to an external video amplifier. The nominal value of Rload is 1500Ω.

When this pin is not used or the TV output is powered-down, this pin should be left unconnected.

S-Video (Chrominance) Feedback.

In Normal mode (internal amplifier used), this pin acts as the buffer feedback node.

An external resistor (Rout) should be connected between this pin and the TV_OUT1 pin.

TV_VFB1 AG22 A O VDDA_VDAC_1P8– In TVOUT Bypass mode (internal amplifier not used), it acts as the direct Video DAC output and should be connected to ground through a load resistor (Rload) and to an external video amplifier. The nominal value of Rload is 1500Ω.

When this pin is not used or the TV output is powered-down, this pin should be left unconnected.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-Table 3-47. Video Outupt (Analog, TV) Terminal Functions (continued)

SIGNAL

TYPE(1) OTHER(2) (3) DESCRIPTION

NAME NO.

TV Input Reference Current Setting.

An external resistor (Rset) should be connected between this pin and VSSA_VDAC to set the reference current of the video DAC. The value of the resistor depends on the mode of operation.

In Normal mode (internal amplifier used), the nominal value for Rset

TV_RSET AH23 A VDDA_VDAC_1P8– is 4700Ω.

In TVOUT Bypass mode (internal amplifier not used), the nominal value for Rset is 10000Ω.

When the TV output is not used, this pin should be connected to ground (VSS).

SIGNAL

TYPE(1) OTHER DESCRIPTION

NAME NO.

RSV1 AD8 O Reserved. (Leave unconnected, do not connect to power or ground.) RSV2 U8 O Reserved. (Leave unconnected, do not connect to power or ground.) RSV3 V8 O Reserved. (Leave unconnected, do not connect to power or ground.)

RSV4 Y14

S Reserved. (Leave unconnected, do not connect to power or ground.)

RSV5 AC8

RSV6 L27 I

RSV7 L28 I

RSV8 M27 I

RSV9 M28 I

RSV10 N28 I

Reserved. (Leave unconnected, do not connect to power or ground.)

RSV11 N27 I

RSV12 P28 I

RSV13 P27 I

RSV14 R27 I

RSV15 R28 I

RSV16 U1 I Reserved. (Leave unconnected, do not connect to power or ground.) RSV17 U2 I Reserved. (Leave unconnected, do not connect to power or ground.)

Reserved. For proper device operation, this pin must always be tied directly to a

1-RSV18 N10 S

µF capacitor to ground (VSS).

Reserved. For proper device operation, this pin must always be tied directly to a

1-RSV19 N11 S

µF capacitor to ground (VSS).

Reserved. For proper device operation, this pin must be tied directly to the 1.8-V

RSV20 P11 S

core supply.

Reserved. For proper device operation, this pin must always be tied directly to a

1-RSV21 P10 S µF capacitor to ground (VSS).

Reserved. For proper device operation, this pin must always be tied directly to a

1-RSV22 M11 S

µF capacitor to ground (VSS).

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State

3.2.26 Supply Voltages

Table 3-49. Supply Voltages Terminal Functions

SIGNAL

TYPE(1) OTHER DESCRIPTION

NAME NO.

VREFSSTL_DDR[0] G15 S Reference Power Supply DDR[0]

VREFSSTL_DDR[1] G14 S Reference Power Supply DDR[1]

CVDD K9, K10, S Variable Voltage Supply for the CORE_L Core Logic Voltage

K12, K18, L9, Domain

L10, L11, For actual voltage supply ranges, seeSection 6.2, Recommended

L12, L14, Operating Conditions.

L15, L17, L19, M10, M12, M13, M14, M16, M18, N9, N13, N14, N17, N19, P12, P14, P16, R15, R17, R19, T12, U11, U13, U17, U19, W11

CVDD_ARM T14, T15, S Variable Voltage Supply for the ARM_L Core Logic Voltage

T16, U15, Domain

U16, V15, For actual voltage supply ranges, seeSection 6.2, Recommended

V16 Operating Conditions.

DVDD M8, N7, P8, S 3.3 V/1.8 V Power Supply for General I/Os

T7, U21, U22, V20,Y11, Y16, AA15, AA17, AB14, AB16

DVDD_GPMC K20, L21, S 3.3 V/1.8 V Power Supply for GPMC I/Os (that is, GPMC, SD2,

M20 and so forth)

DVDD_GPMCB P20, T20 S 3.3 V/1.8 V Power Supply for GPMCB I/Os

DVDD_SD P7, P9 S 3.3 V/1.8 V Power Supply for MMC/SD/SDIO I/Os (specifically,

SD0, SD1, and pin W6)

DVDD_DDR[0] E20, E21, S 1.5 V/1.8 V Power Supply for DDR[0] I/Os

G16, H16, H17, J15, J16, J17, J18

DVDD_DDR[1] E8, E9, G13, S 1.5 V/1.8 V Power Supply for DDR[1] I/Os H12, H13,

H14, J10, J11, J13

DVDD_M R10 S 1.8 V Power Supply . For proper device operation, this pin must

always be connected to a 1.8-V Power Supply.

DVDD_C W19, W20 S 3.3 V/1.8 V Power Supply for Camera I/F I/Os

VDDA_ARMPLL_1P8 R13 S 1.8 V Analog Power Supply for PLL_ARM and PLL_SGX

VDDA_VID0PLL_1P8 AB18 S 1.8 V Analog Power Supply for PLL_VIDEO0

VDDA_VID1PLL_1P8 AA18 S 1.8 V Analog Power Supply for PLL_VIDEO1

VDDA_AUDIOPLL_1P8 R18 S 1.8 V Analog Power Supply for PLL_AUDIO

VDDA_DDRPLL_1P8 H15 S 1.8 V Analog Power Supply for PLL_DDR

VDDA_L3PLL_1P8 N18 S 1.8 V Analog Power Supply for PLL_L3, PLL_HDVPSS, and

PLL_MEDIACTL

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State

NAME NO.

VDDA_PCIE_1P8 W9, W10 S 1.8 V Analog Power Supply for PCIe.

For proper device operation, this pin must always be connected to a 1.8-V Power Supply, even if the PCIe is not being used.

VDDA_SATA_1P8 U9, U10 S 1.8 V Analog Power Supply for SATA.

For proper device operation, this pin must always be connected to a 1.8-V Power Supply, even if the SATA is not being used.

VDDA_HDMI_1P8 W18 S 1.8 V Analog Power Supply for HDMI.

For proper device operation, this pin must always be connected to a 1.8-V Power Supply, even if the HDMI is not being used.

VDDA_USB0_1P8 AA12 S 1.8 V Analog Power Supply for USB0.

For proper device operation, this pin must always be connected to a 1.8-V Power Supply, even if the USB0 is not being used.

VDDA_USB1_1P8 W13 S 1.8 V Analog Power Supply for USB1.

For proper device operation, this pin must always be connected to a 1.8-V Power Supply, even if the USB1 is not being used.

VDDA_VDAC_1P8 AB19 S 1.8 V Reference Power Supply for VDAC.

For proper device operation, this pin must always be connected to a 1.8-V Power Supply, even if the VDAC is not being used.

VDDA_USB_3P3 AA13 S 3.3 V Analog Power Supply for USB0 and USB1.

For proper device operation, this pin must always be connected to a 3.3-V Power Supply, even if USB0 and USB1 are not being used.

VDDA_1P8 L20, M7, S 1.8 V Power Supply for on-chip LDOs and I/O biasing

M22, R20, U7, V10, W15, Y13

LDOCAP_ARM W14 A ARM Cortex-A8 VBB LDO output.

This pin must always be connected via a 1-uF capacitor to VSS.

LDOCAP_ARMRAM V14 A ARM Cortex-A8 RAM LDO output.

This pin must always be connected via a 1-uF capacitor to VSS.

LDOCAP_RAM0 P18 A CORE RAM0 LDO output.

This pin must always be connected via a 1-uF capacitor to VSS.

LDOCAP_RAM1 R11 A CORE RAM1 LDO output.

This pin must always be connected via a 1-uF capacitor to VSS.

LDOCAP_RAM2 L18 A CORE RAM2 LDO output.

This pin must always be connected via a 1-uF capacitor to VSS.

LDOCAP_SGX T10 A SGX530 VBB LDO output.

This pin must always be connected via a 1-uF capacitor to VSS.

LDOCAP_SERDESCLK T11 A SERDES_CLKP/N Pins LDO output.

This pin must always be connected via a 1-uF capacitor to VSS.

3.2.27 Ground Pins (VSS)

Table 3-50. Ground Terminal Functions

SIGNAL

TYPE(1) OTHER DESCRIPTION

NAME NO.

VSS A1, A12, GND Ground (GND)

A17, A28, D9, D20, J12, J14, J19, K11, K13, K14, K15, K16, K17, K19, L8, L13, L16, L22, M9, M15, M17, M19, M21, N8, N12, N15, N16, N20, N21, N22, P13, P15, P17, P19, P21, R8, R9, R12, R14, R16, R21, R22, T8, T9, T13, T17, T18, T19, T21, T22, U12, U14, U18, U20, V7, V9, V11, V17, V19, V21, W12, W16, W17, Y1, Y2, Y10, Y12, Y15, Y17, Y18, Y19, AA14, AA16, AD21, AE1, AE2, AE9, AE20, AF23, AG1, AH1, AH28

VSSA_VDAC AA19 GND Analog GND for VDAC.

For proper device operation, this pin must always be connected to ground, even if the VDAC is not being used.

VSSA_HDMI V18 GND Analog GND for HDMI

For proper device operation, this pin must always be connected to ground, even if the HDMI is not being used.

VSSA_USB V12, V13 GND Analog GND for USB0 and USB1.

For proper device operation, this pin must always be connected to ground, even if USB0 and USB1 are not being used.

VSSA_DEVOSC AG3 GND Ground for Device Oscillator

VSSA_AUXOSC R2 GND Ground for Auxiliary Oscillator

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State

4.2 Boot Modes

The state of the device after boot is determined by sampling the input states of the BTMODE[15:0] pins when device reset (POR or RESET) is de-asserted. The sampled values are latched into the CONTROL_STATUS register, which is part of the Control Module. The BTMODE[15:11] values determine the following system boot settings:

• RSTOUT_WD_OUT Control

• GPMC CS0 Default Data Bus Width, Wait Enable, and Address/Data Multiplexing

For additional details on BTMODE[15:11] pin functions, see Table 3-1, Boot Configuration Terminal Functions.

The BTMODE[4:0] values determine the boot mode order according to Table 4-1, Boot Mode Order. The 1st boot mode listed for each BTMODE[4:0] configuration is executed as the primary boot mode. If the primary boot mode fails, the 2nd, 3rd, and 4th boot modes are executed in that order until a successful boot is completed.

The BTMODE[7:5] pins are RESERVED and should be pulled down as indicated inTable 3-1, Boot

W dokumencie AM3871 (Stron 136-142)

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