Precision Instrumentation Amplifiers and a Read-Out IC for Sensor Interfacing

(1)

(2)

(3)

I1

PRECISION INSTRUMENTATION

AMPLIFIERS AND A READ-OUT IC

(4)

(5)

Precision Instrumentation Amplifiers

and a Read-Out IC for Sensor Interfacing

Proefschrift

ter verkrijging van de graad van doctor aan de Technische UniversiteitDelft,

op gezag van deRector Magnificus prof.ir. K.C.A.M. Luyben, voorzitter van het College voor Promoties,

in het openbaar te verdedigen

op maandag 12 december 201 I om 15:00 uur

r

TU

Delft Libra

1

PrOmetheuSPlein

rr

L

2

628 ze

Delft

-door

RongWU

elektrotechnischingenie ur

MasterofScience van Fudan University,Shanghai,China geboren te Nanchang,China

(6)

Samenstellingpromotiecommissie:

Rector Magnificus, Technische Universiteit Delft,voorzitter

Prof. dr. ir. K.A. A. Makinwa, Technische Universiteit Delft, promotor Prof. dr. ir.J.H. Huijsing, Technische Universiteit Delft

Prof. dr. J. R. Long, Technische Universiteit Delft Prof. ir. A.J.M.van Tuijl, Universiteit Twente

Prof. dr. W.M. C. Sansen, Katholieke Universiteit Leuven Prof.dr.C. C. Enz, École Polytechnique Fédérale De Lausanne Or. ir.J.F.Witte, National Semiconductor. BV,Delft

Prof. dr. ir. G. C. M. Meijer,Technische Universiteit Delft (reservelid)

Printed by lpskamp,Enschede ISBN:978-94-6191-113-1

All rights reserved. No part of this publication may be reproduced or distribut edin anyfarm or by anymeans, orstored in a databaseor retrieval sy stem , without thepriorwr itten permission oftheauthor.

(7)

(8)

(9)

!

I I

I

4. A Chopper Instrumentation Amplifier with Offset Reduction Loop 83

4.1 Amplifier Requirements 84

4.2 Amplifier Archit ectur e 85

4.3 OffsetReduct ion Loop 89

4.3.1 Basic Concept. 90

4.3.2 Transfer Function Analysis 93

4.4 OtherSoureesof Chopper Ripple 97

4.4. 1 Cascode Buffer lsolation 97

4.4.2 Chopper Ripple from the Intermediat eStage 10 I 4.5 Applying ORL to General PurposeInstrumentationAmplifiersand Operational

Amplifiers 102

4.6 Circuit Implementations 103

4.6.1 The Input Stage s : 103

4.6.2 The lntermediate and Output Stages 109

4.6.3 The Cascode Buffers 110

4.6.4 Constant-G; Bias Circuit.. 112 4.6.5 Chopper Clock Design and Layout.. 114

4.7 Measurement Results 118

4.8 Benchm ark andConclusions 125

4.9 References 127

5. A Chopper Instrumentation Amp lifier wit h Gain Error Redu ction

Loop tB

5.1 Motivation 130

5.2 Dynami c Element Matchin g 131

5.3 Analog Gain Error ReductionLoop 131

5.3.1 Basic Concept.. 131

5.3.2 Qualitativeanalysis 133

5.3.3 Quantitativeanalysis 133

5.4 Digitally-AssistedGainError Reduction Loop 139

5.5 Comparisonbetween ORL and GERL I41

5.6 The Effects ofChopping,DEMand GERLon GmTransfer Functions 142

5.7 Circuit Implementations 145

5.7.1 Current-Feedback Instrumentation Amplifier with Analog Gain Error

(12)

5.7.2 Current-Feedback Instrumentation Amplifier with Digitally-Assisted

Gain Error Reduction Loop 151

5.8 Measurement Results 154

5.9 Benchmark and Conclusions 161

5.10 References 163

6. Read-Out IC 167

6.1 ADC Requirements 168

6.2 Architecture Design of the ADC. 171

6.2.1 Modulator Topology 171

6.2.2 Non-Idealities in the L\L Modulator. 177

6.3 Gain Accuracy Improvement Techniques in the Read-Out IC. 185

6.3.1 Dynamic Element Matching 186

6.3.2 Digitally-Assisted Gain Error Correction Scheme 187 6.4 Offset and IifNoise Suppression Techniques in the Read-Out 1C. 189

6.4.1 Previous Approach 189

6.4.2 Proposed Approach 192

6.5 Error Correction Techniques Summary 194

6.6 Circuit Implementations 196 6.6.1 CFIA Implementation 196 6.6.2 ADC Implementation 200 6.7 Measurement Results 205 6.8 Conclusions 215 6.9 References 216 7. Conclusions 219 7.1 Original Contributions 219 7.2 Main Findings 221

7.3 Other Applications of this Work 221

7.4 Future Work 222 7.5 References 222 Summary Samenvatting 225 231

(13)

Acknowledgements Publications About the Author

237

239

(14)

(15)

CHAPTER

₁

INTRODUCTION

1.1 Motivation

In this chapter,_{the motivation and objectives of this work arc described,}

then an overview of prior art read-out electronics _{is given. This is followed}

by a description of achallenging application: the read-out of a precision thermistor bridge intended for high resolution temperature measurements in wafer steppers. Finally, _{the highlights and organization of the thesis are}

presentcd.

A sensor can be defined as a device that forms the interface between non-c\ectrical physical domains and the c\ectrical domain. Examples of such physical domains are the thermal, magnetic, mechanical, radiant and chemical domains. _{Sensors are ubiquitous in our lives and indispensable in}

many applications, e.g. process control, weighing scales, environmental monitoring, and temperature measurement. They can be found in wafer steppers,_{weighing scales, mobile phones and automobiles, etc. For example}_,

there are more than 300 sensors in a modern car and the overall value of the market is expected to grow from $9.9 billion in 2009 to $16.1billion in 2014 [1.1].

This thesis describes the theory, _{design and realization of precision}

instrumentation amplifiers and read-out les for interfacing bridge transducers and thermocouples._{The goal of the work is to investigate}

power-efficient techniques to eliminate low frequency (LF) errors in the read-out electronics, _{so as to achieve high accuracy}_, _{low noise and low drift while}

(16)

(a)

v.:

Measurem ent junclion Vout Reference junction (b) (c)

Figurc 1.1 Examples ofbridge transdueers and thermocouples (a) Load cell (b) Thermocouple (c) Thermistor Bridge

While these sensors convert the physical signals into c1eetrical domain, their output voltage are smalI, in the millivolt-level, sueh as thermoeouples and bridge transducers (thermistor bridges,Hall sensorsand load cells).This thesisfocuseson the design ofthe interface c1ectronics for such sensors. A.Load Ce"

A load cell is a sensor that is used to convert a force into an c1ectrical

signal. It usually consists of a number of strain gauges configured in a Wheatstone bridge (Figure 1.1 (a». Through a mechanical arrangement, the

sensed force deforms the strain gauge,thus changing its c1ectrical resistance. A recent report has shown that the global load cell market is forecast to reach $1.5 billion dollarsby 2015 [1.2].

B. Thermocouple

A thermocouple eonsistsof two wires made of different metals that are joined at one end,called the measurement junction.At the other end of the conductors, a reference junction is formed (Figure 1.1 (b». If the

measurement and the reference junctions are at different temperatures, a

voltage appears across the two terminals that is a function of this temperature difference. Thermocouples are widely used in industrial manufacturing environments.

C.ThermistorBridge

A thermistor is aresistor whose value varies significantly with temperature. To measure temperature, they are usually configured in a Wheatstone bridge structure (Figure 1.1 (cj). Compared to thermocouples, thermistor bridges exhibit higher sensitivity and lower noise, thus they are

(17)

1.1 Motivation

widely used in precision temperature measurement _applications_, _{such as} temperature contral and compensation systems.

D.Hall Sensors Digital output ...::;- --

--ADC

Digital output A Read-Out Electronics Instrumentation VCM Amplifier Analog output Microprocessor

Read-out IC for bridge transducers that consists of an instrumentation amplifier and an ADC

Sensor

Read-out c1ectranics bridging the analog and digital worlds Sensor

Figure 1.3

Figure 1.2

The principle behind the Hall Effect is that a magnetic _{field induces a} voltage between two points on the sides of a current-carrying _{conductor. A} Hall sensor is thus a four terminal device which _{can be modeled as a} Wheatstone bridge. Hall sensors can be used for contactless _{current sensing}_, since they are sensitive to the induced magnetic _{field instead of the target} (current) itself. Besides current-sensing, _{they are also widely used for} position measuring, speed detection and praximity_{switching applications}

(18)

1.2 Overview of Read-Out Electronics for Sensors

The electrical information produced by the sensor is usually an analog signal and thus needs to be converted to a robust digital signal for further signal processing [1.3][1.4]. The system that convertsthe analogsignalfrom the sensor to the digital domainis calleda sensor read-out system. Figure 1.2 shows a typical strain gauge readout system. The analog outputsignalofthe strain gauge is processed by the read-out clectronics and converted into a digital signal.

Given the broad applications ofthermocouples and bridge transducers, it is important to investigate and improve the quality of their read-out clectronics and this will be the main goal of this thesis. Load cells, thermocouples, thermistor bridges and Hall sensors typically output low-frequency (LF) small signals in the millivolt-range. Therefore, they need amplifiers to boost such signals to levelscompatiblewith thc input ranges of typical Analog-to-Digital Converters (ADCs) (Figure 1.3). A single integrated chip on which both the preamp and the suceeeding ADC is implemented is called a read-out IC.

Although the differential output voltageof the sensor Vidcan be as small

as a few millivolts (Figure 1.3), the common-mode (CM) voltage VCM, depending on the application,may be much larger and may even vary by a few volts during the period of operation. Furthermore, the CM voltage of thermocouples may equal one of the supply rails, usually ground. To accommodate this variabie CM voltage, an lnstrumentationAmplifier (IA) is generally used for sensor read-out applications. To accurately process the millivolt-level signal from the sensor, the input referred error of the IA should be at the mierovolt- or nanovolt-level. To cope with CM variations of a few volts, the IA should have a common-mode rejection ratio (CMRR) greater than 12üd B. Furthermore, it should have high input impedance so as not to attenuate the sensor signalor load the sensor. This amplifier is very critical since it determines the overall performance of the read-out IC. To

sum up, the main functions ofthis amplifier are to I. Amplify the weak differential voltage(Vid)

2. Reject the sensor common-mode voltage(VCM ) (CMRR>12üdB)

3. Be capableofhandlingCM voltages near the rails 4. Provide high input impedance for bridge read-out

As the amplifier is used to detect a small differential signal, its input-referred error (due to noise and offset) must be reduced weil below the

(19)

1.2 Overview of Read-Out Electronics for Sensors minimum signal amplitude. Since most sensor applications _{operate near DC} with a bandwidth of a few Hz, lIJ noise is the dominant _{noise source.} Although bipolar technology is weil known for its low _{offset and low lIJ} noise [1.5], nowadays, CMOS is the preferred technology_{because of its low} cost and the powerful capability of digital signal processing. Howcver, amplifiers realized in CMOS technology have nonidealities _{such as offset} and Iljnoise. The worst-case offset can bc as large as IOmV,_{while the lIJ} noise corner frequency can be a few tens of kHz. This problem_{can be solved} with dynamic offset cancellation techniques. _{The first MOS chopper} operational amplifier was reported in [1.6]. Later, CM_{OS amplifiers with} microvolt offset levels have been achieved [1.7][1.8][1.9][t.lO][I.II] _and amplifiers with Iljnoise corner frequency ofa fcw Hz [1.l2][1.13] _{and even} a few tens of mHz [1.14] have been reported.

Besides offset, gain error is anothcr dominant _{souree of error.} _It _is usually detcrmined by component mismatch and has typical _{values of}_±_I% in a standard CMOS process. Furthermore, the amplifier's_{gain should have} very low temperature drift, so that it can be used _{for temperature} measurement applications (e.g. _{for the read-out of thermocouple and} thermistor bridge). Instrumentation amplifiers meeting _{such spccifications} (Iow noise, low offset and low drift) are further _{c1assified as precision} instrumentation amplifiers. The succeeding ADC converts _{the amplified} analog output to the digital domain, while maintaining _the signal-to-noise-ratio from thc precision instrumentation amplifier.

To conclude, _{achieving low thermal and lIJ noise, high accuracy}

and low drift is quite challenging in today's mainstream _{CMOS technology} whose inherent precision is limited by Iljnoise, component _{mismatch, gain} error and drift. A further challenge is to achieve good power_{efficiency since} many sensor systems are battery-powered. _{This is also essential for precision} temperature mcasuremcnt to restriet local sc1f-heatingerrors.

This thesis addrcsses these challenges in two ways. First, _{it presents the} design oftwo stand-alone precision instrumentation_{amplifiers which can be} indepcndcntly used in many practical systems to drive _{an cxternal ADC.} Second, it describes the design of a read-out _{IC that combines the} instrumentation amplifier and the ADC into one chip, _{so as to provide a} digital output.

(20)

Figure 1.4 Bridge instrumentation amplifier realized by three operational amplifiers

1.3 Instrumentation Amplifier Topologies

Instrumentation amplifiers can be built in several ways. The commonly used topologies are the classic three-opamp, switched-capacitor, capacitively-coupled, current-mode and current-feedback instrumentation amplifiers (lAs).

1.3.1 Thrce-Opamp Topology

The three-opamp IA uses voltage feedback to obtain a gain determined by resistors [1.15]. Figure 1.4 shows a fully-differential three-opamp IA in which the first stage is a fully-diffcrcntial amplifier with a gain of

(R_z,+R )+R22)/R, and the second stage is a differential amplifier.

The CMRR of the three-opamp IA is determined by the product of the

finite gain of its first stage, and the finite CMRR of its second stage. The latter is determined by the matching of the feedback resistors R)-R6, which usually leads to aCMRRof about 80dB [1.16]. Furthermore, it can not sense

the supply rails because the input CM level of the amplifier must be set within its output voltage range. This topology is also not very power-efficient, as it requires the use oftwo high-gain opamps. However,it exhibits high input impedance and good linearity over a wide input and output range. If a differential output is required, the first stage can be used alone, which is known as the "two-opamp" topology.

(21)

1.3 Instrumentation Amplifier Topologies

1.3.2 _{Switchcd-Capacitor Topology}

The switched-capacitor (SC) IA uses capacitors as the feedback elements [1.17][1.18]. A fully-differential SC IA is shown in Figure 1.5. When clock

$1 is high, the input signal is sampled on capacitor C

h while the integration

capacitor C2 is reset. When clock $ 2 is high_, _{the charge stored on C, is} transferred to C2• The closed-Ioop gain of the IA is determined by C

1/C2•

With careful layout, this gain can achieve 0.1% gain error and low drift over temperature. Furthermore, this topology accommodates a large CM input range since the input sampling capacitors block DC. However, it can not provide a continuous signal and the sampling procedure of the SC amplifier increases noise level due to noise folding. The noise associated with sampling is the well-known kT/C _{noise [1.19]. To reduce noise}_, _input

capacitorCl _{needs to be increased. However, this results in a decrease in the}

input impedance due to the switching impedance of input capacitors [1.20].

v"'" + ~_",<:,,""""-+---0+ Rb , c,

V~I--H"--1

_' ,n CH", Con Rb I 4>,

Figure 1.6 _{Capacitively-coupled instrumentation amplifier} Figure 1.5 _{Switched-capacitor instrumentation amplifier}

(22)

1.3.3 Capacitivcly-Coupled Topology

A recent development is the continuous-time capacitively-couplcd (and chopped) IA [I.l2][ 1.21]. As shown in Figure 1.6, it employs an input chopper (polarity reversing switch) to convert the input DC signaI into an AC signal, which can be transported via the capacitors. An output chopper then converts the amplified AC signal back to DC. Since capacitors block DC signaIs,this topology exhibits a rail-to-rail input CM range. Furthermore, it is very power-efficient since it has a continuous-time signal path and its power consumption is mainly dominated by Cm l • lts input impedance is

typically in the order of several M.n, determined by the impedance of the input capacitors at the chopping frequency. This can be increased to a few tens of M,Q by using an impedance boosting technique [1.21]. The disadvantage of this topology is that the switchcd-chopper capacitor causes spikes (or glitches) and more noise at the amplifier output.

Reset(<Prst) ---~---, Slow chop(<Pscl - . . . - - - + - - - : f - - - - ,

-/'T

T Fastchop (<Pfc,<Pfc_d)---<~ -+- - J

Figure 1.7 Block diagram of an improved capacitively-coupled analog-to-digital interface [1.22]

(23)

1.3 lnstrumentation Amplifier Topologies

An improved _{eapaeitively-coupled analog-to-digital interface was} reported in [1.22]. As shown in Figure 1.7, it consists of a sampler and a sigma-delta _(~L) _{ADC. The sampler employs a c1osed-Ioop} capacitively-eoupled topology consisting of a V-to-l converter, a Gm-C integrator followed by a sample-and-hold amplifier (Figure 1.8). Unlike [1.12][ 1.21] in which the input chopper precedes the input capacitors, here, the input chopper is shifted in the sensor. The sampler (Figure 1.8) directly proeesses the modulated sensor signal, _{thus its input capacitor Cs provide high input} impedance and also store the offset for coarse offset caneellation. The residual offset, lifnoise_{of the interface electronies (mainly from the ADC)} and the mismatch of the input capacitors are then eliminated by nested chopping that chops the complete read-out chain.

The presence of the sampler (Figure 1.8) means that this eircuit can not be, used as a stand-alone IA with a continuous-time output signa\. This implies that capacitively-coupled lAs are more compatible with a SC sampled ADC. With proper timing, _{sampling of the spikes at the IA output} [1.21] can be avoided and the non-continuous signaI path [1.22] is not an issue for a SC sampled ADC.

1.3.4 _{Current-Mode Topology}

Figure 1.9 shows a current-mode instrumentation amplifier [1.23][1.24][1.25][1.26]. The feedback around the input amplifiers AI and

Az _{forces the input voltage across the resistor} _RI, _{The eurrent through this} resistor is mirrored by precision current mirrors and converted into a voltage by R

_z,

_{and then buffered by the output opamp A}

3. The CMRR of this

topology depends on the matching of the current-mirrors and the DC precision of the current mirrors is essential for the overall offset, gain accuracy, _{drift and linearity. Since the matching of an impcdancc-boosted} current mirror is still insufficient for the required DC precision, thin-film resistor-degenerated current mirrors [1.26] _{is used and a CMRR larger than} 12üdB is achieved. However, _{precise thin-film resistors are not always} available in CMOS technology.

(24)

Vout

o

GND

Figure 1.9 Current-mode instrumentation amplifier

R 2l VOOI+

v

.;

Rl

v.

;

R22 Vout+ Vfbk+ Vfbk

-Figure 1.10 Current-feedback instrumentation amplifier

1.3.5 Currcnt-Fccdbac kTopology

Figure 1.10 shows a current-feedback instrumentation amplifier(CFIA).

The input transconductor Cm2and feedback transconductor Cm3 convert the

input and feedback voltages into corresponding eurrents. Their difference is then nulled by the gain of Cm l• The overall feedback ensures that the output

currents of Cm2and Cm3cancel and thus thc amplifier's gain is given by

(25)

1.4 Current-Feedback InstrumentationAmplifier

The CFIA is weil suited for bridge read-out. First, compared to the three-opamp topology, _{it achieves higher CMRR}_, _{because the input}

transconduetor Cm2 isolates the input CM level by converting the input

differential voltage to a differential current [1.27]. lts CMRR is mainly determined by the CMRR of Cm2 and can be made greater than 120dB.

Second,_{it is capable of handling input CM voltages that inc1ude either of th} e

supply rails [1.16]. Third, it is more power efficient because it can be seen as a merged version of the three-opamp topology [1.28], in which the output stages are shared.

Compared to the switched-capacitor IA,_{the CFIA avoids noise folding}_.

Furthermore, the CFIA has higher input impedance than the capacitively-coupled topology, and it does not produce output glitches. The CFIA is thus more suitable for use as a stand-alone IA.

The main disadvantage of the CFIA is its limited gain accuracy. From (1.1), _{assuming the open-loop gain of the CFIA is high enough and that}

precision external feedback resistors (RI,R21and R22) arc used, the CFIA's

c1osed-Ioop gain accuracy is mainly determined by the matching between the input and feedback transconductors (Cm2 and Cm3) . Furthermore_, _{the linear}

range of a CFIA is often limited by the input and feedback transconductors to several tens of mV. Although this limited input range is not a problem for many bridge applications, _{extending it will make the CFIA useful for other}

applications.

The first part of the thesis will focus on the design of improved CFIAs, while their major disadvantages-limited gain accuracy, limited input range and nonlinearity will be addressed.

1.4 _{Current-Feedback Instrumentation Amplifier}

The first CFIA was introduced by Analog Oevices [1.29] in 1971,and was implemented in bipolar technology. Later, the current-feedback concept was again described by Huijsing in 1981 [1.30] and by Säckinger in 1987 [1.31]. In 1984, a bipolar CFIA used in low-power biomedical applications was reported by Hamstra [1.32]. _{In 1993, Dool described another bipolar}

CFIA with a CM input range that inc1uded the negative rail [1.16].

The first CFIA implemented inCMOS technology was presented In 1987 by Steyaert for medical applications [1.33]. Although amplifiers In CMOS technology typically has larger offset and lIJ noise than these in bipolar technology, _{the existence of good MOS switches means that both}

(26)

these non-idcalitics can be mitigated by dynamic offset cancellation techniques. Later, in 2004, Chan introduced a CFIA that employs dynamic offset cancellation techniques to achieve low offset (1611 Y) and low lij"noise [1.34].

Table 1.1 Performance of Low-offset CFIAs Witte r 1.351 Pertiisr 1.361 Witte r1.371

Year 2009 2010 2008

Supplv voltage 5V 3.0to 5.5V 2.8 to 5.5V

Supply current 325/lA 1.7mA 850llA

Input 42nVNHz 27nVNHz 136 nVNHz

noise PSD

CMRR 130dB 142dB 140dB

Gain error 0.05% ±O.I% ±O. I%

(Untrimmed) (Untrimmed) (trimmed) (Relative) (Absolute) (Absolute) Offset <2.5 J.1 V <2 J.1V <5J.1 V

GBW 640kHz 800kHz IMHz

NEFr1.331 29.2 43 153

Recently, several CFIAs have been reported [1.35][1.36][1.37] which achieve offsets lcss than 511Y or even less than 211Y.Table 1.1 summaries the performance of these CFIAs. Since power efficiency is an important design criterion in this work, the noise efficiency factor (NEF) [1.33] is used to evaluate the power efficiency of these CFIAs. It relates the amplifier's noise PSD and supply current,as givcn by:

2/_'₀₁

1r .V,.4kT ·B W

(1-2)

where Vnis the input-referred noise voltage, I/ot is the supply current of the

amplifier, VI is the thermal voltage which equals kT/q , and BW is the amplifier bandwidth.

As seen from Table 1.1,although these CFIAs all achievc offsets of a few u V, they consume significant amount of power (NEF > 24). Unlike noise, the offset does not have a direct trade-off with power consumption. This means that it should be possible to achieve low offset with low power.

(27)

1.5 Read-Out ICs

Through a new technique (an offset reduction loop (ORL) [1.28]), a precision CFIA is presented in this thesis that achieves microvolt-offset with 3x _{improved power efficiency (NEF} ₌ _{8.8) compared to [1.35]. Moreover}

, its lij' noise corner is in the mHz range, which has not been achieved by previous stand-alone CMOS amplifiers.

As mentioned before, the main disadvantage of the CFIA is its limited gain accuracy, _{which is deterrnined by the mismatch of the input and} feedback transconductances. If precision feedback resistors are used, in the worst-case,_{th is mismatch can be as large as 2}_%. _{To reduce this mismatch,} resistor-degeneration was used [1.36][1.37], since with carefullayout, or by trimming,_{resistors can be made to match better than transistors. As aresuIt}

, a gain error of 0.1% _{has been achieved [1.36][ 1.37]. However, resistor} degeneration leads to a significant loss in power efficiency (NEF=43 [1.36] and 153 [1.37]). Moreover, trimming the degeneration resistors [1.37] increases production cost. This thesis presents a power-efficient CFIA that achieves high gain accuracy without trimming. By using dynamic element matching and a gain error reduction loop (GERL) [1.38]), it achieves an untrimmedgain error of 0.06%_{in a power efficient manner (NEF}

₌

_11.2).

1.5 _{Read-Out ICs}

The second part of the thesis is devoted to the design of a read-out IC. It consists of a precision instrumentation amplifier followed by an analog-to-digital converter (AOC). The IA provides high input impedance and relaxes the offset and noise requirements of the AOC.

Since the read-out IC acts as an AOC, a figure of merit (FOM) [1.39] is used to evaluate its power efficiency. This FOM relates the read-out IC's resolution and bandwidth with its the power consumption,as given by

FOM

=

Power

2.BW·2ENOB (1-3)

where BW is the bandwidth of the AOC, ENOB is the effective number of bits,defining as

where SNOR is the Signal-to-Noise-Distortion-Ratio_. _{Note that inc1uding} ENOB in the forrnula takes into account the distortion introduced by thc ADC.

(1-4)

ENDB

=

SNDR-I .76

(28)

- - - , : Loop-filter Quantizer I In 1+ 1 1

+

1 1 : D~ 1 1 L ~ Decimalion filter 1 - - - , 1 _{1 0} Digital Down 1 ut filter sampler 1 1 1 L I

Figure 1.11 Block diagram of a~:EADC

Many precision read-out ICs have been reported, which achieve more than 20bit resolution, low offset and gain drift «15ppm/°C) [1.40][1.41][1.42][1.43][1.44]. They are intended for precision instrumentation and measurement applications. To achieve such high resolution within a small bandwidth «250Hz), a delta-sigma (~:E)ADC is a good choice. This is due to the fact that the resolution of Nyquist-rate ADCs is limited by component matching, while ~:E ADCs apply over-sampling

technique which trades speed for resolution. Furthermore, with noise shaping, ~:EADCs can easily achieve a resolution higher than IS-bit [1.45].

Figure 1.11 shows the block diagram of a ~:E ADC. It consists of a single-loop~:Emodulator and a decimation filter. The~:E modulator consists of a loop filter, performing the noisc-shaping, a low resolution quantizer, which is over sampled and a digital-to-analog converter (DAC). The oversampling ratio (OSR) is defined as OSR=fs/2fi" wherefs is the sampling rate and

fb

is the signal bandwidth.The ~:E modulator shapes the frequency response of the quantization errors in such a way that the quantization error is reduced in the frequency band of interest,while itis increased outside that band. Therefore, high resolution can be obtained in a relatively small bandwidth. Since most of the quantization noise is shifted to higher frequencies,itis necessary to eliminate the high frequency noise by using a decimation filter.

For instrumentation applications, the input signal is a low-frcqucncy or DC signal, so the ~:E ADC typically operates in 'single-shot' mode, which means that it powers up, produces a single conversion result and finally powers down again to save power. This type of ~:E ADCs are called

(29)

I.S Rcad-Out ICs

I. The loop filter and the decimation filter are reset at the beginning of a conversion.

2. The modulator does not operate continuously, but runs for a limited number ofN clock cycles, producing a bitstream ofN bits.

Incremental LlL _{ADCs provide very precise conversion with accurate} gain, _{high linearity and low offset [1.46]. A first-order} _LlL _{modulator for}

instrumentation applications was already introduced by Van der Plassche in 1978 [1.47], which achieves 6-bit resolution reference to IV. In 2006,

Quiquempoix reported a 22-bit third-order incremental ADC reference to SV [1.46]. It_{achieves a 21.!V offset, 2ppm gain error and 4ppm INL with a FOM}

of 4.8pJ/conv .

However, since bridge sensors typically produce millivolt-level signais,

they need precision lAs to boost the sensor signals to the typical ADC input range of a few volts (Figure 1.3)._{The IA is the most challenging and power}

consuming part,_{since it determines the noise and accuracy performance of}

the read-out IC [1.48].

The lAs in previous precision read-out ICs generally employ switched-capacitor (SC) or two-opamp IA topologies. For instance, Analog Devices reported a rcad-out IC in 1997 [1.40] that used a SC IA, as shown in Figure 1.12. Due to the sampling in the SC amplifier, its noise level increases due to noise folding. Furthermore, an additional input buffer was necessary to provide high input impedance for bridge read-out. To satisfy the noise specification, this read-out IC results in a high power consumption of 80mW to achieve an 18-bit resolution with lOmV full scale. The ADC is realized with a second-order incremental LlL ADC. _{System-Ievel chopping is} employed to chop the entire analog signal path at a slow frequency of

fi

.

F

[1.40]. The subsequent digital decimation filter creates notches to suppress the modulated offset due to chopping. Overall, it achieves an offset drift in the level of 10nV/"C._{The FOM ofthe total read-out IC is 43000pJ}_/Conv.

In 2000, _{Cirrus Logic described a read-out IC [1.41], shown in Figure}

1.13.It_{consists of a two-opamp IA and a fourth-order incremental}_LlL_ADC. This architecture is also not particularly power efficient, since the two-opamp IA requires two high-gain amplifiers, thus resulting in a high power consumption of 40m W to achieve a 19-bit with 28mV full scale in a BW of 128Hz(FOM

=

164pJ/Conv).

(30)

Digital Output

Transducer ADC

SensorBridge l - ---l

Buffer

Figure 1.12 Block diagram ofthe Read-Out IC in [1.40]

Block diagram of Read-Out ICin[lAl]

Sensor Bridge Figure 1.13 R Two-opamp IA

UM

Digital Decimation Output filter

o

0

f--k--+-+---+--l V-I ss:

o

0

f--f---'t--j''--+----i Converterf-r-4---J Modulator

Figure 1.14 Block diagram of Hall sensor interface in[IA9]

A Hall sensor interface for compass application was reported by van de

Meer et.al in 2005 [1.49] and its block diagram is shown in Figure 1.14. It

consists of a voltagc-to-current converter (VIC), whose differential CUITent

output is digitized by a first-order sigma-delta modulator. The output of the modulator is averaged over an entire spinning-currcnt cycle by a decimation

filter. To achieve high linearity over a wide dynamic range, the VIC consists

of two opamps, each with a DC gain of over 120dB. This Hall sensor

interface achieves 120dB resolution and less than 50n V offset with a consuming 21mW.

(31)

1.5 Rcad-Out ICs

Reeently rcleased rcad-out ICs from Analog Devices [1.42], Cirrus Logic [1.43] and Texas Instruments [1.44], still use the SC or two-opamp lAs. That is _{part of the reason why these read-out IC}_s _{are not very power} efficient. The FOM of [1.42][1.43][1.44] are 135, 9000 and 172 pJ/Conv , respectivcly.

CFIAs, in contrast, _{provide superior power efficiency}_,_{since they avoid} noise folding and share output stages. Furthermore, the CF lAs exhibit high CMRR [1.16][1.35] and rail-to-rail sensing capability [1.16][1.36]. In order to show the potentialof CFIAs _{in rcad-out IC applications, th}_is _thesis presents the design of a read-out IC [1.50] that combines a CFIA and an ADC. In this work, _{various dynamic cancellation techniques are u}_s_{cd to} clirninate the I

If

noise,offset, _{gain error and drift. Moreover, digital signal} processing on the output ofthe ADC is explored to improve theCFIA's gain accuracy and gain drift. The CFIA and the ADC can then collaborate together to achieve optimum performance. Compared to the state-of-thc-art [1.42], _{the proposed rcad-out IC achieves 10}_x _{better offset (50n V),} comparable gain drift (1.2pprn/°C) _{and better power efficient (FOM}

₌

1I1 pJ/Conv).

1.6 _{Targeted Sensor Applications and Challenges}

As a test-case,_{the challenging task of dcveloping interface electronics} for a precision thermistor bridge was attempted. lt _{is intended for use in} wafer steppers where IlK-Ievel temperature resolution is required [1.28].

In wafer steppers,_{thermal expansion is an important souree of error and} s_{o control loops are used to stabilize the temperature}_,_{and consequcntly the} dimensions of critical mechanical components. The mechanical stability requirements on these components translate into allowable temperature drifts in the order of 100llK per minute. To measure such slow drifts with sufficicnt resolution,the total noise of the sensor _{read-out system should be} lcss than IIlK (Je) from 21.IoC

to 22.9°C,_{i.e. a 1.8°C range (equivalent to a} 21-bit resolution) when measured in a bandwidth ranging from 3mHz to 50mHz.

(32)

Vref=1.22V Metal Foil 11.4kn Figure 1.15 14nV/'-'Hz ..._-oVout Thermistor 11.4kn @22°C

Dual thermistor bridge

Since the goal is to prevent temperature drift, the absolute accuracy of the temperature measurement system may be much worse than its 1~K resolution. Thus absolute accuracy is established by periodic system-Ievel calibrations. To maintain accuracy during the (minute-long) intervals between calibrations, the thermistors, as weil as the interface c1ectronics used to read them out should be characterized by low LF noise, with I

IJ

noise corners in the order of only a few mHz. In addition, the read-out c1ectronics must have low offset and gain drift (a few ppm/SC) to maintain system accuracy over temperature.

Compared to other temperature sensors such as thermocouples,negative temperature coefficient (NTC) thermistors are weil suited forhigh-resolution temperature measurements because they can achieve high sensitivity, low thermal noise,low I(l noise corners (in the mHz range for high quality parts), and good long-term stability (about I mK/year) [1.51

J

.

In order to double the sensitivity, a double thermistor bridge consisting of two thermistors and two metal foil resistors is shown in Figure 1.15. In our case, the resistance of the thermistor (R, in Figure 1.15) is IIAkQ at 22°C,the same as the resistance of the metal foil resistors(RI in Figure 1.15). Therefore, the bridge output is zero at a temperature of 22°C. Due to the toleranee of its components, the bridge has a gain error of±0.5% . When biased by a band-gap reference at 1.22V, the cornmon-rnodc voltage of the bridge is 0.61V and its sensitivity is 27m VPC.Thus, over the required I.SoC range, the output range ofthe bridge is±24.3mV.

Being only at the millivolt level, the output of the thermistor bridge should be amplified before it is digitized or processed further. This requires the use of a low-noise instrumentation amplifier followed by an ADC. The

(33)

1.6 Targeted Sensor Applieations and Challenges

challenges associated with the design of the read-out electronics are discussed below.

The first challenge is the required resolution: 0.331lK(I o) in a 1.8°C range in a bandwidth ranging from 3mHz to 50mHz. Together with the sensitivity of the bridge (27mV/"C), this translates into an input-referred noise density requirement of 31 nV/...JHz for the whole system. The thermal noise level of the thermistor bridge is 14nV/...JHz, and so the amplifier's white noise density was chosen to be at roughly the same level, i.e. 16nV/...JHz. To achieve high power efficiency, the amplifier's noise should be white in the bandwidth of interest, which means that the amplifier's lIJ noise corner frequency must be below 3mHz. To justify such low noise specifications, the ampli fier must also have high CMRR (>120dB) and PSRR (>120dB).

The second challenge is the need for the amplifier to accommodate different input and output CM voltages. Since the bridge is biased at 1.22V , the input CM is at 0.61V. While the output CM is at 2.5V, since the amplifier'soutput is to be digitized by an Analog-to-Digital converter (ADC) with a 0 to 5V input range.

Thirdly,since the sensor and the read-out electronics are calibrated as a single system, the read-out clectronics should exhibit very low offset and gain drift (a few ppm/sC) to maintain system accuracy over temperature. Thus,the read-out electronics aims to achieve gain and offset drift less than

Ippm/°Cand IOnV/oC,respectively.

The final challenge involves self-heating. For the thermistor read-out application in wafer steppers, the rcad-out e1ectronics and the thermistor bridge are located in the vacuum environment of a wafer stepper where heat sinking is a significant problem. The power consumption of the interface clectronics should not be larger than that of the bridge (a few hundreds of

IlA) to restriet local self-heating errors.

To make the interface clectronics not only useful for thermistor bridge, but also applicable for other voltage-out sensors, e.g. strain gauge and thermocouple and Hall sensors, as shown in Table 1.3,the read-out IC was also designed to achieve the same gain accuracy as stain gauges: less than 0.02% [1.52]. Since Hall sensor output with zero field conditions is less than 50n V, in order to accurately process sensor output,the interface electronics must have an offset less than 50nV [1.49]. Furthermore, the read-out IC is dcsigned to have a bandwidth of 5Hz, to make it useful for some strain

(34)

gauges applications. Thus,the target cd noise specification is a noise PSD of 16nV/-JHz from 3mHz to 5Hz, which corresponds to a 20-bit resolution reference to±40mV.

In S1I11111101Y, the low noise, low drift and low power qualities of the

rcad-out electronics presented in this thesis are beyond the capability of current available interface electronics. These qualities make the demanding thermistor rcad-out application in wafer steppers possible. In addition, the read-out c1ectronics also can be used for interfacing strain gauge, thermocouples and Hall sensors.

Although this research work is targeted for sensor applications, the ncw tcchniques developed in this work also can be applied to other applications, such as general purpose operational amplifiers, general purpose CFIAs and general purpose rcad-out ICs.

Table 1.3 Typical sensor specifications and targets ofthe reed-out IC Strain Thermo- Thermistor Hall Target of Gauge couple bridge Sensor read-out

electronics

Resolution 20bit 18bit 21bit 20bit 20bit

(±IOmV) (±2mV) (±48mV) (±50mV) (±40mV)

Noise PSD 'oj

V

14nVNHz 'oj 16nVNHz

l/fnoise 'oj 'oj <3mHz 'oj ImHz

corner

BW 5Hz 'oj

v

5Hz

Gain drift

V

Ippm/°C

V

Ippm/°C

Gain error 0.02%

,

V

v

0.02%

Offset

,

V

50nV 50nV

Offset drift

,

10nVt'C 'oj 10nVt'C

Supply

,

300~A

V

<300~A

current

Note:forsensorspecifications, only the mostchallenging one is shown in each row,whilc the

(35)

1.7 Organization of the Thesis Sensorl->

~~

Stand-alone (1)

~

~ Dool Sensor

t-r-

CFIA ~

t-+

Read-OutlC (2) Motivation & challenges

Precision& low noise techniques

Precision CFIA& Gain Accuracy Improvement techniques

CFIAwith offset reduction loop

CFIAwith Gain error reduction loop

Read-<lut IC Chapler 1 (1) Chapter 2 (1 ) Chapter3 (1) Chapler4 (1) Chapter 5 (2) Chapter6 Theory Theory Implementation Implementation I

l

•

I

Figure 1.16 Organization of the thesis

1 .7

O

rganization

o

f the Thesis

This thesis has been divided into seven chapters. The organization of the thesis is ilIustrated in Figure 1.16. It is divided into two parts. The first part is indicated as (I) in Figure 1.16: the design of precision stand-alone lAs for bridge interfacing. The second part is indicated as (2) in Figure 1.16: the design of a read-out IC that combines the IA and an ADC. The outlines for each chapter are discussed as follows.

Since this thesis IS mainly about techniques for eliminating low frequency errors, Chapter 2 describes the nature of these errors and the associated dynamic offset cancellation techniques used to mitigate them. It

then shows how these techniques can be applied to operational amplifiers.

(36)

In Chapter 3, these techniques will be extended to CFIAs. Since the main disadvantage of CFIAs is their limited gain accuracy, this chapter discusses the available tcchniques to improve this, such as resistor-degeneration, dynamic element matching, etc. The advantages and disadvantages of each of these techniques are analyzed.

Chapter 4 presents the architecture design and implementation of a

CFIA. A new technique (offset reduction loop) is proposed to suppress the chopper ripple without causing noise folding. This CFIA achieves low offset, low thermal and lij'noiseand simultaneously,low power consumption. A lij' noise corner of ImHz is achieved at a noise PSD of 15nV/v'Hz with a NEF

of8.8.

Chapter 5 discusses an improved version CF IA of the first CFIA described in Chapter 4. It maintains the noise performance of the first design and alsoachieves high gain accuracy without trimming.This is obtained by dynamic element matching and another proposed new technique (gain error reduction loop). It achieves less than 31lV offset, and 0.06%untrimmed gain error in a power efficient manner (NEF= I 1.2). These results show that the CFIA achieves state-of-thc-art performance in terms of offset, lij'noise, gain aceuracy and power efficiency.

The basic architecture of the CFIA discussed in Chapter 4 is then combined with an ADC to build a read-out IC. Chapter 6 discusses the

system-Ievel design of the read-out IC together with implementation details and measurement results. The CFIA and the ADC collaborate at system-level to achieve an optimum performance. Measurement results show that the realized read-out IC achieves state-of-the-art offset and drift performance.

In Chapter 7, the main conclusions of the thesis are presented. Special sections have been included to highlight the original contributions of this thesisand some recommendations for future work are made.

1.8 References

[1.1] M. Fitzgerald, "Automotivc Sensor Demand Forecast 2008 to 2017: Global Economie Rebound Sparks Growth",Sept. 2010,[Online]. Available at:https://www.strategyanalytics.com/default.aspx?mod=ReportAbstractVie

(37)

1.8 References

[1.2] Global Load Cells Market to Reach US$1.5 Billion by 2015,

According to a New Report by Global Industry Analysts, Inc. Feb, 20 11,

[Online]. Available at:

http://www .prweb.eom/releases/load_cells/singleyoint_shear_beam/prweb8

121165.htm

[1.3] A Bakker and J. H. Huijsing , "High-Accuracy CMOS Smart

TemperatureSensors,"KluwerAcademie Publishers,Boston ,2000.

[1.4] J. H. Huijsing, F. R. Riedijk,and G. van der Horm, "Developments in integrated smart sensors," Sensors andActuators, vol. 43,no. 1-3, pp.

276-288,May 1994.

[1.5] G. Erdi, "Amplifier Techniques for Combining Low Noise, Precision ,

and High-Speed Performance," IEEE1. Solid-State Circuits ,vol. sc-16,no.

6,Dec. 1981.

[1.6] R. Poujois and J. Borcl, "A low drift fully integrated MOSFET

operational amplifier," IEEE 1. Solid-State Circuits. vol. 13, pp. 499-503 ,

Aug.1978.

[1.7] C. C. Enz, E. A. Vittoz and F. Krummenacher, "A CMOS chopper

amplifier,"IEEEJ.Solid-State Circuits, vol.sc-22, no. 3,pp. 335-342,June

1987.

[1.8]J. F. Witte,J. H. Huijsingand K. AA.Makinwa,"A chopper and

auto-zero offset-stabilized CMOS instrumentation amplifier," IEEE Symposium

on VLSICircuits, pp.210-2 11, June2009.

[1.9] M.A P.Pertijsand W. J.Kindt, " A 140dB-CMRR Current-Feedback

Instrumentation Amplifier Employing Ping-Pong Auto-Zeroing and

Chopping," IEEEISSCC,Dig. Tech.Papers,pp.324-325,Feb.2009. [1.10] S. Sakunia,F.Witte, M.Pertijsand K.A.A. Makinwa, "A Ping-Pong

-Pang Current-Feedback Instrumentation Amplifier with 0.04% Gain Error,"

IEEE Symposium on VLSI Circuits ,pp. 60-61,June 2011.

[1.11] J. F. Witte, J. H. Huijsing and K. A.A. Makinwa, "A C

urrent-Feedback Instrumentation Amplifier with 5~VOffset for Bidirectional

High-Side Currcnt-Sensing," IEEE ISSCC. Dig. Tech. Papers , pp. 74-75, Feb. 2008.

(38)

[1.I2] T. Denison et al., "A 2.21lW 94nV/.yHz Chopper-Stabilized instrumentation amplifier for EEG Detection in Chronic Implants," IEEE

ISSCC.Dig. Tech.Papers,pp. 162-163, Feb. 2007.

[1.13] R. F. Yazicioglu et al., "A 200llW Eight-Channel Acquisition ASIC for Ambulatory EEG Systems," IEEE ISSCC. Dig. Tech. Papers, pp.

164-165,Feb. 2008.

[1.14] M. Kejariwal, P. Ammisetti and A. Thomsen,"A 250+dBOpen Loop Gain Feedforward Compensated High Precision Operational Amplifier,"

ESSCIRC, Dig. Tech.Papers,pp. 187- 190, Sept. 2002.

[1.15] AD8250 Data Sheet, Analog Devices Inc.,Norwood, MA, 2007. [1.16] B. J. van den Dool and J. H. Huijsing, "Indirect current feedback instrumentation amplifier with a cornmon-modc input range that includes the negative rail,"IEEE 1. Solid-State Circuits ,vol. 28, no. 7, pp.743-749,July

1993.

[1.17] P. M. Van Peteghem, I. Verbauwhede and W. M. C Sansen, "Micropowcr high-performance SC building block for integrated Iow-level signal processing,"IEEE 1. Solid-StateCircuits, pp.837-844, Aug. 1985.

[1.18] K. Martin, L. Ozcolak, Y. S. Lee and G. C. Ternes, "A differential switchcd-capacitor amplifier," IEEE 1. Solid-State Circuits, vol. sc-22,no. I, pp. 104 -106, Feb.1987.

[1.19] C. C. Enz and G. C. Ternes, "Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization," Proc. IEEE, vol. 84, no. 11, pp.

1584-1614, ov.1996.

[1.20] N. Verma, A. Shoeb, J. Bohorquez et al., "A micro-power EEG acquisition SoC with integrated feature extraction processor for a chronic seizure detection system," IEEE 1. Solid-State Circuits, vol. 45, no. 4, pp. 804-8 I 6, Apr. 20 IO.

[1.21] Q. Fan, J.H. Huijsing and K. A.A. Makinwa, "A 1.81lW IIlV-Offset Capacitivcly-Couplcd Chopper Instrumentation Amplifier in 65nm CMOS,"

(39)

1.8 References

[1.22] C. Ezekwe et al,"A 6.7nV/--JHz Sub-mHz-l(fcorner 14b

Analog-to-Digital Interface for Rail-to-Rail Precision Voltage Sensing," IEEE ISSCC,

Dig. Tech. Papers,pp. 246-247, Feb. 2011.

[1.23] C. Toumazou, F. J. Ligey, and M. E. Anding, "Extcnding

Voltage-Mode Op Amps to Current-Voltage-Mode Performance,"lEE Proc.Circuits,Devices

and Systems, vol. 137,no. 2,pp. 116-130,Apr. 1990.

[1.24] S. J.Azhari and H. Fazlalipoor, "CMRR in Voltage-Op-Amp-Based

Currcnt-Modc Instrumentation Amplifiers (CM IA)," IEEE Trans. Instrum.

Meas., vol. 58,pp. 563-569,Mar. 2009.

[1.25] K.Koli and K.A. I. Halonen, "CMRR Enhancement Techniques for

Current-Mode Instrumentation Amplifiers," IEEE Trans. Circuits and

Sy stems I:Fundam. TheoryApp/icat. ,vol. 47,no. 5,pp. 622-632,May 2000.

[1.26] V. Schaffer, M. F. Snoeij,M.V. Ivanov and D. T.Trifonov,"A 36V Programmabie lnstrumentation Amplifier with Sub-20IlV Offset and a

CMRR in Excess of 120dB at All Gain Settings," IEEE 1. Solid-State

Circuits, vol. 44, no.7, pp.2036-2046, July 2009.

[1.27] J. H. Huijsing, "Opcrational amplifiers: theory and design," Second Edition,Springer,Netherlands, 2011.

[1.28] R. Wu, K. A.A. Makinwa and J.H. Huisjing, "A Chopper

Current-Feedback Instrumcntation Amplifier with a ImHz lifNoise Corner and an

AC-Coupled Ripple Reduction Loop," IEEE1. Solid-State Circuit,vol. 44,

no. 12,pp.3232-3243,Dec.2009.

[1.29] H. Krabbe, "A high-performance monolithic instrumentation

amplifier," IEEE ISSCC,Dig. Tech. Papers, pp. 186-187,Feb. 1971.

[1.30] J. H. Huijsing, "Cornparativc Study of Some Types of

Differential-Differential Amplifiers," European Conferenceon Electrotechnics, Eurocon,

B 6-8( I)(2),22-26,Apr. 1981.

[1.31]E.Säckinger and W.Guggenbühl, "A Versatile Building Bloek:Thc CMOS Differential Difference Amplifier," IEEE1. So/id-State Circuits,vol. SC-22, no. 2, pp. 287-294, Apr. 1987.

[1.32] G. H. Hamstra, A. Peper and C. A. Grimbergen, "Power

Low-Noise Instrumentation Amplifier for Physiological SignaIs," Medical &

(40)

[1.33] M. SJ. Steyaert, W. M.e. Sansen and Z. Chang, "A Micropower low-Noise Monolithic Instrumentation Amplifier for Medical Purpose," IEEE1.

Solid-State Circuits, vol. sc-22, no. 6, pp. 1163-1168, Dec. 1987.

[1.34] P. K. Chan, K. A. Ng and X. L.Zhang, "A CMOS Chopper-Stabilized Differential Difference Amplifier for Biomedical Integrated Circuits," The 4th IEEE International Midwest Symposium on Circuits and Systems, (MWSCAS), 1II-33-6, vol. 3, 2004.

[1.35] J. F. Witte, J.H.Huijsing and K. A.A. Makinwa, "A chopper and auto-zero offset-stabilized CMOS instrumentation amplify er," IEEE Symposium

on VLSI Circuits, pp. 210-211, June 2009.

[1.36] M. A. P.Pertijs and W. J. Kindt, "A 140dB-CMRR Current-Feedback Instrumentation Amplifier Employing Ping-Pong Auto-Zeroing and Chopping," IEEE 1. Solid-State Circuits, vol. 45, no. 10, pp. 2044-2056, Oct. 2010.

[1.37] J. F. Witte, J. H. Huijsing and K. A.A. Makinwa, "A Current-Feedback Instrumentation Amplifier with 511 V Offset for Bidirectional High-Side Current-Sensing," IEEE ISSCC. Dig. Tech. Papers, pp. 74-75, Feb. 2008.

[1.38] R. Wu, J. H. Huijsing, and K. A.A. Makinwa, "A Current-Feedback Instrumentation Amplifier with a Gain Error Reduction Loop and 0.06% Untrimmed Gain Error," IEEE ISSCC. Dig. Tech. Papers, pp. 244-245, Feb. 2011.

[1.39] B. Murmann and B.Boser, "Digitally assisted pipeline ADCs: theory and implcmentation," Kluwer Academie Publishers, Boston,2004.

[1.40] D. McCartney, Sherry, A. Sherry et al, "A Low-Noise Low-Drift Transducer ADC," IEEE 1. Solid-State Circuits, Vo1.32, No.7,pp. 959 - 967, July 1997.

[lAl] A. Thomsen et al., "A DC Measurement IC with 130nVpp Noise in

10Hz," IEEE ISSCC. Dig. Tech. Papers, pp. 334-335, Feb. 2000. [1042] AD7193 datasheet:

http://www.analog.com/en/analog-to-digital

converters/adconverters/ad7I 93/products/product.html

(41)

1.8 References

http://www.cirrus.com/en/products/pro/detail/PII08.html

[1.44] ADS 1282 datasheet:

http://focus.ti .com/docs/prod/folders/print/adsI282.html

[1.45] S. R. Norsworthy, R. Schreier, and G. C. Ternes, Eds., "Delta-Sigma

Data Converters: Theory, Design and Simu/ation," Piscataway, IEEE Press,

New York, 1997.

[1.46] V. Quiquempoix et al., "A Low-Power 22-bit Incremental ADC,"

IEEEJ.So/id-State Circuits, vol. 41, No. 7, pp. 1562-1571, July 2006.

[1.47] R. J. van der Plassche, "A sigma-delta modulator as an AID converter," IEEE Trans. Circuits and Systems, vol. 25, no. 7, pp. 510-514, July 1978.

[1.48] A. Thomsen et al., "A DC Measurement IC with 130nVpp Noise in

10Hz," IEEE ISSCC, Dig. Tech. Papers, pp. 334-335, Feb. 2000.

[1.49] 1. C. van de Meer, F.R. Riedijk, E. van Kampen, K. A.A. Makinwa

and J. H. Huijsing, "A fully integrated CMOS Hall sensor with a 3.651-lT3a offset for compass applications," IEEE ISSCC, Dig. Tech. Papers, pp. 246-247, Feb.2005.

[1.50] R. Wu, J. H. Huijsing, and K. A.A. Makinwa, "A 21-bit ±40mV Range Read-Out IC for Bridge Transducers," IEEE ISSCC, Dig. Tech.

Papers, pp. 110-111, Feb. 2011.

[1.51] G. C. Meijer, "Thcrmal sensors," Institute of Physics publishing, 1994. [1.52] C. Slattery and M.Nie, "A Reference Design for High-Performance, Low-Cost Weigh Scales", Dec. 2005, [Online]. Available at:

http:

(42)

(43)

CHAPTER

2 DY

NAMIC

OFFSET CANCELLATIO

N

TECHNIQUES FOR OPERATIONAL

AMPLIFIERS

At low frequencies, offset, lij"noise and drift are the dominant error sourees of operational amplifiers. This is especially true in CMOS technology. This chapter reviews precision techniques that can be used to achievelow Iij"noiseand low offset in operational amplifiers.

There are three types of CMOS offset cancellation techniques: trimming,chopping and auto-zeroing.Trimming is usually performed during production to e1iminate offset. Auto-zeroing is a sampling technique in which the offset is measured and then subtracted in subsequent clock phases. Chopping, on the other hand, is a continuous-tirne modulation technique in which the signal and offset are modulated to different frequencies. Due to the modulated offset and lij"noise,a chopper ripple appears at the amplifier output. Since chopping and auto-zeroing are dynamic techniques that continuously reduce offset, theyalso remove low frequency lij"noise as weil asoffset drift over temperature or time.

In auto-zcroing amplifiers, the residual offset is mainly caused by charge injection and clock feed-through. While in chopper amplifiers, the residual offset is mainly caused by demodulated clock feed-through spikes.

Severaltechniques canbe used to counteractthese non-idealities.

Later in this chapter, several dynamic-offsct-cornpcnsation techniques uscdin operationalamplifierswillbe discussed,e.g.ping-pongauto-zeroing,

offset stabilization, and specifically, chopper offset stabilization of a l ow-frequency path in a rnulti-path amplifier. To suppress chopper ripple,

numerous ripple reduction techniques can be used. It will be shown that

(44)

2 .1

Introduetion

For sensor applications, the bandwidth of interest is generally a few Hz. In this bandwidth, offset, lifnoise and drift are the dominant error sources. Thus, dynamic offset cancellation techniques are required to mitigate these errors. Before those dynamic offset cancellation techniques are discussed, it is necessary to first understand the nature and origins of these error sources.

2.2 Low Frequ

enc y

Errors

2.2.1 Off

set

In CMOS technology, the worst-case offset of a differential input pair can be as large as lOmY [2.1]. This offset is caused by manufacturing variation or uncertainty. For example, MOS devices exhibit threshold voltage (V1h) mismatch because Vthis a function ofthe doping levels in MOS channels and the gates,and these parameters vary randomly from one device to another.

On the other hand, the dimensions of MOS devices suffer from random, microscopie, variations during fabrication and hence there is mismatch between the equivalent lengths and widthsof nominally identica ltransistors. This mismatch can be reduced by using large devices. However, this increases chip area and therefore production cost.

2.2.2 l

ifnoise

I

if

noise is mainly caused by the defects in the interface between the gate oxide and the silicon substrate, so it depends on the "clcanncss" of the oxide-silicon interface and may be considerably different from one CMOS technology to another [2.2][2.3]. The typical lif noise corner frequency of CMOS technology is in the order of several kHz to tens of kHz, making the

lifnoise a dominant error souree at low frequencies.Related to the lifetime of the carriers,the lifnoise can be modeled as a function of frequency [2.2], given by:

v

2

₌

_K

n WLC

f '

ox

(2-1)

where K is a process-dependent constant in the order of 1O-25y2F, Wand L

(45)

2.2 Low Frequency Errors

per unit area,andfis the operation frequency.Generally, lifnoisein PMOS

is much lower than NMOS in most technologies [2.3].

I

In (2-\), the noise speetral density of the I

if

noise is inversely

proportional to the frequency.The inverse dependenee of (2-1) on the area of

the transistor WL suggests that to decrease I

if

noise,the device area must be increased.However,this again increases chip area.

2.2.3

Drift

I

Drift is caused by the cross-sensitivity of some error sourees to

temperature or time. Low drift is a critical requirement for precision

temperature measurement (e.g. thermistor bridges and themocouples), since the drift of the interface c1ectronics can then not be distinguished from the sensor signal itsc1f.

Drift mainly manifests itself as offset drift and gain drift. Thus it can be

reduced by suppressing the offset and gain error to a low enough level,and

furthermore by dynamically compensating for their temperature drift.

To conclude, Figure 2.1 depiets the low frequency errors in CMOS

amplifier. As can be seen in the bandwidth of a few Hz for bridge transducer

applications, the main errors are caused by lif noise, offset, and drift. To

mitigate these errors, dynamic offset cancellation techniques can be employed,which will be described in the next section.

..

-log(freq) 10kHz ""10HZ

K

/f nOiSe 1/fcorner frequency

...1

thermal noise

I

"'.

Noise Il offset,drift

PSD /

dB

• •

I

Figure 2.1 Low frequency noise spectrum for CMOS amplifier

I

!

_i

(46)

2.3 D

ynamic

Offset Cancellation Techniques

To reduce offset, three types of offset cancellatio n techniques can be

applied: trimming, auto-zeroing and chopping. Trimming involves

measuring and then reducing the offset during production. While this

approach can be used to obtain an order-of-magnitude reduction ofthe offset,

it is unable to reduce the initial mV-level offset below a few tens of I-lV,

because offset drift is not compensated for. Moreover, trimming does not

eliminate low-frequency noise, such as

l

IJ

noise. Dynamic offset

cancellation techniques, such as auto-zeroing or chopping are therefore

needed to counteract this problem.

2.

3.1 A

uto-zeroing

Auto-zeroing is a discrete-time sampling technique. It involves

sampling the offset of the amplifier in one clock phase, and then subtracting

it from the input signal in the other clock phase. There are three basic

topologies for auto-zeroing [2.4]: output offset storage (also called

open-loop offset cancellation),input offset storage (also called closed-Ioop offset cancellation) and closed-Ioop offset cancellation using an auxiliary amplifier.

Outpilt Offs etStorag e

Figure 2.2 depiets an auto-zcroed amplifierwith output offset storage.

When CK is high, the amplifier is in the auto-zeroing phase in which its

inputs are shorted together, driving its output to VOU!

=

A.Vos. During this

period, nodes X and Y are shorted together as weIl. When all the node

voltages are settled, A·Vosis stored acrossCland C2. When CK tumslow, the

amplifier enters the amplification phase. The differential input voltage

together with Vos is amplified, andstored on Cl and C2•Since Vos is already

stored on Cland C2, Vxand Vydoes not see Vos,which is fully cancelled.

(47)

2.3 Dynamic Offset Cancellation Techniques

When a switch opens, it injects some charge into the surrounding circuitry. This charge consists of gate-souree/drain channel charge and charge injected through the overlap capacitances (also known as clock fccd-through). In reality, the charge injection in the switches S3and S4will not completely cancel. The mismatch charge injection results in a residual offset,

given by

v

=

(qjnj3 _ qjnj_{4) /}

A

os.res C C

1 Z

(2-2)

where qinj3and qinj4are the charge injection caused by switchesS3and S4,A is the DC gain of the amplifier. Note that if A is large, A·Vosmay saturate the amplifier's output. For this reason,A is typically chosen to be between 10 and 100 [2.2]. An integrated amplifier with three cascaded auto-zeroed amplifiers with output voltage storage has been described in [2.4]. In [2.5], these stages were chopped, resulting in a low drift MOSFET operational amplifier.

Input OfJset Storage

The output offset storage technique limits the maximum gain of the amplifier. If a high gain is needed, storing the offset at the input storage capacitance would be a better solution. Figure 2.3shows the basic principle of input offset storage technique [2.2]. In the auto-zeroing phase when CK is high, the output and input of the amplifier are shorted together by switches SI and Sz,placing the amplifier in a unity-gain configuration.

When the node voltages are settled,the output voltage VOU!is given by

•

A

V

Oll 1

=- - .

V

os

I+A s,

Figure 2.3 Auto-zeroing with input offset storage

(48)

The circuit reproduces the amplifier's offset at nodes X and Y, storing the result on Cl and Cl .Note that for a zero differential input, the differential output is equal to Vos.Thus, the input-refcrrcd offset voltage of the overall circuit equalsVos/Aif S3and S4 match perfectly.

If S3 and S4 have any mismatch, this will cause mismatch charge

injection and,in turn,lead to a residual offset, which is given by

v

.

;::::

Vos

+

cQinj 3 _ Qinj 4) .

res A+l C C

I 2

(2-4)

where qinj3and qinj4are the charge injection caused by switchesSJand S4,

and A is the DC gain ofthe amplifier.

From (2-4),the offset Vosis suppressed by the gain of the amplifier. The charge injection and the leakage of the capacitors can be reduced by increasing the size of the capacitors, but cannot be suppressed by the gain beeause the capacitors are directly at the amplifier input.

The drawback of input offset storage and output offset storage is that they introduce capacitors in the signal path.The bottom-plate parasitic ofthe

capacitors decreases the amplifier bandwidth, thus degrading its phase

margin and stability.

C1osed-L oop OffsetCancel/a/ionwith Auxiliary Amplifier

To mitigate the stability issue, c1osed-loop offset cancellation with an auxiliary amplifier can be uscd to isolate the offset storage capacitors from the signal path, as shown in Figure 2.4.

In the auto-zeroing phase,the inputs of Gmlare shortcd. Thus,the output

voltage Voutcan be calculated as

(2-5) Thus,

(49)

2.3 Dynamic Offset Cancellation Techniques

Figure 2.4 Auxiliary amplifier placed in a feedback loop during offset cancellation

This voltage is stored on Cland C2afterS3andS4turn off. The offset voltage referred to the main input is given by

v

= Voo/,AZ::::: VOS1 + VOS 2 • os.o« G R G R G R mi m2 mI (2-7) I

I

I I I

The charge injection due to the mismatch ofS3andS4contributes to the offset of Gm2•In order to attenuate this charge injection,as seen from (2-7), Gm2is usual1y chosen to be at least 50 times smaller than Gm l .

Note that in an auto-zeroed amplifier,half of the clock period is used for auto-zeroing, so the amplified output is only available during part of the clock period. Such amplifiers cannot provide a continuous-time output,

unless a ping-pong topology is employed [2.4][2.6].

As seen from the discussion above, these three offset cancellation techniques cancel offset by periodically subtracting the offset obtained during the previous sampling moment. This assumes that the offset does not change too much during the amplification time. Since low-frequency noise and DC offset can not be distinguished from each other, these techniques also eliminate 1ij'noise and drift. However, the sampling action of the auto-zeroing techniques affects the amplifier's noise performance at frequencies below the sampling frequency [2.4].

Noise in Auto-Zeroing

As discussed above, auto-zeroing is a sampling technique.To complete settle within a half clock cycle, the noise bandwidth.fn.BW(determined by the

Precision Instrumentation Amplifiers and a Read-Out IC for Sensor Interfacing

PRECISION INSTRUMENTATION

AMPLIFIERS AND A READ-OUT IC

Precision Instrumentation Amplifiers

and a Read-Out IC for Sensor Interfacing

Proefschrift

r

TU

Delft Libra

PrOmetheuSPlein

rr

L

2

628

ze

Delft

RongWU

!

Contents

I

237

239

CHAPTER

1

INTRODUCTION

1.1

Motivation

v.:

--ADC

1.2

Overview of Read-Out Electronics for Sensors

1.3

Instrumentation Amplifier Topologies

1.3.1

Thrce-Opamp Topology

1.3.2

Switchcd-Capacitor Topology

V~I--H"--1

1.3.3

Capacitivcly-Coupled Topology

-/'T

1.3.4

Current-Mode Topology

z,

v

.;

v.

;

1.4

Current-Feedback Instrumentation Amplifier

=

1.5

Read-Out ICs

=

=

+

fb

fi

.

F

=

UM

o

0

o

0

If

=

1.6

Targeted Sensor Applications and Challenges

IJ

J

.

V

v

v

V

V

,

V

₁

_{Switchcd-Capacitor Topology}

_{Current-Mode Topology}

_z,

_{Current-Feedback Instrumentation Amplifier}

₌

_{Read-Out ICs}

₌

_{Targeted Sensor Applications and Challenges}

₌

_K