LF412-3

National

Sem iconductor

LF412A/LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier

General Description

T h e se de vice s are low cost, high speed, JF E T input o p e ra ­ tional am p lifie rs w ith ve ry low in p u t o ffs e t vo lta ge and g uar­

an tee d in p u t o ffs e t vo lta g e drift. T h e y require lo w supply cu rre nt y e t m aintain a large gain ba n dw id th p ro d u ct and fa st sle w rate. In addition, w e ll m atched high vo lta ge JF E T input de vice s pro vid e ve ry low in p u t bias and o ffse t currents.

LF412 dual is pin co m p a tib le w ith th e LM 1558, allow ing d e ­ signers to im m e dia te ly upgrade th e overall pe rfo rm an ce o f existing designs.

T hese a m p lifie rs m ay be used in a p p lica tio n s such as high speed integrators, fa s t D /A con verters, sam ple and hold circuits and m any o th e r circuits requiring low input o ffse t vo lta ge and drift, lo w in p u t bias current, high input im p e d ­ ance, high sle w rate and w id e bandw idth.

Features

Internally trim m ed o ffs e t vo lta ge 1 m V (m ax) Input o ffs e t vo lta g e d rift 10 juV /°C (m ax)

Low input bias cu rre nt 50 pA

Low in p u t noise cu rre nt 0.01 pA/VFlz

W ide gain bandw idth 3 M H z (m in)

H igh sle w rate 1 0 V /ju s (m in)

Low su p p ly cu rre nt 1.8 m A /A m p lifie r

H igh input im pedance 10 1 2a

Low to ta l h a rm onic disto rtio n A v = 1 0 , ^ 0 .0 2 % R L = 1 0 k , V o = 20 Vp-p, BW = 20 H z-20 kH z

Low 1 / f noise co rn e r 50 Hz

Fast se ttlin g tim e to 0.01 % 2 fxs

Typical Connection

Bf

Simplified Schematic

Ordering Information Connection Diagrams

L F 4 1 2 X Y Z

X in d ica te s ele ctrica l grade Y in d ica te s te m p e ra tu re range

“ M ” fo r m ilitary

“ C ” fo r co m m ercial Z in d ica te s pa ckag e type

“ H ” o r “ N ”

M etal C an P ackage

\l*

Note. Pin 4 connected to case.

TOP VIEW

1 /2 Dual O rd e r N u m b er LF412A M H ,

LF412M H , LF412A C H o r LF412C H S ee NS P ackage N u m b e r H 08B

D u al-ln-Line P ackage

v+

OUTPUTB

INVERTING INPUT B

NON-INVERTING INPUT B

TOP VIEW

TL/H/5656-1 O rd e r N um ber L F412A C J, LF412C J,

LF412A C N o r LF412C N S ee NS P ackage N u m b er J08A o r N 08E

F 4 1 2 A /L F 4 1 2

L F 4 1 2 A /L F 4 1

Absolute Maximum Ratings

If M ilita ry /A e ro s p a c e s p e c ifie d d e v ic es a re req u ired , p lease c o n ta c t th e N a tional S em ic o n d u c to r S ales O ffic e / D is trib u to rs fo r a v a ila b ility and s p e c ific atio n s .

(N o te 9)

S up p ly V oltage D iffe re n tia l Input V oltage In p ut v o lta ge R ange

(N o te 1) O u tp u t S ho rt C ircuit

D uration (N ote 2)

L F412A LF412 H P ackage N P ac k a g e

± 2 2 V ± 1 8 V P ow er D issipation (N o te 10) (N o te 3) 6 7 0 m W

± 3 8 V ± 3 0 V Tj m ax 150°C 1 15°C

0jA (Typical) 15 2 °C /W 1 1 5 °C /W

+ 19V ± 15V O p e rating T em p. R ange (N ote 4) (N o te 4)

S to rag e Tem p. -6 5 ° C < ;Ta^ 1 5 0oC-- 6 5 ° C ^ T a ^ 1 5 C o n tin u o us C ontinuous R ange

Lead T e m p.

(S oldering, 10 sec.) 260°C 260°C

ESD rating to be de term in e d.

DC Electrical Characteristics (Notes)

S ym bol P ara m e te r C o n d itio n s LF412A LF412

U nits

Min T y p M ax Min T y p M ax

v o s Input O ffs e t V olta g e Rs = 10 k ft, Ta = 25°C 0.5 1.0 1.0 3.0 m V

A Vq s/A T A ve ra g e TC o f Input O ffs e t V oltage

R s = 1 0 k f t (N ote 6)

7 10 7 20

(N o te 6) ju,V/°C

>OS Input O ffs e t C urrent V s = + 1 5 V (N o te s 5 and 7)

Tj = 25°C 25 100 25 100 pA

Tj = 70°C 2 2 nA

T j= 1 2 5 ° C 25 25 nA

>B Input B ias C urrent V s = + 1 5 V (N o te s 5 and 7)

Tj = 25°C 50 200 50 200 pA

Tj = 70°C 4 4 nA

T j= 125°C 50 50 nA

Rin Input R e sista n ce Tj = 25°C 1012 1012 a

Av o l Large Signal V olta g e Gain

V S = ± 1 5 V , V o = ± 1 0 V ,

R L = 2 k , T A = 25°C 50 200 25 200 V /m V

O ve r T e m pe ratu re 25 200 15 200 V /m V

V o O u tp u t V olta g e Sw ing V S = ± 1 5 V , R L = 1 0 k ± 1 2 ± 1 3 .5 ± 1 2 ± 1 3 .5 V

VcM Input C o m m o n -M od e V olta g e R ange

± 1 6 + 19.5 ±11 + 14.5 V

- 1 6 . 5 - 1 1 . 5 V

C M R R C om m o n -M od e R e je ctio n R atio

R s ^ 1 0 k

80 100 70 100 dB

PSRR S upply V olta g e R ejection R atio

(N o te 8)

80 100 70 100 dB

•s S upply C urrent V 0 = 0V, R|_ = oo 3.6 5.6 3.6 6.5 m A

AC Electrical Characteristics (Notes)

S ym bol P a ra m e te r C o n d itio n s LF412A LF412

U nits

Min T y p M ax Min T y p M ax

A m p lifie r to A m p lifie r C oupling

Ta= 25°C, f = 1 Hz-20 kH z

(Input R eferred) - 1 2 0 - 1 2 0 dB

SR S le w R ate V S = ± 1 5 V , T A = 25°C 10 15 8 15 V /ja s

G B W G a in-B andw idth P roduct Vs= ± 1 5 V , Ta = 25°C 3 4 2.7 4 M H z

e n E qu iva len t Input N oise V oltage

Ta= 25°C, R s = i o o n ,

f = 1 kH z 25 25 nV A /H z

•n E quivalent Input N oise

C urrent

T A = 2 5 ° C ,f= 1 kH z

0.01 0.01 p A /V fiz

3-84

Note 1: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.

Note 2: Any of the amplifier outputs can be shorted to ground indefintely, however, more than one should not be simultaneously shorted as the maximum junction temperature will be exceeded.

Note 3: For operating at elevated temperature, these devices must be derated based on a thermal resistance of 9^.

Note 4: These devices are available in both the commercial temperature range 0°C ^Ta^ 70°C and the military temperature range - 5 5 9C ^ Ta^ 125°C. The temperature range is designated by the position just before the package type in the device number. A “C" indicates the commercial temperature range and an "M"

indicates the military temperature range. The military temperature range is available in "H” package only. In all cases the maximum operating temperature is limited by internal junction temperature Tj max.

Note 5: Unless otherwise specified, the specifications apply over the full temperature range and for Vs = ± 20V for the LF412A and for Vs = ± 15V for the LF412.

Vos. >B> ar>d los are measured at Vc m^O.

Note 6: The LF412A is 100% tested to this specification. The LF412 is sample tested on a per amplifier basis to insure at least 85% of the amplifiers meet this specification.

Note 7: The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature, Tj. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pq. T j= T A + 0 jA Pd where 0jA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum.

Note 8: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice.

Vs = ± 6 V to ±15V.

Note 9: Refer to RETS412AX for LF412AMH military specifications and to RETS412X for LF412MH military specifications.

Note 10: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside guaranteed limits.

Typical Performance Characteristics

1 zUJ

cecc

=>

o

<CO

In p u t Bias C u rre n t

Vs = ±15V Ta =; 25° IC

- 1 0 - 5 0 5 10

COMMON-MODE VOLTAGE (V)

- 5 0 - 2 5 0 25 50 75 100 125 TEMPERATURE (°C)

0 5 10 15 20 25

SUPPLY VOLTAGE ( ± V )

P ositive C o m m o n -M o d e

0 5 10 15 20 25

POSITIVE SUPPLY VOLTAGE (V)

N e g a tiv e C o m m o n -M o d e

0 - 5 - 1 0 - 1 5 - 2 0 - 2 5 NEGATIVE SUPPLY

VOLTAGE (V)

0 10 20 30 40

OUTPUT SOURCE CURRENT (mA)

N e g a tiv e C u rre n t Lim it

0 10 20 30 40

OUTPUT SINK CURRENT (mA)

0 5 10 15 20 25

SUPPLY VOLTAGE ( ± V )

0.1 1 10

Rl-OUTPUT LOAD (kit)

TL/H/5656-2

F 4 1 2 A /L F 4 1 2

L F 4 1 2 A /L F 4 1

Typical Performance Characteristics

G ain B andw idth

VS = ± 1 5 V RL = 2k C|.= 1 0 I0 pF

- 5 0 - 2 5 0 25 50 75 100 125 TEMPERATURE (°C)

D is to rtio n vs F requency

10 100 1k 10k 100k

FREQUENCY (Hz)

U n d is to rte d O u tp u t V o lta g e S w ing

FREQUENCY(Hz)

160 140

“ 120 I - 100

fe z M

g <

^ « 60 o 40

20

0

C o m m o n -M o d e R ejectio n R atio

100 1k 10k 100k 1M 10M FREQUENCY(Hz)

GO «=

P o w e r S upply R ejectio n R atio

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

70

60 CO

i f ⁵⁰

=j

| ^{% 40}

t r u j

Z CD 30

id ^ 5 fe 5 > 20

UJ 10

0

O p e n L o o p V o lta g e Gain

5 10 15 20

SUPPLY VOLTAGE ( ± V )

O u tp u t Im p e d a n c e

100 1k 10k 100k 1M

FREQUENCY (Hz)

- 1 0

S le w R a te

vs = ±15V

R|_ = 2 k --- Ay = 1______ | _ 1 _ 1 ________

50 - 2 5 0 25 50 75 100 125 TEMPERATURE (°C)

O pen L oop F req u en cy R e s p o n s e

1 10 100 1k 10k 100k 1M 10M FREQUENCY(Hz)

E q u ivalen t Input N oise V o lta g e

10 100 1k 10k 100k

FREQUENCY(Hz)

In v e rte r S ettling T im e

0.1 1 10

SETTLING TIME (//S)

TL/H/5656-3

3-86

Pulse Response

TIME (0 .2 /zs /D IV )

Large Signal In v erting

TIME (2 ^ s /D IV )

Sm all Signal N o n -In v e rtin g

TIME (0 .2 /xS/DIV)

L arge Signal N o n -In v e rtin g

TIME (2 p & f DIV)

Application Hints

T h e LF412 series o f JF E T input dual op a m ps are in te rn a lly trim m e d (B I-FE T I|t m) providing ve ry lo w input o ffs e t v o lt­

ag e s and g u a ranteed input o ffs e t vo lta g e drift. T h e se JF E T s have large reverse bre a kd o w n vo lta g e s fro m g a te to so u rce and dra in e lim inating th e need fo r cla m p s a cro ss th e inputs.

T h e re fo re , large d iffe re n tia l in p u t v o lta g e s can e asily be a c­

co m m o d a te d w ith o u t a large in cre a se in input current. Th e m axim um d iffe re n tia l input vo lta ge is in d e p e n d e n t o f th e su p p ly vo lta ge s. H ow ever, n e ith e r o f th e in p u t vo lta g e s sh o u ld b e a llo w ed to exce ed th e n e gative su p p ly as th is w ill ca u se la rge cu rre nts to flo w w h ich can re su lt in a de stro yed unit.

E xceeding th e negative co m m on -m o d e lim it on e ith e r input w ill ca u se a reversal o f th e phase to th e o u tp u t and fo rce th e a m p lifie r o u tp u t to th e co rre sp o n din g high o r lo w state.

E xceeding th e negative c o m m o n -m o d e lim it on b o th inputs w ill fo rce th e a m p lifie r o u tp u t to a high state. In n e ith e r ca se does a latch o cc u r sin ce raising th e input b a ck w ith in th e co m m on -m o d e ra nge again p u ts th e input sta g e and th u s th e a m p lifie r in a norm al o p e ra tin g m ode.

E xceeding th e po sitive c o m m o n -m o d e lim it on a single in p u t w ill n o t cha n g e th e p h ase o f th e output, how ever, if bo th inputs e xceed th e lim it, th e o u tpu t o f the a m p lifie r m ay be fo rce d to a high state.

T h e am p lifie rs w ill o p e ra te w ith a co m m on -m o d e in p u t v o lt­

age equal to th e p o sitive supply; how ever, th e gain b a n d ­ w idth and sle w rate m ay be decre a se d in th is co n d itio n . W hen th e ne g ative c o m m o n -m o d e vo lta ge sw ings to w ithin 3V o f th e negative supply, an in cre a se in in p u t o ffs e t vo lta g e m ay occur.

F 4 1 2 A /L F 4 1 2

L F 4 1 2 A /L F 4 1

Application Hints

Each am p lifie r is in dividually biased by a ze n e r re fe re n ce w hich a llo w s n orm al circ u it ope ra tio n on ± 6.0V p o w e r su p ­ plies. S upply v o lta g e s less than th e se m ay re su lt in lo w e r gain ba n dw id th and sle w rate.

The a m p lifie rs w ill drive a 2 k f l load re sista n ce to ± 1 0 V o ve r th e fu ll te m p e ra tu re range. If th e a m p lifie r is fo rce d to drive he a vie r load currents, how ever, an in cre a se in in p u t o ffse t vo lta g e m ay o cc u r on th e negative vo lta g e sw ing and fin a lly reach an a ctive cu rre n t lim it on b o th p o sitive and ne g ­ ative sw ings.

P recautions sh o u ld be ta ke n to ensure th a t th e p o w e r su p ­ ply fo r th e in te g ra te d circ u it n e ver be co m es reversed in p o ­ larity o r th a t th e unit is n o t in a d ve rte n tly installed ba ckw a rd s in a so c ke t as an unlim ited cu rre n t surge th ro u g h th e re su lt­

ing fo rw a rd d io d e w ith in th e IC could cause fu sin g o f th e internal c o n d u cto rs and re su lt in a d e stroyed unit.

B ecause th e se a m p lifie rs are JF E T ra ther th a n M O S FE T input op a m p s th e y do n o t require special handling.

A s w ith m ost am plifiers, ca re sh o u ld be ta ke n w ith lead dress, co m p o n e n t p la c e m e n t and su p p ly d e co u p lin g in o r­

d e r to en su re stability. For e xam ple, re sisto rs fro m th e o u t­

p u t to an in p u t should be p la ced w ith th e b ody clo se to th e in p u t to m inim ize “ p ick-u p ” and m axim ize th e fre q u e n cy o f th e fe e d b a c k p o le by m inim izing th e ca p a cita n ce from th e input to ground.

A fe e d b a c k po le is crea te d w h e n th e fe e d b a c k around any a m p lifie r is resistive. Th e p arallel re sista n ce and ca p a ci­

ta n ce fro m th e input o f th e d e vice (usually th e inverting in­

put) to A C g round se t th e fre q u e n c y o f th e pole. In m any in sta nce s th e fre q u e n cy o f th is p o le is m uch g re a te r than th e e xp e cte d 3 dB fre q u e n cy o f th e clo se d loop gain and co n s e q u e n tly th e re is negligible e ffe c t on sta b ility m argin.

H ow ever, if th e fe e d b a c k p o le is le ss th a n a p p ro xim a te ly 6 tim e s th e e xp e cte d 3 dB fre q u e n c y a lead ca p a cito r should be pla ced fro m th e o u tp u t to th e in p u t o f th e op am p. The value o f th e added ca p a cito r sh o u ld be such th a t th e RC tim e co n s ta n t o f th is ca p a cito r and th e re sista n ce it parallels is g re a te r th a n o r equal to th e o riginal fe e d b a c k p o le tim e co n sta n t.

3-88

Typical Application

S in g le S u p p ly S a m p le a n d H o ld

Detailed Schematic

TL/H/5656-9

F 4 1 2 A /L F 4 1 2