ADS7223

(1)

SAR ADC CHA1P/CHA3

CHA1N/CHA2 CHA0P/CHA1 CHA0N/CHA0 CMA

Input Mux

CHB1P/CHB3 CHB1N/CHB2 CHB0P/CHB1 CHB0N/CHB0 CMB

Input Mux

Serial Interface

and FIFO

SAR ADC REF1

REF2

AVDD DVDD

CS CLOCK BUSY SDI RD SDOA SDOB

Control Logic

M0 M1 CONVST

AGND DGND

RGND

2.5V REF String

DAC

String DAC REF2

REF1

REFIO1

REFIO2

Dual, 1MSPS, 16-/14-/12-Bit, 4×2 or 2×2 Channel, Simultaneous Sampling Analog-to-Digital Converter

Check for Samples:ADS8363,ADS7263,ADS7223

1

FEATURES DESCRIPTION

2• Eight Pseudo- or Four Fully-Differential Inputs The ADS8363 is a dual, 16-bit, 1MSPS analog-to-digital converter (ADC) with eight pseudo-

• Simultaneous Sampling of Two Channels

or four fully-differential input channels grouped into

• Excellent AC Performance:

two pairs for simultaneous signal acquisition. The

– SNR: analog inputs are maintained differentially to the input

93dB (ADS8363) of the ADC. The input multiplexer can be used in 85dB (ADS7263) either pseudo-differential mode, supporting up to four 73dB (ADS7223) channels per ADC (4x2), or in fully-differential mode that allows to convert up to two inputs per ADC (2x2).

– THD:

The ADS7263 is a 14-bit version while the ADS7223 –98dB (ADS8363)

is a 12-bit version of the ADS8363.

–92dB (ADS7263)

–86dB (ADS7223) The ADS8363/7263/7223 offer two programmable

reference outputs, flexible supply voltage ranges, a

• Dual Programmable and Buffered 2.5V

programmable auto-sequencer, data storage of up to Reference Allows:

four conversion results per channel, and several – Two Different Input Voltage Range Settings power-down features.

– Two-Level PGA Implementation

All devices are offered in a 5x5mm QFN-32 package.

• Programmable Auto-Sequencer

• Integrated Data Storage (up to 4 per channel)

Functional Block Diagram for Oversampling Applications

• 2-Bit Counter for Safety Applications

• Fully Specified over the Extended Industrial Temperature Range

APPLICATIONS

• Motor Control: Current and Position

Measurement including Safety Applications

• Power Quality Measurement

• Three-Phase Power Control

• Programmable Logic Controllers

• Industrial Automation

• Protection Relays

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

(2)

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder atwww.ti.com.

FAMILY OVERVIEW

PRODUCT RESOLUTION NMC INL SNR THD

ADS8363 16 bits 16 or 15 bits⁽¹⁾ ±3 or ±4 LSB⁽¹⁾ 93dB (typ) –98dB (typ)

ADS7263 14 bits 14 bits ±1 LSB 85dB (typ) –92dB (typ)

ADS7223 12 bits 12 bits ±0.5 LSB 73dB (typ) –86dB (typ)

(1) See Electrical Characteristics.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

ADS8363, ADS7263, ADS7223 UNIT

Supply voltage, AVDD to AGND or DVDD to DGND –0.3 to +6 V

Supply voltage, DVDD to AVDD 1.2 × AVDD⁽²⁾ V

Analog and reference input voltage with respect to AGND AGND – 0.3 to AVDD + 0.3 V

Digital input voltage with respect to DGND DGND – 0.3 to DVDD + 0.3 V

Ground voltage difference |AGND-DGND| 0.3 V

Input current to any pin except supply pins –10 to +10 mA

Maximum virtual junction temperature, TJ +150 °C

Human body model (HBM),

±2000 V

Electrostatic JEDEC standard 22, test method A114-C.01 discharge (ESD)

Charged device model (CDM),

ratings, all pins ±500 V

JEDEC standard 22, test method C101

(1) Stresses above these ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.

(2) Exceeding the specified limit causes an increase of the DVDD leakage current and leads to malfunction of the device.

THERMAL INFORMATION

ADS8363, ADS7263, ADS7223

THERMAL METRIC⁽¹⁾ UNITS

RHB 32 PINS

qJA Junction-to-ambient thermal resistance 33.3

qJCtop Junction-to-case (top) thermal resistance 29.5

q_JB Junction-to-board thermal resistance 7.3

yJT Junction-to-top characterization parameter 0.2 °C/W

yJB Junction-to-board characterization parameter 7.4

qJCbot Junction-to-case (bottom) thermal resistance 0.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report,SPRA953.

2 Submit Documentation Feedback

(3)

ELECTRICAL CHARACTERISTICS: ADS8363

All minimum/maximum specifications at T_A= –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and t_DATA= 1MSPS, unless otherwise noted. Typical values are at T_A= +25°C, AVDD = 5V, and DVDD = 3.3V.

ADS8363

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RESOLUTION 16 Bits

DC ACCURACY

Half-clock mode –3 ±1.2 +3 LSB

INL Integral nonlinearity

Full-clock mode –4 ±1.5 +4 LSB

Half-clock mode –0.99 ±0.6 +2 LSB

DNL Differential nonlinearity

Full-clock mode –1.5 ±0.8 +3 LSB

VOS Input offset error –2 ±0.2 +2 mV

V_OSmatch ADC to ADC –1 ±0.1 +1 mV

dV_OS/dT Input offset thermal drift 1 mV/°C

Referenced to the voltage at

GERR Gain error –0.1 ±0.01 +0.1 %

REFIOx

G_ERRmatch ADC to ADC –0.1 ±0.005 +0.1 %

GERR/dT Gain error thermal drift 1 ppm/°C

REFIOx

CMRR Common-mode rejection ratio Both ADCs, dc to 100kHz 92 dB

AC ACCURACY

SINAD Signal-to-noise + distortion V_IN= 5V_PPat 10kHz 89 92 dB

SNR Signal-to-noise ratio VIN= 5VPPat 10kHz 90 93 dB

THD Total harmonic distortion VIN= 5VPPat 10kHz –98 –90 dB

SFDR Spurious-free dynamic range V_IN= 5V_PPat 10kHz 90 100 dB

ADS7263

DC ACCURACY

INL Integral nonlinearity –1 ±0.4 +1 LSB

DNL Differential nonlinearity –0.5 ±0.2 +1 LSB

VOS Input offset error –2 ±0.2 +2 mV

V_OSmatch ADC to ADC –1 ±0.1 +1 mV

dV_OS/dT Input offset thermal drift 1 mV/°C

GERR Gain error REFIOx –0.1 ±0.01 +0.1 %

G_ERRmatch ADC to ADC –0.1 ±0.005 +0.1 %

GERR/dT Gain error thermal drift 1 ppm/°C

REFIOx

AC ACCURACY

SNR Signal-to-noise ratio VIN= 5VPPat 10kHz 84 85 dB

THD Total harmonic distortion VIN= 5VPPat 10kHz –92 –88 dB

SFDR Spurious-free dynamic range V_IN= 5V_PPat 10kHz 88 92 dB

Submit Documentation Feedback 3

(4)

ADS7223

DC ACCURACY

INL Integral nonlinearity –0.5 ±0.2 +0.5 LSB

DNL Differential nonlinearity –0.5 ±0.1 +0.5 LSB

V_OS Input offset error –2 ±0.2 +2 mV

VOSmatch ADC to ADC –1 ±0.1 +1 mV

dVOS/dT Input offset thermal drift 1 mV/°C

G_ERR Gain error –0.1 ±0.01 +0.1 %

REFIOx

GERRmatch ADC to ADC –0.1 ±0.005 +0.1 %

G_ERR/dT Gain error thermal drift 1 ppm/°C

REFIOx

AC ACCURACY

SNR Signal-to-noise ratio V_IN= 5V_PPat 10kHz 72 73 dB

THD Total harmonic distortion V_IN= 5V_PPat 10kHz –86 –84 dB

SFDR Spurious-free dynamic range VIN= 5VPPat 10kHz 84 86 dB

ELECTRICAL CHARACTERISTICS: GENERAL

ADS8363, ADS7263, ADS7223

ANALOG INPUT

(CHxxP – CHxxN) or CHxx to

FSR Full-scale input range –V_REF +V_REF V

CMx

VIN Absolute input voltage CHxxx to AGND –0.1 AVDD + 0.1 V

CIN Input capacitance CHxxx to AGND 45 pF

C_ID Differential input capacitance 22.5 pF

I_IL Input leakage current –16 16 nA

PSRR Power-supply rejection ratio AVDD = 5.5V 75 dB

SAMPLING DYNAMICS

Half-clock mode 17.5 tCLK

tCONV Conversion time per ADC

Full-clock mode 35 t_CLK

Half-clock mode 2 t_CLK

t_ACQ Acquisition time

Full-clock Mode 4 t_CLK

fDATA Data rate 25 1000 kSPS

tA Aperture delay 6 ns

t_Amatch ADC to ADC 50 ps

t_AJIT Aperture jitter 50 ps

Half-clock mode 0.5 20 MHz

f_CLK Clock frequency

Full-clock mode 1 40 MHz

Half-clock mode 50 2000 ns

tCLK Clock period

Full-clock mode 25 1000 ns

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ELECTRICAL CHARACTERISTICS: GENERAL (continued)

ADS8363, ADS7263, ADS7223

INTERNAL VOLTAGE REFERENCE

Resolution Reference output DAC resolution 10 Bits

Over 20% to 100% DAC range 0.2V_REFOUT V_REFOUT V

V_REFOUT Reference output voltage REFIO1, DAC = 3FFh, 2.485 2.500 2.515 V

REFIO2, DAC = 3FFh 2.480 2.500 2.520 V

dVREFOUT/dT Reference voltage drift ±10 ppm/°C

DNLDAC DAC differential linearity error –4 ±1 4 LSB

INL_DAC DAC integral linearity error –4 ±0.5 4 LSB

V_OSDAC DAC offset error V_REFOUT= 0.5V –4 ±1 4 LSB

PSRR Power-supply rejection ratio 73 dB

IREFOUT Reference output dc current –2 +2 mA

Reference output short-circuit

I_REFSC 50 mA

current⁽¹⁾

t_REFON Reference output settling time C_REF= 22mF 8 ms

VOLTAGE REFERENCE INPUT

VREF Reference input voltage range 0.5 2.5 2.525 V

I_REF Reference input current 50 mA

External ceramic reference

CREF 22 mF

capacitance DIGITAL INPUTS⁽²⁾

I_IN Input current V_IN= DVDD to DGND –50 +50 nA

C_IN Input capacitance 5 pF

Logic family CMOS with Schmitt-Trigger

VIH High-level input voltage DVDD = 4.5V to 5.5V 0.7DVDD DVDD + 0.3 V

V_IL Low-level input voltage DVDD = 4.5V to 5.5V –0.3 0.3DVDD V

Logic family LVCMOS

V_IH High-level input voltage DVDD = 2.3V to 3.6V 2 DVDD + 0.3 V

VIL Low-level input voltage DVDD = 2.3V to 3.6V –0.3 0.8 V

DIGITAL OUTPUTS⁽²⁾V

C_OUT Output capacitance 5 pF

C_LOAD Load capacitance 30 pF

Logic family CMOS

VOH High-level output voltage DVDD = 4.5V, IOH= –100µA 4.44 V

VOL Low-level output voltage DVDD = 4.5V, IOH= +100µA 0.5 V

Logic family LVCMOS

V_OH High-level output voltage DVDD = 2.3V, I_OH= –100µA DVDD – 0.2 V

V_OL Low-level output voltage DVDD = 2.3V, I_OH= +100µA 0.2 V

(1) Reference output current is not internally limited.

(2) Specified by design; not production tested.

(6)

ELECTRICAL CHARACTERISTICS: GENERAL (continued)

ADS8363, ADS7263, ADS7223

POWER SUPPLY

AVDD to AGND, half-clock mode 2.7 5.0 5.5 V

AVDD Analog supply voltage

AVDD to AGND, full-clock mode 4.5 5.0 5.5 V

3V and 3.3V levels 2.3 2.5 3.6 V

DVDD Digital supply voltage

5V levels, half-clock mode only 4.5 5.0 5.5 V

AVDD = 3.6V 12.0 16.0 mA

AVDD = 5.5V 15.0 20.0 mA

AVDD = 3.6V, sleep/auto-sleep

0.8 1.2 mA

AIDD Analog supply current modes

AVDD = 5.5V, sleep/auto-sleep

0.9 1.4 mA

modes

Power-down mode 0.005 mA

DVDD = 3.6V, CLOAD= 10pF 1.1 2.5 mA

DIDD Digital supply current

DVDD = 5.5V, CLOAD= 10pF 3 6 mA

AVDD = DVDD = 3.6V 47.2 66.6 mW

Power dissipation (normal P_D

operation) AVDD = 5.5V, DVDD = 3.6V 86.5 117.0 mW

(7)

CHB1P/CHB3 CHB1N/CHB2 CHB0P/CHB1 CHB0N/CHB0 CHA1P/CHA3 CHA1N/CHA2 CHA0P/CHA1 CHA0N/CHA0

SDOB BUSY CLOCK CS RD CONVST SDI M0 1

2 3 4 5 6 7 8

24 23 22 21 20 19 18 17

ADS8363 ADS7263 ADS7223

(Thermal Pad)

CMB CMA AGND AVDD DGND DVDD NC SDOA

32

REFIO1

9 31

REFIO2

10 30

RGND

11 29

AGND

12 28

AVDD

13 27

NC

14 26

NC

15 25

M1

16

PIN CONFIGURATION

RHB PACKAGE QFN-32 (TOP VIEW)

Pin Descriptions

PIN

NAME NO. TYPE⁽¹⁾ DESCRIPTION

CHB1P/CHB3 1 AI Fully-differential noninverting analog input channel B1 or pseudo-differential input B3 CHB1N/CHB2 2 AI Fully-differential inverting analog input channel B1 or pseudo-differential input B2 CHB0P/CHB1 3 AI Fully-differential noninverting analog input channel B0 or pseudo-differential input B1 CHB0N/CHB0 4 AI Fully-differential inverting analog input channel B0 or pseudo-differential input B0 CHA1P/CHA3 5 AI Fully-differential noninverting analog input channel A1 or pseudo-differential input A3 CHA1N/CHA2 6 AI Fully-differential inverting analog input channel A1 or pseudo-differential input A2 CHA0P/CHA1 7 AI Fully-differential nonInverting analog input channel A1 or pseudo-differential input A1 CHA0N/CHA0 8 AI Fully-differential inverting analog input channel A1 or pseudo-differential input A0

REFIO1 9 AIO Reference voltage input/output 1. A ceramic capacitor of 22µF connected to RGND is required.

REFIO2 10 AIO Reference voltage input/output 2. A ceramic capacitor of 22µF connected to RGND is required.

RGND 11 P Reference ground. Connect to analog ground plane with a dedicated via.

AGND 12, 30 P Analog ground. Connect to analog ground plane.

AVDD 13, 29 P Analog power supply, 2.7V to 5.5V. Decouple to AGND with a 1mF ceramic capacitor.

NC 14, NC This pin is not internally connected.

15, 26

M1 16 DI Mode pin 1. Selects the digital output mode (seeTable 4).

M0 17 DI Mode pin 0. Selects analog input channel mode (seeTable 4).

Serial data input. This pin is used to set up of the internal registers, and can also be used in

SDI 18 DI

ADS8361-compatible manner. The data on SDI are ignored when CS is high.

Conversion start. The ADC switches from sample into hold mode on the rising edge of CONVST.

CONVST 19 DI Thereafter, the conversion starts with the next rising edge of the CLOCK pin.

Read data. Synchronization pulse for the SDOx outputs and SDI input. RD only triggers when CS is

RD 20 DI

low.

(1) AI = analog input, AIO = analog input/output, DI = digital input, DO = digital output, DIO = digital input/output, P = power supply, NC = not connected.

(8)

Pin Descriptions (continued)

PIN

NAME NO. TYPE⁽¹⁾ DESCRIPTION

Chip select. When this pin is low, the SDOx, SDI, and RD pins are active; when this pin is high, the CS 21 DI SDOx outputs are 3-stated, while the SDI and RD inputs are ignored.

External clock input. The range is 0.5MHz to 20MHz in half-clock mode, or 1MHz to 40MHz in

CLOCK 22 DI

full-clock mode.

Converter busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after

BUSY 23 DO

the conversion is complete.

SDOB 24 DO Serial data output for converter B. Active only if M1 is low. 3-state when CS is high.

SDOA 25 DO Serial data output for converter A. 3-state when CS is high.

DVDD 27 P Digital supply, 2.3V to 5.5V. Decouple to DGND with a 1mF ceramic capacitor.

DGND 28 P Digital ground. Connect to digital ground plane.

CMA 31 AI Common-mode voltage input for channels Ax (in pseudo-differential mode only).

CMB 32 AI Common-mode voltage input for channels Bx (in pseudo-differential mode only).

(9)

1 18 21

conversion n

data n 1 - CH

0/1 AD

A/B MSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D15 MSB CH 0/1 data n 1-

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

t_H1 t_S1 t₂

t₁

t_CLK

t_CLKL t_CLKH

CLOCK

CS

CONVST

BUSY

RD

SDO (CID = ‘1’)

x⁽¹⁾

SDI SDO (CID = ‘0’)

x⁽¹⁾

t_D1 t_D2

t_D6 t_D3

t_H3 t_D5

t₃

t_S2 t_H2

t_CONV

t_DATA

t_ACQ

TIMING DIAGRAMS

(1) The ADS7263/7223 output data with the MSB located as ADS8363 and last 2/4 bits being '0'.

Figure 1. Detailed Timing Diagram: Half-Clock Mode (ADS8361-Compatible)

(10)

conversion n

data n CLOCK

CS

CONVST

BUSY

RD

SDOx⁽¹⁾

t_CLKL

t₁

SDI

RD

SDOx⁽¹⁾

SDI (CID = ‘0’)

(CID = ‘1’)

t_CLK

t₂

t_D2

t_H1 t_S1

t_D5 t_H4 t_D4

data n

t_S2 t_H2

t_D6 t_D1

t_S2 t_H2

t_D5 t_H4 t_D4

t_CONV t_ACQ

t_CLKH

1 23 25 36 41

t_DATA

CH0/1 M S B

D 14 D

13 D 12 D

11 D

10 D9D8 D7D6D5D4 D3D0D1D0

D 15 D

14 D 13 D

12 D 11 D

10 D9D8D7 D6D5D4D3D2 D1D0

M S B

D 14 D

13 D 12 D

11 D

10 D9D8 D7D6D5D4 D3D2D1D0

D 15 D

14 D 13 D

12 D 11 D

10 D9D8 D7D6D5D4D3 D2D1D0 AD

A/B

TIMING DIAGRAMS (continued)

(2) The ADS7263/7223 output data with the MSB located as ADS8363 and last 2/4 bits being '0'.

Figure 2. Detailed Timing Diagram: Full-Clock Mode

(11)

TIMING CHARACTERISTICS⁽¹⁾

Over the recommended operating free-air temperature range of –40°C to +125°C, and DVDD = 2.3V to 5.5V, unless otherwise noted.

ADS8363, 7263, 7223

PARAMETER TEST CONDITIONS MIN MAX UNIT

tDATA Data throughput fCLK= max 1 ms

Half-clock mode 17.5 tCLK

tCONV Conversion time

Full-clock mode 35 t_CLK

t_ACQ Acquisition time 100 ns

Half-clock mode 0.5 20 MHz

f_CLK CLOCK frequency

Full-clock mode 1 40 MHz

Half-clock mode 50 2000 ns

tCLK CLOCK period

Full-clock mode 25 1000 ns

t_CLKL CLOCK low time 11.25 ns

t_CLKH CLOCK high time 11.25 ns

t1 CONVST rising edge to first CLOCK rising edge 12 ns

10 ns

t₂ CONVST high time Half-clock mode: timing

1 t_CLK

modes II and IV only Half-clock mode: timing

t₃ RD high time modes II, IV, SII, and SIV 1 t_CLK

only

tS1 RD high to CLOCK falling edge setup time 5 ns

t_H1 RD high to CLOCK falling edge hold time 5 ns

t_S2 Input data to CLOCK falling edge setup time 5 ns

t_H2 Input data to CLOCK falling edge hold time 4 ns

2.3V < DVDD < 3.6V 19 ns

tD1 CONVST rising edge to BUSY high delay⁽²⁾

4.5V < DVDD < 5.5V 16 ns

CLOCK 18th falling edge (half-clock mode) or 2.3V < DVDD < 3.6V 25 ns tD2 24th rising edge (full-clock mode) to BUSY low

4.5V < DVDD < 5.5V 20 ns

delay

Half-clock mode, 2.3V <

14 ns

DVDD < 3.6V tD3 CLOCK rising edge to next data valid delay

Half-clock mode, 4.5V <

12 ns

DVDD < 5.5V

tH3 Output data to CLOCK rising edge hold time Half-clock mode 3 ns

tD4 CLOCK falling edge to next data valid delay Full-clock mode 19 ns

t_H4 Output data to CLOCK falling edge hold time Full-clock mode 7 ns

2.3V < DVDD < 3.6V 16 ns

t_D5 RD falling edge to first data valid

4.5V < DVDD < 5.5V 12 ns

tD6 CS rising edge to SDOx 3-state 6 ns

(1) All input signals are specified with tR= tF= 1.5ns (10% to 90% of DVDD) and timed from a voltage level of (VIL+ VIH)/2.

(2) Not applicable in auto-sleep power-down mode.

(12)

3.0 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 - - - - - -

INL(LSB)

100 200 300 400

Data Rate (kSPS)

500 600 700 800 900 1000 ADS8363 Positive ADS7263 Positive ADS7223 Positive

ADS8363 Negative ADS7263 Negative ADS7223 Negative

3.0 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 - - - - - -

DNL (LSB)

100 200 300 400

Data Rate (kSPS)

500 600 700 800 900 1000 ADS8363 Positive ADS7263 Positive ADS7223 Positive

ADS8363 Negative ADS7263 Negative ADS7223 Negative

3.0 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 - - - - - -

INL(LSB)

0 8192 16384

Code

24576 32768 40960 49152 57344 65536

ADS8363 3.0

2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 - - - - - -

DNL(LSB)

0 8192 16384

Code

24576 32768 40960 49152 57344 65536 ADS8363

3.0 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 - - - - - -

INL(LSB)

-40 -25 -10 5 20 35 50 65 80 95 110 Temperature ( C)°

125 AVDD = 5V, Negative

AVDD = 3V, Negative AVDD = 5V, Positive AVDD = 3V, Positive

ADS8363 3.0

2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 - - - - - -

DNL(LSB)

-40 -25 -10 5 20 35 50 65 80 95 110 Temperature ( C)°

125 AVDD = 5V, Negative

AVDD = 3V, Negative AVDD = 5V, Positive AVDD = 3V, Positive

ADS8363

TYPICAL CHARACTERISTICS

At T_A= +25°C, AVDD = 5V, DVDD = 3.3V, V_REF= 2.5V (internal), and f_DATA= 1MSPS, unless otherwise noted.

INTEGRAL NONLINEARITY vs DIFFERENTIAL NONLINEARITY vs

DATA RATE DATA RATE

Figure 3. Figure 4.

INTEGRAL NONLINEARITY vs CODE DIFFERENTIAL NONLINEARITY vs CODE

INTEGRAL NONLINEARITY vs DIFFERENTIAL NONLINEARITY vs

TEMPERATURE TEMPERATURE

(13)

2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 - - - -

OffsetErrorandMatch(mV)

2.7 3.1 3.5 3.9 4.3 4.7 5.1

AVDD (V)

5.5 Offset Error Offset Match All Devices

2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 - - - -

OffsetErrorandMatch(mV)

-40 -25 -10 5 20 35 50 65 80 95 110 Temperature ( C)°

125 Offset Error Offset Match All Devices

0.10 0.08 0.06 0.04 0.02 0 0.02 0.04 0.06 0.08 0.10 - - - - -

Gain Error and Match (%)

2.7 3.1 3.5 3.9 4.3 4.7 5.1

AVDD (V)

5.5 Gain Error Gain Match All Devices

-40 -25 -10 5 20 35 50 65 80 95 110 Temperature ( C)°

125 0.10

0.08 0.06 0.04 0.02 0 0.02 0.04 0.06 0.08 0.10 - - - - -

Gain Error and Match (%)

Gain Error Gain Match All Devices

100

95

90

85

80

75

70

CMRR (dB)

2.7 3.1 3.5 3.9 4.3 4.7 5.1

AVDD (V)

5.5 All devices f = 100kHz

-40 -25 -10 5 20 35 50 65 80 95 110 Temperature ( C)°

125 100

95

90

85

80

75

70

CMRR (dB)

All devices f = 100kHz

TYPICAL CHARACTERISTICS (continued)

OFFSET ERROR AND OFFSET MATCH vs OFFSET ERROR AND OFFSET MATCH vs

ANALOG SUPPLY VOLTAGE TEMPERATURE

GAIN ERROR AND GAIN MATCH vs GAIN ERROR AND GAIN MATCH vs

COMMON-MODE REJECTION RATIO vs COMMON-MODE REJECTION RATIO vs

(14)

0 20 40 60 80 100 120 140 160 180 - - - - - - - - -

Amplitude(dB)

0

Frequency (kHz)

500 50 100 150 200 250 300 350 400 450

All Devices

0 20 40 60 80 100 120 140 160 180 - - - - - - - - -

Amplitude(dB)

0

Frequency (kHz)

250

50 100 150 200

All Devices

-40 -25 -10 5 20 35 50 65 80 95 110 Temperature ( C)°

125 100

95 90 85 80 75 70 65 60 55 50

SNRandSINAD(dB)

ADS8363 SINAD ADS7263 SINAD ADS7223 SINAD ADS8363 SNR

ADS7263 SNR ADS7223 SNR 100

95 90 85 80 75 70 65 60 55 50

SNRandSINAD(dB)

10

f_IN(kHz)

50

20 30 40

ADS8363 ADS7263 ADS7223

SINAD SINAD SINAD ADS8363 SNR

ADS7263 ADS7223

SNR SNR

80

84

92

96

100 -

-

- -

- 88

104

THD (dB)

10

f_IN(kHz)

50

20 30 40

ADS8363 ADS7263 ADS7223

-40 -25 -10 5 20 35 50 65 80 95 110 Temperature ( C)°

125 -

-

- 80

84

92

96

100 88

104

THD (dB)

ADS8363 ADS7263 ADS7223

f_IN= 10kHz

FREQUENCY SPECTRUM FREQUENCY SPECTRUM

(4096 Point FFT; f_IN= 10kHz) (4096 Point FFT; f_IN= 10kHz, f_SAMPLE= 0.5MSPS)

SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE +

DISTORTION DISTORTION

vs INPUT SIGNAL FREQUENCY vs TEMPERATURE

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION

(15)

105 103 101 99 97 9 93 91 89 87 85 5

SFDR (dB)

-40 -25 -10 5 20 35 50 65 80 95 110 Temperature ( C)°

125 ADS8363 ADS7263 ADS7223 f_IN= 10kHz

104

100

96

92

88

84

80

SFDR (dB)

10

f_IN(kHz)

50

20 30 40

ADS8363 ADS7263 ADS7223

-40 -25 -10 5 20 35 50 65 80 95 110 Temperature ( C)°

125 20

18 16 14 12 10 8 6 4 2 0 I(mA)AVDD

AVDD = 5.5V AVDD = 3.6V All Devices

-40 -25 -10 5 20 35 50 65 80 95 110 Temperature ( C)°

125 20

18 16 14 12 10 8 6 4 2 0 I(mA)DVDD

DVDD = 5.5V DVDD = 3.6V All Devices

0 100 200

f_SAMPLE(kSPS)

800 20

18 16 14 12 10 8 6 4 2 0 I(mA)AVDD

300 400 500 600 700 External Reference Internal Reference All Devices in Auto-Sleep Mode

0 100 200

f_SAMPLE(kSPS)

1000 20

18 16 14 12 10 8 6 4 2 0 I(mA)AVDD

All Devices

300 400 500 600 700 800 900 External Reference Internal Reference

SPURIOUS-FREE DYNAMIC RANGE SPURIOUS-FREE DYNAMIC RANGE

ANALOG SUPPLY CURRENT DIGITAL SUPPLY CURRENT

vs TEMPERATURE vs TEMPERATURE

ANALOG SUPPLY CURRENT vs DATA RATE

ANALOG SUPPLY CURRENT vs DATA RATE (Auto-Sleep Mode)

(16)

R 100W

SER R

100W

SW

R 100W

SER R

100W

SW

5pF C_PAR

C 5pF^PAR CHxx+

CHxx-

40pF C_S

C 40pF^S AVDD

AVDD

AGND

AGND Input

Mux CHx1P/CHx3

CHx1N/CHx2 CHx0P/CHx1 CHx0N/CHx0

To ADC

THEORY OF OPERATION

GENERAL DESCRIPTION Channel selection is performed using either the external M0 pin or the C[1:0] bits in the Configuration The ADS8363/7263/7223 contain two 16-/14-/12-bit

(CONFIG) register in fully-differential mode, or using analog-to-digital converters (ADCs), respectively, that

the SEQFIFO register in pseudo-differential mode. In operate based on the successive approximation

either case, changing the multiplexer settings impacts register (SAR) principle. These ADCs sample and

the conversion started with the next CONVST pulse.

convert simultaneously. Conversion time can be as low as 875ns. Adding an acquisition time of 100ns,

Table 1. Fully-Differential 2:1 Multiplexer and a margin of 25ns for propagation delay and

Configuration CONVST pulse generation, results in a maximum

conversion rate of 1MSPS. C1 C0 ADC+ ADC–

0 x CHx0P CHx0N

Each ADC has a fully-differential 2:1 multiplexer

1 x CHx1P CHx1N

front-end. In many common applications, all negative input signals remain at the same constant voltage (for

example, 2.5V). For these applications, the Table 2. Pseudo-Differential 4:1 Multiplexer multiplexer can be used in a pseudo-differential 4:1 Configuration

mode, where the CMx pins function as

C1 C0 ADC+ ADC–

common-mode pins and all four analog inputs are

0 0 CHx0 CMx/REFIOx

referred to the corresponding CMx pin.

0 1 CHx1 CMx/REFIOx

The ADS8363/7263/7223 also include a 2.5V internal

1 0 CHx2 CMx/REFIOx

reference. This reference drives two

1 1 CHx3 CMx/REFIOx

independently-programmable, 10-bit digital-to-analog converters (DACs), allowing the voltage at each of

The input path for the converter is fully differential the REFIOx pins to be adjusted through the internal

and provides a good common-mode rejection of 92dB REFDACx registers in 2.44mV steps. A low-noise,

at 100kHz (for the ADS8363). The high CMRR also unity-gain operational amplifier buffers each of the

helps suppress noise in harsh industrial DAC outputs and drives the REFIOx pin.

environments.

The ADS8363/7263/7223 provide a serial interface

Each of the 40pF sample-and-hold capacitors (shown that is compatible with the ADS8361. However,

as C_SinFigure 28) is connected through switches to instead of the ADS8361 A0 pin that controls the

the multiplexer output. Opening the switches holds channel selection, the ADS8363/7263/7223 offers a

the sampled data during the conversion process.

serial data input (SDI) pin that supports additional

After the conversion completes, both capacitors are functions described in the Digitalsection of this data

precharged for the duration of one clock cycle to the sheet (also see theADS8361 Compatibilitysection).

voltage present at the REFIOx pin. After precharging, the multiplexer outputs are connected to the sampling ANALOG

capacitors again. The voltage at the analog input pin This section discusses the analog input circuit, the is usually different from the reference voltage;

ADCs, and the reference design of the device. therefore, the sample capacitors must be charged to within one-half LSB for 16-, 14-, or 12-bit accuracy

Analog Inputs during the acquisition time t_ACQ (see the Timing

Diagrams).

Each ADC is fed by an input multiplexer, as shown in Figure 27. Each multiplexer is used in either a fully-differential 2:1 configuration (as shown in Table 1) or a pseudo-differential 4:1 configuration (as shown inTable 2).

Figure 28. Equivalent Analog Input Circuit Figure 27. Input Multiplexer Configuration