• Nie Znaleziono Wyników

CXA1746

N/A
N/A
Protected

Academic year: 2022

Share "CXA1746"

Copied!
19
0
0

Pełen tekst

(1)

Absolute Maximum Ratings (Ta=25°C)

• Supply voltage VCC 13 V

• Operating temperature Topr –40 to +85 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation

PD 350 mW

(Ta = 85 °C)

Recommended Operating Condition

• Supply voltage VCC 6 to 12 V Description

The CXA1746Q is a 2-channel electronic volume IC. A 34-bit serial data input controls the level and characteristics of the output signal. It may be used in car stereos and general audio systems.

Features

• Loudness

• Volume control

(from 0 dB to –87 dB, –∞ dB: Fine (1 dB-step) Coarse (8 dB-step)

• Balance

• Tone control

(3-band, 2 dB-step from –15 dB to +15 dB)

• Fader

(2 dB-step to –20 dB, –25 dB, –35 dB, –45 dB, –60 dB, –∞ dB)

• Input and gain selector (4 channels)

• Serial data control (DATA, CLK, CE)

• Single 8 V power supply

• Zero-cross detection circuit

• Timer

• Power-off mute

Structure Bipolar IC

Electronic Volume

48 pin QFP (Plastic)

(2)

Block Diagram and Pin Configuration

1 2 3 4 5 6 7 8 9 10 11 12

13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

37

38

39

40

41

42

43

44

45 46

47

48 LOUD

V OLUME 8dB STEP

V OLUME

1dB STEP TONE FA DER V CTBUFF

V CTBUFF V CTBUFF SHIFT REGISTER

LA TCH V CTBUFF 1dB STEP

V OLUME TONE FA DER

ZCDET

INPUT SWITCHINPUT SWITCH

LA TCH CONTROL LOUD

V CTBUFF V CTBUFF 8dB STEP

V OLUME

FNTO

REO1 CE

CLK

DGND GND

VCC

VCT DATA

TIMER

REO FNTO2 GAIN12

GAIN11

IN14 IN13

IN12

IN11 IN21

IN22

IN23 IN24

GAIN21

GAIN22

GAIN134 LDLC1 LDHC1 INAO1 VRIN1 TCHC1 TCMC11 TCMC12 TCLC11 TCLC12 TCO1 FDIN1

GAIN234 LDLC2 LDHC2 INAO2 VRIN2 TCHC2 TCMC21 TCMC22 TCLC21 TCLC22 TCO2 FDIN2

(3)

Pin Description and Equivalent Circuit Pin Pin Name I/O Resistance

Equivalent Circuit Description

No. Pin voltage

2 35

3 34

4 33

5 32

6

LDLC2 LDLC1

LDHC2 LDHC1

INAO2 INAO1

VRIN2 VRIN1

TCHC2

6.18k VCT

8.92k VCT

— VCT

10k VCT

5k

Sets loudness low cut-off frequency.

Set loudness high cut-off frequency

Input selector output

Volume input

GND VCC

2 35

3

GND VCC

34

GND VCC

4 33

32 5

GND VCC

VCC

(4)

Pin Pin Name I/O Resistance

Equivalent Circuit Description

No. Pin voltage

7 30

8 29

9 28

10 27

11 26

TCMC21 TCMC11

TCMC22 TCMC12

TCLC21 TCLC11

TCLC22 TCLC12

TCO2 TCO1

4k VCT

4k VCT

8k VCT

8k VCT

— VCT

Sets tone Mid frequency

Sets tone Mid frequency

Sets tone Bass frequency

Sets tone Bass frequency

Tone control output

GND VCC

7 30

GND VCC

8 29

GND VCC

9 28

27

GND VCC

10

GND VCC

11 26

(5)

Pin Pin Name I/O Resistance

Equivalent Circuit Description

No. Pin voltage

12 25

13 24

14 23

15

16

FDIN2 FDIN1

REO2 REO1

FNT02 FNT01

TIMER

DATA

24k VCT

— VCT

— VCT

~∞

~∞

Fader input

Rear output

Front output

Sets timer constant

Serial data input

GND VCC

12 25

GND VCC

13 24

GND VCC

14 23

GND VCC

15

VCC

16

(6)

Pin Pin Name I/O Resistance

Equivalent Circuit Description

No. Pin voltage

17 18 19 20

21

22

1 36 37 38 47 49

39 40 41 42 43 44 45 46

VCT VCC GND DGND

CLK

CE

GAIN234 GAIN134 GAIN12 GAIN11 GAIN21 GAIN22

IN14 IN13 IN12 IN11 IN21 IN22 IN23 IN24

— VCT

— VCC

— Gnd

~∞

~∞

~∞ VCT

50k VCT

1/2 VCC

Power supply input Ground

Digital ground

Serial clock input

Latch enable input

External gain setting for input amplifier

Signal input

GND VCC

21

GND VCC

22

GND VCC

36 37 38 47 48 1

39 40 41 43

GND VCC

44 45 46 42

(7)

Data Format

First Bit

Last Bit

D1 NOP

D2 NOP

D3 ISW

D4

D5 LOUD

D6

D7 VRC1

D8 D9 D10

D11 VRF1

D12 D13

D14 VRC2

D15 D16 D17

D18 VRF2

D19 D20

D21 TONE BASS

D22 D23 D24

D25 TONE MID

D26 D27 D28

D29 TONE TREBLE

D30 D31 D32

D33 FADER

D34 D35

D36 FADER SELECT

(8)

ISW

LOUD

VRC1/VRC2

MODE D3 D4

IN14/IN24, GAIN134/GAIN234 IN13/IN23, GAIN134/GAIN234 IN12/IN22, GAIN12/GAIN22 IN11/IN21, GAIN11/GAIN21

1 1 0 0

1 0 1 0

OUTPUT (dB) D6/D13 D7/D14 D8/D15 D9/D16 0

–8 –16 –24 –32 –40 –48 –56 –64 –72 –80 – ∞ – ∞

1 1 0 0 1 1 0 0 1 1 0 0 0 1

1 1 1 0 0 0 0 1 1 1 1 0 1

1 1 1 1 1 1 1 0 0 0 0 0

1 0 1 0 1 0 1 0 1 0 1 0 0

MODE D5

ON 1

OFF 0

(9)

VRF1/VRF2

BASS/MID/TREBLE

BOOST/CUT

OUTPUT (dB) D10/D17 D11/D18 D12/D19

0 –1 –2 –3 –4 –5 –6 –7

1 0 1 0 1 0 1 0 1

1 0 0 1 1 0 0 1

1 1 1 0 0 0 0

OUTPUT (dB) D20/D24/D28 D21/D25/D29 D22/D26/D30 15

12 10 8 6 4 2 0

1 0 1 0 1 0 1 0 1

1 0 0 1 1 0 0 1

1 1 1 0 0 0 0

MODE D23/D27/D31

BOOST 1

CUT 0

(10)

FADER

FADER SELECT

RESET

Reset is performed automatically when power is first supplied to the IC; there is no reset pin.

The following table shows the respective statuses of various settings after a reset has been performed.

However, from the time when power is first supplied until the first data transfer, keep CE high by pulling it up to VCC, etc.

OUTPUT (dB) D32 D33 D34 D35

– ∞ –60 –45 –35 –25 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1

1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

MODE D36

FRONT 1

REAR 0

MODE SET VALUE

INPUT 1

VRC1 – ∞dB

VRF1 –7 dB

VRC2 – ∞dB

VRF2 –7 dB

LOUD OFF

TONE BASS 0 dB

TONE MID 0 dB

TONE TREBLE 0 dB

FADER 0 dB, REAR

(11)

Waiting period

Min. Typ. Max.

3µs 5µs 9µs

30µs 50µs 90µs

300µs 500µs 900µs

3ms 5ms 9ms

30ms 50ms 90ms

300ms 500ms 900ms

TIMER pin capacitance C C = 100pF C = 0.001µF C = 0.01µF C = 0.1µF C = 1µF C = 10µF

Timer Waiting Period Setting Chart (VCC= 6 to 12V, operating temperature = –40°C to 85°C) Timing Chart

t1 tck tsu th t2 tL

tce t10.5µs

t2≥0.5µs tck1.0µs tsu≥0.5µs th0.5µs

tce4.0µs

D1 D2 D34 D35 D36 Invalid

tL≥tT+0.5µs

(tT is the maximum value for the timer operation time) CE

DATA

CLK

CE

(12)

Electrical Characteristics

VCC=8 V, Ta=25°C, Input=0 dB unless otherwise specified

Item Symbol Conditions Min. Typ. Max. Unit

— 21 23 mV

— 0.003 0.01 %

— 8 10 µVrms

8 — — dBm

72 90 —

85 90 —

7 8 9

7 8 9

13 15 17

13 15 17 dB

13 15 17

13 15 17

13 15 17

13 15 17

3 — 6

0 — 1.5

1 — VCC-1

V No signal

1 kHz, 5 dBm output

Short-circuit at input, A weight 1 kHz

1 kHz

100 Hz, VRC=–16 dB 10 kHz, VRC=–16dB

DATA, CLK, CE DATA, CLK, CE IN11 to 14 IN21 to 24 VRIN1, 2 FDIN1, 2 ICC

THD Vn Vom

CS ATTm

Glb Glh Gbb Gbc Gmb Gmc Gtb Gtc Vsh Vsl Vin Current consumption

Total Harmonic distortion Output noise voltage Max output voltage Separation

Max. attenuation factor Loudness LOW Loudness HIGH Bass max. boost gain Bass max. cut gain Mid max. boost gain Mid max. cut gain Treble max. boost gain Treble max. cut gain Input voltage HIGH Input voltage LOW Input voltage range

(13)

Electrical Characteristic Test Circuit

GAIN 234

LDLC 2

LDHC2 INA O2

VRIN 2

TCHC2 TCM C2 1

TCM C2 2

TC LC21

TC LC22

TCO 2

FDIN 2

2

15

GAIN 134

LDLC 1

LDHC1 INA O1

VRIN 1

TCHC1 TCM C1 1

TCM C1 2

TC LC11

TC LC12

TCO 1

FDIN 1

FNTO1 FNTO2

GAIN12 GAIN22 110

R5 10k C1

0.047µ C3

0.0022µ

345 C510µ

C7 0.0027µ

C9 0.033µ C11 0.022µ

6789 C13

10µ

C15 0.39µ

C17

10µ1112 AB AC V6

13R7 10k

R8 10k

AB 14

R14 10k

C20

0.01µ16R9 1k

V1 VEE 3-6V

S4C19

100µ

17

1819

20

21R10 1k

R11 1k

R12 10k

R13 10k

V3 V2

2223

24

R15 10k

V5 AC

1k R19

C21 220p

R15 10k

R20 1k

R18 1k

OPAMP

R17 10k

5V 0VCE 5V 0V CLK 5V 0V DATA

S1

C18 B

V4 AC A

S5_A

25

10µ 26

C15 0.39µ

27

C14 10µ 28

C12 0.022µ

C10 0.033µ

C8 0.0027µ

29303132

S2

C6 10µ 33

0.0022µ

C4 3435

0.047µ C2 10k

R5 36

10k 10k R4

R2

37 38

AC V14

S14B A39

AC V13

S13B A40 S12

AC V12

41 S11

AC V11

S21

AC V21

S22

AC V22

S23

AC V23

S24

AC V24

42 43 44 45 46 47 48

R3 R1 10k

10k S5_B

-60dBm

BA B A B A B A B A B A B AS3

VCC 3-6V

GAIN11 IN14 IN13 IN12 IN11 IN21 IN22 IN23 IN24 GAIN21

REO1 CE CLK DGND GND VCC VCT DATA TIMER REO2

(14)

Application Circuit

GAIN 234

LDLC 2

LDHC2 INA O2

VRIN 2

TCHC2 TCM C2 1

TCM C2 2

TC LC21

TC LC22

TCO 2

FDIN 2

2

15FNTO1 FNTO2

GAIN12 GAIN22 110

R5 10k C1

0.047µ C3

0.0022µ

345 C510µ

C7 0.0027µ C9

0.033µ C11

0.022µ

6789 C13

10µ

C15 0.39µ

C17

10µ

1112

13R7 10k

R8 10k14

C20

0.01µ

R9 1k

C19 33µ

17

19

21R10 1k

R11 1k

R12 10k

R13 10k 2324 TO POWER SUPPLY

C18 25

10µ 26

C15 0.39µ

27

C14 10µ 28

C12 0.022µ

C10 0.033µ

C8 0.0027µ

29303132

C6 10µ

0.0022µ

C4 3435

0.047µ C2

10k

R5 36

10k 10k R4

R2

37 47 48

R3 R1 10k

10k

1618

2022 TO CPU

38

33 39 40 41 42 43 44 45 46

INPUT SIGNAL SOURCES C21 10µ

OUTPUT SIGNAL

GAIN 134

LDLC 1

LDHC1 INA O1

VRIN 1

TCHC1 TCM C1 1

TCM C1 2

TC LC11

TC LC12

TCO 1

FDIN 1

GAIN11 IN14 IN13 IN12 IN11 IN21 IN22 IN23 IN24 GAIN21

REO1 CE CLK DGND GND VCC VCT DATA TIMER REO2 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

(15)

Description of Operation

(1) Gain of input amplifier

The input selector stage may be configured as a buffer or a non-inverting amplifier.

(2) Loud

The loudness function achieves the necessary frequency characteristics by using a filter as shown below.

The resistors are built in so that fLand fHcan be set by selecting C1and C2.

GAIN134 GAIN12 GAIN11 IN14

IN13 IN12 IN11

INA01 CXA1746Q

R1 R2

Input amp of channel 1 VCT

Gain=1+R2/R1

36 37

38 33

39 40 41 42

LDHC1 LDHC2

VCT VRIN1

VRIN2

R2=8.92k

20k 25.7k

CXA1746Q

C1

LDLC1 LDLC2 fL=1/(2πC1R1) fH=1/(2πC2R2)

C2

R1=6.18k

fL

fH

VCT 3

4

32 5

3 5

(16)

(3) Tone control BASS: LPF

MID: BPF

TREBLE: HPF

18 27 TCLC12

TCLC22

VCT R1=8k

CXA1746Q

C1

fL=1/(2πC1R1//R2)

R2=8k

VCT VCT

8k 8k

fL

TCMC12 TCMC22

VCT

HPF16k

CXA1746Q

C2

TCMC11 TCMC21 fL=1/(2πC2R3) fH=1/(2πC3R4)

R4=8k

C3 LPF

R3=4k

VCT

VCT 16k 4k

4k

fL fH

fM 29

8

38 7

3 1

10k

CXA1746Q

TCHC11 TCHC21 fH=1/(2πC4R5)

R5=5k

fH

C4

VCT

VCT 10k 10k

10k

(17)

(4) Zero-cross detector and Timer

A built-in zero-cross detection circuit is used to detect the zero-cross points of the input signal. When data arrived at the IC, they are executed at the next zero-cross point or when there is no input signal. This is to minimize 'click' noise during the transition of levels.

The timer circuit is added to ensure that the data is executed even when a zero-cross point is not detected after a pre-determined period of time from the falling edge of the CE pulse.

(5) VCT pin

The internal circuit of VCT pin has the following structure.

Insert a buffer when using it as a reference voltage for an external circuit.

(6) Power-off Mute

This function mutes the output pins FNTO1, FNTO2, REO1 and REO2, when the VCCgoes below 5V, by turning off the bias of the output stage of the fader circuit. By so doing, the 'pop' noise caused by the drop in these pins potential from VCC/2 during power-off can be avoided.

Time constant=(0.5/10µ)×C [sec]

CE

CXA1746Q 10µA

C TIMER 15 VCC

0.5V

VCT

GND 100k

100k VCC

CXA1746Q 17

(18)

VOLTAGE (dB) 20

10

0

–10

–201 10 100 1k 10k 100k

Tone Control Frequency Characteristics

FREQUENCY (Hz)

BASS MID TREBLE

–15 dB 15 dB

20

10

0

–10

–20

10 100 1k 10k 100k

Loudness Frequency Characteristics

FREQUENCY (Hz)

VRC=0 dB

VOLTAGE (dB)

–30

VRC=–8 dB VRC=–16 dB

VRC=–24 dB

1

Examole if Reoresentative Characteristics

(19)

SONY CODE EIAJ CODE JEDEC CODE

M

PACKAGE STRUCTURE

PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS

EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY

48PIN QFP (PLASTIC)

15.3 ± 0.4

12.0 – 0.1+ 0.4

0.8 0.3 – 0.1+ 0.15

0.24 13 24 25

36

37

48

1 12

2.2 – 0.15 + 0.35

0.9 ± 0.2

0.1 – 0.1 + 0.2

13.5

0.15 – 0.05 + 0.1

QFP-48P-L04 QFP048-P-1212

0.7g

0.15

Package Outline Unit : mm

Cytaty

Powiązane dokumenty

² If the data values are grouped in classes on a frequency table or column graph, do we still know what the highest and lowest values are..

Note that we consider 0 to be a natural number, this is a convention, some textbook author may exclude 0 from the set of natural numbers.. In other words rational numbers are

(b) Find the Cartesian equation of the plane Π that contains the two lines.. The line L passes through the midpoint

Thus eigenfunctions of the Fourier transform defined by the negative definite form −x 2 in one variable are the same as eigenfunctions of the classical in- verse Fourier

4.5.. Denote this difference by R.. In a typical problem of combinatorial num- ber theory, the extremal sets are either very regular, or random sets. Our case is different. If A is

In 1920’s, Hardy and Littlewood introduced an ana- lytic method for solving Waring’s problem: That is, they showed that every sufficiently large natural number can be expressed as a

Totally geodesic orientable real hypersurfaces M 2n+1 of a locally conformal Kaehler (l.c.K.) manifold M 2n+2 are shown to carry a naturally induced l.c.c.. manifolds in a natural

The paper contains the estimates from above of the principal curvatures of the solution to some curvature equations.. A correction of the author’s previous argument is