74ACT11194

(1)

SCAS094 − NOVEMBER 1989 − REVISED APRIL 1993

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265 POST OFFICE BOX 1443

•

HOUSTON, TEXAS 77001

Copyright  1993, Texas Instruments Incorporated

2−1

• Inputs Are TTL-Voltage Compatible

• Parallel-to-Serial, Serial-to-Parallel Conversions

• Left or Right Shifts

• Parallel Synchronous Loading

• Direct Overriding Clear

• Temporary Data Latching Capability

• Center-Pin V

_CC

and GND Configurations Minimize High-Speed Switching Noise

• ^EPIC ^t (Enhanced-Performance Implanted CMOS) 1- m m Process

• 500-mA Typical Latch-Up Immunity at 125 ° C

• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

description

This bidirectional shift register features parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:

Parallel (broadside) load

Shift right (in the direction Q

_A

toward Q

_D

) Shift left (in the direction Q

_D

toward Q

_A

) Inhibit clocking (do nothing).

Synchronous parallel loading is accomplished by applying the 4 bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low.

Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode control inputs are low.

The 74ACT11194 is characterized for operation from − 40 ° C to 85 ° C.

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11 SR SER

Q_A Q_B GND GND GND GND Q_C Q_D SL SER

S0 S1 A B V_CC V_CC C D CLR CLK DW OR N PACKAGE

(TOP VIEW)

!" # $%&" !# '%()$!" *!"&+

*%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"#

#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&

"&#"0 !)) '!!&"&#+

EPIC is a trademark of Texas Instruments Incorporated.

(2)

•

2−2

FUNCTION TABLE

INPUTS OUTPUTS

CLR MODE

CLK SERIAL PARALLEL

QA QB QC QD

CLR S1 S0 CLK

LEFT RIGHT A B C D QA QB QC QD

L X X X X X X X X X L L L L

H X X L X X X X X X QA0 QB0 QC0 QD0

H H H ↑ X X a b c d a b c d

H L H ↑ X H X X X X H QAn QBn QCn

H L H ↑ X L X X X X L QAn QBn QCn

H H L ↑ H X X X X X QBn QCn QDn H

H H L ↑ L X X X X X QBn QCn QDn L

H L L X X X X X X X QA0 QB0 QC0 QD0

H = high level (steady state) L = low level (steady state)

X = irrelevant (any input, including transitions)

↑ = transition from low to high level

a,b,c,d = the level of steady-state input at inputs A, B, C, or D, respectively.

QA0, QB0, QC0, QD0 = the level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were established.

QAn, QBn, QCn, QDn = the level of QA, QB, QC, or QD respectively, before the most-recent ↑ transition of the clock.

timing clear, load, right-shift, inhibit, and clear sequences

CLK S0

QC CLR

QB QA

Load

Shift Right Mode

Control Inputs S1

QD Serial R

Data Inputs L

A

Parallel Data Inputs

B

H L

C D

H L

Outputs

Clear

Shift Left Inhibit

Clear

(3)

•

2−3

logic symbol ^†

CLR

SRG4 12 R

1 C4 S0 20

1

3, 4D B 17

3, 4D C 14

2 3 8 19 0

S1 11 CLK

QA QB QC /2

M0 3

1, 4D SR SER 1

3, 4D 18

A

9 QD 3, 4D

13 D

2, 4D SL SER 10

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

1S C1 1R

R Mode S0

Control Inputs S1

19

20

A B C D

18 17 14 13

SR SER 1 10

SL SER Parallel Inputs

1S C1 1R

R

1S C1 1R

R

1S C1 1R

R

CLK

CLR

QA 2

QB 3

QC 8

QD 9

Parallel Outputs

(4)

•

2−4

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

^†

Supply voltage range, V

_CC

. . . −0.5 V to 7 V Input voltage range, V

_I

(see Note 1) . . . −0.5 V to V

_CC

+ 0.5 V Output voltage range, V

_O

(see Note 1) . . . −0.5 V to V

_CC

+ 0.5 V Input clamp current, I

_IK

(V

_I

< 0 or V

_I

> V

_CC

) . . . ± 20 mA Output clamp current, I

_OK

(V

_O

< 0 or V

_O

> V

_CC

) . . . ± 50 mA Continuous output current, I

_O

(V

_O

= 0 to V

_CC

) . . . ± 50 mA Continuous current through V

_CC

or GND . . . ± 100 mA Storage temperature range . . . −65 ° C to 150 ° C

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

recommended operating conditions

MIN NOM MAX UNIT

VCC Supply voltage 4.5 5.5 V

VIH High-level input voltage 2 V

VIL Low-level input voltage 0.8 V

VI Input voltage 0 VCC V

VO Output voltage 0 VCC V

IOH High-level output current − 24 mA

IOL Low-level output current 24 mA

Dt /Dv Input transition rise or fall rate 0 10 ns/ V

TA Operating free-air temperature − 40 85 °C

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC TA = 25°C

MIN MAX UNIT

PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX UNIT

IOH = − 50 A 4.5 V 4.4 4.4

IOH = − 50 mA

5.5 V 5.4 5.4

VOH IOH = − 24 mA

4.5 V 3.94 3.8 V

VOH IOH = − 24 mA 5.5 V 4.94 4.8

V

IOH = − 75 mA} 5.5 V 3.85

IOL = 50 A 4.5 V 0.1 0.1

IOL = 50 mA

5.5 V 0.1 0.1

VOL IOL = 24 mA 4.5 V 0.36 0.44 V

VOL IOL = 24 mA 5.5 V 0.36 0.44

V

IOL = 75 mA} 5.5 V 1.65

II VI = VCC or GND 5.5 V ±0.1 ±1 mA

ICC VI = VCC or GND, IO = 0 5.5 V 8 80 mA

DICCw One input at 3.4 V, Other inputs at GND or VCC 5.5 V 0.9 1 mA

Ci VI = VCC or GND 5 V 4 pF

‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.

§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC.

(5)

•

2−5

timing requirements over recommended operating free-air temperature range, V _CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

TA = 25°C

MIN MAX UNIT MIN MAX MIN MAX UNIT

fclock Clock frequency 0 100 0 100 MHz

tw Pulse duration CLK high or low 5 5

tw Pulse duration ns

CLR low 4.5 4.5 ns

Select 6 6

tsu Setup time before CLK ↑ Data 4 4 ns

tsu Setup time before CLK ↑

CLR inactive 1 1

ns

th Hold time after CLK ↑ Select 1.5 1.5

th Hold time after CLK ↑ ns

Data 1 1 ns

switching characteristics over recommended operating free-air temperature range, V _CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER FROM TO TA = 25°C

MIN MAX UNIT

PARAMETER FROM

(INPUT)

TO

(OUTPUT) MIN TYP MAX MIN MAX UNIT

fmax 100 130 100 MHz

tPLH CLK Any Q 2.2 5.8 6.9 2.2 7.7

tPHL CLK Any Q ns

2.6 6.6 7.7 2.6 8.8 ns

tPLH CLR Any Q 2.9 7.1 9.1 2.9 10.3 ns

operating characteristics, V _CC = 5 V, T _A = 25 ° C

PARAMETER TEST CONDITIONS TYP UNIT

Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 69 pF

(6)

•

2−6

PARAMETER MEASUREMENT INFORMATION

50% VCC 1.5 V

1.5 V 1.5 V

3 V

3 V 0 V

0 V th

tsu

VOLTAGE WAVEFORMS Data Input

tPLH

tPHL

tPLH VOH

VOH VOL

VOL 1.5 V 1.5 V

3 V 0 V

50% VCC 50% VCC

Input (see Note B)

Out-of-Phase Output In-Phase

Output Timing Input

(see Note B)

50% VCC

VOLTAGE WAVEFORMS

3 V

0 V

1.5 V 1.5 V

tw

VOLTAGE WAVEFORMS Input

LOAD CIRCUIT From Output

Under Test CL = 50 pF

(see Note A) 500 Ω

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.

C. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

(7)

PACKAGING INFORMATION

Orderable Device Status⁽¹⁾ Package Type

Package Drawing

Pins Package Qty

Eco Plan⁽²⁾ Lead/Ball Finish MSL Peak Temp⁽³⁾

74ACT11194DW OBSOLETE SOIC DW 20 TBD Call TI Call TI

74ACT11194N OBSOLETE PDIP N 20 TBD Call TI Call TI

(1)The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 24-Jun-2005

Addendum-Page 1

(8)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(9)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(10)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(11)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(12)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(13)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(14)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(15)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(16)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(17)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(18)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(19)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(20)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(21)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(22)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(23)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

(24)

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

Addendum-Page 1

74ACT11194







•

•

• Inputs Are TTL-Voltage Compatible

• Parallel-to-Serial, Serial-to-Parallel Conversions

• Left or Right Shifts

• Parallel Synchronous Loading

• Direct Overriding Clear

• Temporary Data Latching Capability

• Center-Pin V

and GND Configurations Minimize High-Speed Switching Noise

• EPIC t (Enhanced-Performance Implanted CMOS) 1- m m Process

• 500-mA Typical Latch-Up Immunity at 125 ° C

• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

description

This bidirectional shift register features parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:

Parallel (broadside) load

Shift right (in the direction Q

toward Q

) Shift left (in the direction Q

toward Q

) Inhibit clocking (do nothing).

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low.

Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode control inputs are low.

The 74ACT11194 is characterized for operation from − 40 ° C to 85 ° C.







•

•

timing clear, load, right-shift, inhibit, and clear sequences







•

•

logic symbol †

logic diagram (positive logic)







•

•

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . −0.5 V to 7 V Input voltage range, V

(see Note 1) . . . −0.5 V to V

+ 0.5 V Output voltage range, V

(see Note 1) . . . −0.5 V to V

+ 0.5 V Input clamp current, I

(V

< 0 or V

> V

) . . . ± 20 mA Output clamp current, I

(V

< 0 or V

> V

) . . . ± 50 mA Continuous output current, I

(V

= 0 to V

) . . . ± 50 mA Continuous current through V

or GND . . . ± 100 mA Storage temperature range . . . −65 ° C to 150 ° C

recommended operating conditions

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)







•

•

timing requirements over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

switching characteristics over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

operating characteristics, V CC = 5 V, T A = 25 ° C







•

•

• ^EPIC ^t (Enhanced-Performance Implanted CMOS) 1- m m Process

logic symbol ^†

timing requirements over recommended operating free-air temperature range, V _CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

switching characteristics over recommended operating free-air temperature range, V _CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

operating characteristics, V _CC = 5 V, T _A = 25 ° C