74VCX162244

August 1997 Revised June 2005

7 4 VC X16 2244 L o w V o lt age 16- Bit Buf fer /Li ne Driv er w ith 3. 6V T o le rant Input s and O u tput s and 26 : Seri es Res ist or in Output s

74VCX162244

Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 : Series Resistor in Outputs

General Description

The VCX162244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/

receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.

The 74VCX162244 is designed for low voltage (1.2V to 3.6V) V_CC applications with I/O capability up to 3.6V. The 74VCX162244 is also designed with 26: series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.

The 74VCX162244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation.

Features

■1.2V to 3.6V V_CC supply operation

■3.6V tolerant inputs and outputs

■26: series resistors in outputs

■t_PD

3.3 ns max for 3.0V to 3.6V V_CC

■Power-off high impedance inputs and outputs

■Supports live insertion and withdrawal

■Static Drive (I_OH/I_OL) r12 mA @ 3.0V V_CC

■Latch-up performance exceeds 300 mA

■ESD performance:

Human body model ! 2000V Machine model ! 200V

■Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)

Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

Ordering Code:

Note 2: Ordering Code “G” indicates Trays.

Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Order Number Package Number Package Description

74VCX162244G (Note 2)(Note 3)

BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74VCX162244MTD (Note 3)

MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

■Uses proprietary noise/EMI reduction circuitry

74VCX162244

Pin Assignment for TSSOP

Pin Assignment for FBGA

(Top Thru View)

FBGA Pin Assignments

Truth Tables

Pin Names Description

OE_n Output Enable Input (Active LOW)

I₀–I₁₅ Inputs

O₀–O₁₅ Outputs

NC No Connect

1 2 3 4 5 6

A O₀ NC OE₁ OE₂ NC I₀

B O₂ O₁ NC NC I₁ I₂

C O₄ O₃ V_CC V_CC I₃ I₄

D O₆ O₅ GND GND I₅ I₆

E O₈ O₇ GND GND I₇ I₈

F O₁₀ O₉ GND GND I₉ I₁₀

G O₁₂ O₁₁ V_CC V_CC I₁₁ I₁₂

H O₁₄ O₁₃ NC NC I₁₃ I₁₄

J O₁₅ NC OE₄ OE₃ NC I₁₅

Inputs Outputs

OE₁ I₀–I₃ O₀–O₃

L L L

L H H

H X Z

Inputs Outputs

OE₂ I₄–I₇ O₄–O₇

L L L

L H H

H X Z

Inputs Outputs

OE₃ I₈–I₁₁ O₈–O₁₁

L L L

L H H

H X Z

Inputs Outputs

OE₄ I₁₂–I₁₅ O₁₂–O₁₅

L L L

L H H

H X Z

7 4 VC X16 2244 Functional Description

The 74VCX162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) con- trolled with each nibble functioning identically, but indepen- dent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE out-

puts are controlled by an Output Enable (OE_n) input. When OE_n is LOW, the outputs are in the 2-state mode. When OE_n is HIGH, the standard outputs are in the high imped- ance mode but this does not interfere with entering new data into the inputs.

Logic Diagram

74VCX162244

Conditions

Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Rat- ings. The “Recommended Operating Conditions” table will define the condi- tions for actual device operation.

Note 5: I_O Absolute Maximum Rating must be observed.

Note 6: Floating or unused inputs must be held HIGH or LOW.

DC Electrical Characteristics (2.7V  V _CC d 3.6V)

Supply Voltage (V_CC) 0.5V to 4.6V DC Input Voltage (V_I) 0.5V to 4.6V Output Voltage (V_O)

Outputs 3-STATE 0.5V to 4.6V

Outputs Active (Note 5) 0.5V to V_CC0.5V DC Input Diode Current (I_IK) V_I  0V 50 mA DC Output Diode Current (I_OK)

V_O  0V 50 mA

V_O! V_CC 50 mA

DC Output Source/Sink Current

(I_OH/I_OL) r50 mA

DC V_CC or GND Current per

Supply Pin (I_CC or GND) r100 mA Storage Temperature Range (T_STG) 65qC to 150qC

Power Supply

Operating 1.2V to 3.6V

Data Retention Only 1.2V to 3.6V

Input Voltage 0.3V to 3.6V

Output Voltage (V_O)

Output in Active States 0V to V_CC

Output in 3-State 0.0V to 3.6V

Output Current in I_OH/I_OL

V_CC 3.0V to 3.6V r12 mA

V_CC 2.3V to 2.7V r8 mA

V_CC 1.65V to 2.3V r3 mA

V_CC 1.4V to 1.6V r2 mA

V_CC 1.2V r100 PA

Free Air Operating Temperature (T_A) 40qC to 85qC Minimum Input Edge Rate ('t/'V)

V_IN 0.8V to 2.0V, V_CC 3.0V 10 ns/V

Symbol Parameter Conditions

V_CC

Min Max Units

(V)

V_IH HIGH Level Input Voltage 2.7 - 3.6 2.0

V 2.3 - 2.7 1.6

1.65 - 2.3 0.65 x V_CC 1.4 - 1.6 0.65 x V_CC 1.2 0.65 x V_CC

V_IL LOW Level Input Voltage 2.7 - 3.6 0.8

V

2.3 - 2.7 0.7

1.65 - 2.3 0.35 x V_CC 1.4 - 1.6 0.35 x V_CC

1.2 0.5 x V_CC

V_OH HIGH Level Output Voltage I_OH 100 PA 2.7 - 3.6 V_CC - 0.2

V

I_OH 6 mA 2.7 2.2

I_OH 8 mA 3.0 2.4

I_OH 12 mA 3.0 2.2

I_OH 100 PA 2.7 - 3.6 V_CC - 0.2

I_OH 4 mA 2.3 2.0

I_OH 6 mA 2.3 1.8

I_OH 8 mA 2.3 1.7

I_OH 100 PA 1.65 - 2.3 V_CC - 0.2

I_OH 3 mA 1.65 1.25

I_OH 100 PA 1.4 - 1.6 V_CC - 0.2

I_OH 1 mA 1.4 1.05

7 4 VC X16 2244 DC Electrical Characteristics (2.7V < VCC £ 3.6V)

Note 7: Outputs disabled or 3-STATE only.

AC Electrical Characteristics

Note 8: For C_L 50 _PF, add approximately 300 ps to the AC maximum specification.

Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t_OSHL) or LOW-to-HIGH (t_OSLH).

Symbol Parameter Conditions V_CC

Min Max Units

(V)

V_OL LOW Level Output Voltage I_OL 100 PA 2.7 - 3.6 0.2

V

I_OL 6 mA 2.7 0.4

I_OL 8 mA 3.0 0.55

I_OL 12 mA 3.0 0.8

I_OL 100 PA 2.7 - 3.6 0.2

I_OL 6 mA 2.3 0.4

I_OL 8 mA 2.3 0.6

I_OL 100 PA 1.65 - 2.3 0.2

I_OL 3 mA 1.65 0.3

I_OL 100 PA 1.4 - 1.6 0.2

I_OL 1 mA 1.4 0.35

I_OL 100 PA 1.2 0.1

I_I Input Leakage Current 0 d V_Id 3.6V 1.2 - 3.6 r5.0 PA

I_OZ 3-STATE Output Leakage 0 d V_Od 3.6V

1.2 - 3.6 r10 PA

V_I V_IH or V_IL

I_OFF Power-OFF Leakage Current 0 d (V_I, V_O) d 3.6V 0 10

PA

I_CC Quiescent Supply Current V_I V_CC or GND 1.2 - 3.6 20

V_CCd (V_I, V_O) d 3.6V (Note 7) 1.2 - 3.6 r20 PA

'I_CC Increase in I_CC per Input V_IH V_CC0.6V 2.7 - 3.6 750 PA

Symbol Parameter Conditions V_CC T_A 40qC to 85qC

Units Figure

(V) Min Max Number

t_PHL, Propagation Delay C_L 30 pF, R_L 500: 3.3 r 0.3 0.8 3.3

ns

Figures

t_PLH 2.5 r 0.2 1.0 3.8 1, 2

1.8 r 0.15 1.5 7.6

C_L 15 pF, R_L 2k: 1.5 r 0.1 1.0 15.2 Figures 1.2 1.5 38 5, 6

t_PZL, Output Enable Time C_L 30 pF, R_L 500: 3.3 r 0.3 0.8 3.8

ns

Figures 1, 3, 4

t_PZH 2.5 r 0.2 1.0 5.1

1.8 r 0.15 1.5 9.8

C_L 15 pF, R_L 2k: 1.5 r 0.1 1.0 19.6 Figures 5, 7, 8

1.2 1.5 49

t_PLZ, Output Disable Time C_L 30 pF, R_L 500: 3.3 r 0.3 0.8 3.6

ns

Figures 1, 3, 4

t_PHZ 2.5 r 0.2 1.0 4.0

1.8 r 0.15 1.5 7.2

C_L 15 pF, R_L 2k: 1.5 r 0.1 1.0 14.4 Figures 5, 7, 8

1.2 1.5 36

t_OSHL Output to Output Skew C_L 30 pF, R_L 500: 3.3 r 0.3 0.5

ns

t_OSLH (Note 9) 2.5 r 0.2 0.5

1.8 r 0.15 0.75 C_L 15 pF, R_L 2k: 1.5 r 0.1 1.5

1.2 1.5

74VCX162244

Capacitance

Symbol Parameter Conditions

V_CC T_A 25qC Units (V) Typical V_OLP Quiet Output Dynamic Peak V_OL C_L 30 pF, V_IH V_CC, V_IL 0V 1.8 0.15

V

2.5 0.25

3.3 0.35

V_OLV Quiet Output Dynamic Valley V_OL C_L 30 pF, V_IH V_CC, V_IL 0V 1.8 0.15 V 2.5 0.25 3.3 0.35 V_OHV Quiet Output Dynamic Valley V_OH C_L 30 pF, V_IH V_CC, V_IL 0V 1.8 1.55

V

2.5 2.05

3.3 2.65

Symbol Parameter Conditions T_A 25qC

Units Typical

C_IN Input Capacitance V_CC 1.8, 2.5V or 3.3V, V_I 0V or V_CC 6 pF

C_OUT Output Capacitance V_I 0V or V_CC, V_CC 1.8V, 2.5V or 3.3V 7 pF

C_PD Power Dissipation Capacitance V_I 0V or V_CC, f 10 MHz, V_CC 1.8V, 2.5V or 3.3V 20 pF

7 4 VC X16 2244 AC Loading and Waveforms (V _CC 3.3V r 0.3V to 1.8V r 0.15V)

FIGURE 1. AC Test Circuit

FIGURE 2. Waveform for Inverting and Non-Inverting Functions

FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic

FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic

TEST SWITCH

t_PLH, t_PHL Open

t_PZL, t_PLZ 6V at V_CC 3.3 r 0.3V;

V_CC x 2 at V_CC 2.5 r 0.2V; 1.8 r 0.15V

t_PZH, t_PHZ GND

Symbol V_CC

3.3V r 0.3V 2.5V r 0.2V 1.8V r 0.15V

V_mi 1.5V V_CC/2 V_CC/2

V_mo 1.5V V_CC/2 V_CC/2

V_X V_OL  0.3V V_OL  0.15V V_OL  0.15V V_Y V_OH 0.3V V_OH 0.15V V_OH 0.15V

74VCX162244

AC Loading and Waveforms (V _CC 1.5V r 0.1V to 1.2V)

FIGURE 5. AC Test Circuit

FIGURE 6. Waveform for Inverting and Non-Inverting Functions

FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic

FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic

TEST SWITCH

t_PLH, t_PHL Open

t_PZL, t_PLZ V_CC x 2 at V_CC 1.5V r 0.1V

t_PZH, t_PHZ GND

Symbol V_CC

1.5V r 0.1V

V_mi V_CC/2

V_mo V_CC/2

V_X V_OL 0.1V

V_Y V_OL  0.1V

7 4 VC X16 2244 Physical Dimensions

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A

V o lt age 16-Bi t Buff er/ L ine Dri ver wit h 3.6V T o ler ant Inp u ts and Outpu ts and 26 : Ser ies R e sist or in Output

Physical Dimensions

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the

2. A critical component in any component of a life support device or system whose failure to perform can be rea-