MSP430F21X1

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MIXED SIGNAL MICROCONTROLLER

1

FEATURES • Serial Onboard Programming, No External Programming Voltage Needed, Programmable

• Low Supply Voltage Range: 1.8 V to 3.6 V

Code Protection by Security Fuse

• Ultra-Low Power Consumption

• Bootstrap Loader – Active Mode: 250 μA at 1 MHz, 2.2 V

• On Chip Emulation Module – Standby Mode: 0.7 μA

• Family Members:

– Off Mode (RAM Retention): 0.1 μA

– MSP430F2101

• Ultra-Fast Wake-Up From Standby Mode in

– 1KB + 256B Flash Memory Less Than 1 μs

– 128B RAM

• 16-Bit RISC Architecture, 62.5-ns Instruction

– MSP430F2111 Cycle Time

– 2KB + 256B Flash Memory

• Basic Clock Module Configurations

– 128B RAM – Internal Frequencies up to 16 MHz With

Four Calibrated Frequencies to ±1% – MSP430F2121

– 32-kHz Crystal – 4KB + 256B Flash Memory

– High-Frequency Crystal up to 16 MHz – 256B RAM

– Resonator – MSP430F2131

– External Digital Clock Source – 8KB + 256B Flash Memory

• 16-Bit Timer_A With Three Capture/Compare – 256B RAM

Registers • Available in a 20-Pin Plastic Small-Outline

• On-Chip Comparator for Analog Signal Wide Body (SOWB) Package, 20-Pin Plastic Compare Function or Slope Analog-to-Digital Small-Outline Thin (TSSOP) Package, 20-Pin

(A/D) Conversion TVSOP Package, and 24-Pin QFN Package

• Brownout Detector • For Complete Module Descriptions, See the MSP430x2xx Family User’s Guide (SLAU144)

DESCRIPTION

The Texas Instruments MSP430 family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 μs.

The MSP430x21x1 series is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer, versatile analog comparator, and sixteen I/O pins.

Typical applications include sensor systems that capture analog signals, convert themto digital values, and then process the data for display or for transmission to a host system. Stand-alone RF sensor front end is another area of application. The analog comparator provides slope A/D conversion capability.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

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Table 1. Available Options

PACKAGED DEVICES

PLASTIC PLASTIC PLASTIC PLASTIC

T_A

20-PIN SOWB 20-PIN TSSOP 20-PIN TVSOP 24-PIN QFN

(DW) (PW) (DGV) (RGE)

MSP430F2101IDW MSP430F2101IPW MSP430F2101IDGV MSP430F2101IRGE

-40°C to 85°C

MSP430F2101TDW MSP430F2101TPW MSP430F2101TDGV MSP430F2101TRGE

-40°C to 105°C

Development Tool Support

All MSP430 microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging and programming through easy-to-use development tools. Recommended hardware options include:

• Debugging and Programming Interface with Target Board – MSP-FET430U28 (PW package)

• Debugging and Programming Interface – MSP-FET430UIF (USB)

– MSP-FET430PIF (Parallel Port)

• Target Board

– MSP-TS430PW28 (PW package)

• Production Programmer – MSP-GANG430

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1 2 3 4 5 6 7 8 9

10 11

12 13 14 15 16 17 18 19 TEST 20

V_CC P2.5/CA5 V_SS XOUT/P2.7/CA7 XIN/P2.6/CA6 RST/NMI P2.0/ACLK/CA2 P2.1/INCLK/CA3 P2.2/CAOUT/TA0/CA4

P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2

P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/TA2/CA1 P2.3/TA1/CA0

11

P2.4/TA2/CA1

10

P2.3/TA1/CA0

9

NC

8

P2.2/CAOUT/TA0/CA4

7

P2.1/INCLK/CA3

12

NC

RST/NMI 5

XIN/P2.6/CA6 4

XOUT/P2.7/CA7 3

VSS 2

NC 1

P2.0/ACLK/CA2 6

14 P1.1/TA0

15 P1.2/TA1

16 P1.3/TA2

17 P1.4/SMCLK/TCK

18 P1.5/TA0/TMS

13 P1.0/TACLK

20

P1.6/TA1/TDI/TCLK

21

P1.7/TA2/TDO/TDI

22

TEST

23

VCC

24

P2.5/CA5

19

NC

Exposed Thermal Pad

Device Pinout

DW, PW, or DGV PACKAGE (TOP VIEW)

RGE PACKAGE (TOP VIEW)

A. NC = Not internally connected

B. Exposed thermal pad connection to V_SSrecommended.

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Basic Clock System+

RAM 256B 256B 128B 128B

Brownout Protection

RST/NMI

VCC VSS

MCLK

SMCLK

Watchdog WDT+

15/16 Bit

Timer_A3 3 CC Registers 16MHz

CPU incl. 16 Registers

Emulation (2BP)

XOUT

JTAG Interface

Flash 8kB 4kB 2kB 1kB ACLK

XIN

Port P1 8 I/ O Interrupt capability, pullup/down

resistors Comparator

_A+

8 Channel Input Mux

P1.x, JTAG 8

P2.x, XIN/XOUT

8

Port P2 8 I/ O Interrupt capability, pullup/down

resistors

MDB MAB

Functional Block Diagram

NOTE: See port schematics section for detailed I/O information.

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Table 2. Terminal Functions

TERMINAL

NO.

DW, I/O DESCRIPTION

NAME PW,

or RGE DGV

General-purpose digital I/O pin

P1.0/TACLK 13 13 I/O

Timer_A, clock signal TACLK input General-purpose digital I/O pin

P1.1/TA 14 14 I/O

Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit General-purpose digital I/O pin

P1.2/TA1 15 15 I/O

Timer_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O pin

P1.3/TA2 16 16 I/O

Timer_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin / SMCLK signal output

P1.4/SMCLK/TCK 17 17 I/O

Test Clock input for device programming and test

General-purpose digital I/O pin / Timer_A, compare: Out0 output

P1.5/TA/TMS 18 18 I/O

Test Mode Select input for device programming and test General-purpose digital I/O pin / Timer_A, compare: Out1 output

P1.6/TA1/TDI/TCLK 19 20 I/O

Test Data Input or Test Clock Input for programming and test General-purpose digital I/O pin / Timer_A, compare: Out2 output P1.7/TA2/TDO/TDI⁽¹⁾ 20 21 I/O

Test Data Output or Test Data Input for programming and test General-purpose digital I/O pin / ACLK output

P2.0/ACLK/CA2 8 6 I/O

Comparator_A+, CA2 input

General-purpose digital I/O pin / Timer_A, clock signal at INCLK

P2.1/INCLK/CA3 9 7 I/O

Comparator_A+, CA3 input General-purpose digital I/O pin

P2.2/CAOUT/TA/CA4 10 8 I/O Timer_A, capture: CCI0B input/BSL receive Comparator_A+, output / CA4 input

P2.3/CA0/TA1 11 10 I/O

P2.4/CA1/TA2 12 11 I/O

Comparator_A+, CA1 input General-purpose digital I/O pin

P2.5/CA5 3 24 I/O

Comparator_A+, CA5 input Input terminal of crystal oscillator XIN/P2.6/CA6 6 4 I/O General-purpose digital I/O pin

Comparator_A+, CA6 input Output terminal of crystal oscillator XOUT/P2.7/CA7⁽²⁾ 5 3 I/O General-purpose digital I/O pin

RST/NMI 7 5 I Reset or nonmaskable interrupt input

Selects test mode for JTAG pins on Port1. The device protection fuse is connected to

TEST 1 22 I

TEST.

VCC 2 23 Supply voltage

VSS 4 2 Ground reference

QFN Pad NA Pad NA QFN package thermal pad. Connect to V_SS. (1) TDO or TDI is selected via JTAG instruction.

(2) If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset.

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General-Purpose Register Program Counter

Stack Pointer Status Register Constant Generator

General-Purpose Register

General-Purpose Register General-Purpose Register

PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5

R12 R13 General-Purpose Register General-Purpose Register

R6 R7 General-Purpose Register General-Purpose Register

R8 R9

R10 R11

R14 R15

SHORT-FORM DESCRIPTION CPU

The MSP430™ CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses and can be handled with all instructions.

Instruction Set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data.

Table 3 shows examples of the three types of instruction formats; Table 4 shows the address modes.

Table 3. Instruction Word Formats

INSTRUCTION FORMAT EXAMPLE OPERATION

Dual operands, source-destination ADD R4,R5 R4 + R5→R5

Single operands, destination only CALL R8 PC→(TOS), R8→PC

Relative jump, unconditional/conditional JNE Jump-on-equal bit = 0

Table 4. Address Mode Descriptions

ADDRESS MODE S⁽¹⁾ D⁽²⁾ SYNTAX EXAMPLE OPERATION

Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10→R11

Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)→M(6+R6)

Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE)→M(TONI)

Absolute ✓ ✓ MOV&MEM,&TCDAT M(MEM)→M(TCDAT)

Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10)→M(Tab+R6)

M(R10)→R11

Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11 R10 + 2→R10

Immediate ✓ MOV #X,TONI MOV #45,TONI #45→M(TONI)

(1) S = source (2) D = destination

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Operating Modes

The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation.

An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

• Active mode (AM) – All clocks are active.

• Low-power mode 0 (LPM0) – CPU is disabled.

– ACLK and SMCLK remain active. MCLK is disabled.

• Low-power mode 1 (LPM1)

– CPU is disabled ACLK and SMCLK remain active. MCLK is disabled.

– DCO dc-generator is disabled if DCO not used in active mode.

• Low-power mode 2 (LPM2) – CPU is disabled.

– MCLK and SMCLK are disabled.

– DCO dc-generator remains enabled.

– ACLK remains active.

• Low-power mode 3 (LPM3) – CPU is disabled.

– MCLK and SMCLK are disabled.

– DCO dc-generator is disabled.

– ACLK remains active.

• Low-power mode 4 (LPM4) – CPU is disabled.

– ACLK is disabled.

– MCLK and SMCLK are disabled.

– DCO dc-generator is disabled.

– Crystal oscillator is stopped.

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Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0xFFFF to 0xFFC0.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, if flash is not programmed), the CPU goes into LPM4 immediately after power up.

Table 5. Interrupt Vector Addresses

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up PORIFG

External reset RSTIFG

Watchdog WDTIFG Reset 0xFFFE 31, highest

Flash key violation KEYV⁽¹⁾ PC out of range⁽²⁾

NMI NMIIFG (non)-maskable

Oscillator fault OFIFG (non)-maskable 0xFFFC 30

Flash memory access violation ACCVIFG^{(1) (3)} (non)-maskable

0xFFFA 29

0xFFF8 28

Comparator_A+ CAIFG maskable 0xFFF6 27

Watchdog Timer+ WDTIFG maskable 0xFFF4 26

Timer_A3 TACCR0 CCIFG⁽⁴⁾ maskable 0xFFF2 25

TACCR2, TACCR1 CCIFG,

Timer_A3 maskable 0xFFF0 24

TAIFG^{(1) (4)}

0xFFEE 23

0xFFEC 22

0xFFEA 21

0xFFE8 20

I/O port P2 (eight flags) P2IFG.0 to P2IFG.7^{(1) (4)} maskable 0xFFE6 19

I/O port P1 (eight flags) P1IFG.0 to P1IFG.7^{(1) (4)} maskable 0xFFE4 18

0xFFE2 17

0xFFE0 16

See⁽⁵⁾ 0xFFDE 15

See⁽⁶⁾ 0xFFDC to 0xFFC0 14 to 0, lowest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF) or from within unused address range.

(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

(4) Interrupt flags are located in the module.

(5) This location is used as bootstrap loader security key (BSLSKEY).

A value of 0xAA55 at this location disables the BSL completely.

A value of 0x0 disables the erasure of the flash if an invalid password is supplied.

(6) The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if necessary.

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Special Function Registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

Legend

rw Bit can be read and written.

rw-0, 1 Bit can be read and written. It is Reset or Set by PUC.

rw-(0), (1) Bit can be read and written. It is Reset or Set by POR.

SFR bit is not present in device.

Table 6. Interrupt Enable 1

Address 7 6 5 4 3 2 1 0

00h ACCVIE NMIIE OFIE WDTIE

rw-0 rw-0 rw-0 rw-0

WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode.

OFIE Oscillator fault interrupt enable NMIIE (Non)maskable interrupt enable ACCVIE Flash access violation interrupt enable

Table 7. Interrupt Enable 2

Address 7 6 5 4 3 2 1 0

01h

Table 8. Interrupt Flag Register 1

Address 7 6 5 4 3 2 1 0

02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw-0 rw-(0) rw-(1) rw-1 rw-(0)

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on V_CCpower-up or a reset condition at RST/NMI pin in reset mode.

OFIFG Flag set on oscillator fault

RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V_CCpower up.

PORIFG Power-on reset interrupt flag. Set on V_CCpower up.

NMIIFG Set via RST/NMI pin

Table 9. Interrupt Flag Register 2

Address 7 6 5 4 3 2 1 0

03h

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Memory Organization

Table 10. Memory Organization

MSP430F2101 MSP430F2111 MSP430F2121 MSP430F2131

Memory Size 1 KB Flash 2 KB Flash 4 KB Flash 8 KB Flash

Main: interrupt vector Flash 0xFFFF to 0xFFE0 0xFFFF to 0xFFE0 0xFFFF to 0xFFE0 0xFFFF to 0xFFE0 Main: code memory Flash 0xFFFF to 0xFC00 0xFFFF to 0xF800 0xFFFF to 0xF000 0xFFFF to 0xE000

Information memory Size 256 Byte 256 Byte 256 Byte 256 Byte

Flash 0x10FF to 0x1000 0x10FF to 0x1000 0x10FF to 0x1000 0x10FF to 0x1000

Boot memory Size 1 KB 1 KB 1 KB 1 KB

ROM 0x0FFF to 0x0C00 0x0FFF to 0x0C00 0x0FFF to 0x0C00 0x0FFF to 0x0C00

RAM Size 128 B 128 B 256 Byte 256 Byte

0x027F to 0x0200 0x027F to 0x0200 0x02FF to 0x0200 0x02FF to 0x0200 Peripherals 16-bit 0x01FF to 0x0100 0x01FF to 0x0100 0x01FF to 0x0100 0x01FF to 0x0100 8-bit 0x0FF to 0x010 0x0FF to 0x010 0x0FF to 0x010 0x0FF to 0x010

8-bit SFR 0x0F to 0x00 0x0F to 0x00 0x0F to 0x00 0x0F to 0x00

Bootstrap Loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to theMSP430memoryvia theBSLis protected by user-defined password.Abootstrap loader security key is provided at address 0FFDEh to disable the BSL completely or to disable the erasure of the flash if an invalid password is supplied. For complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User’s Guide, literature number SLAU319.

Table 11. BSL Keys

BSLKEY DESCRIPTION

00000h Erasure of flash disabled if an invalid password is supplied

0AA55h BSL disabled

any other value BSL enabled

Table 12. BSL Function Pins

BSL FUNCTION DW, PW, DGV PACKAGE PINS RGE PACKAGE PINS

Data transmit 14 - P1.1 14 - P1.1

Data receive 10 - P2.2 8 - P2.2

Flash Memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A to D can be erased individually, or as a group with segments 0 to n.

Segments A to D are also called information memory.

• Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required.

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Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the following clock signals:

• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal

• Main clock (MCLK), the system clock used by the CPU

• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules

Table 13. DCO Calibration Data, Provided From Factory In Flash Info Memory Segment A

DCO FREQUENCY CALIBRATION REGISTER SIZE ADDRESS

CALBC1_1MHZ byte 0x010FF

1 MHz

CALBC0_1MHZ byte 0x010FE

CALBC1_8MHZ byte 0x010FD

8 MHz

CALBC0_8MHZ byte 0x010FC

CALBC1_12MHZ byte 0x010FB

12 MHz

CALBC0_12MHZ byte 0x010FA

CALBC1_16MHZ byte 0x010F9

16 MHz

CALBC0_16MHZ byte 0x010F8

Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.

Digital I/O

There are two 8-bit I/O ports implemented—ports P1 and P2.

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt condition is possible.

• Edge-selectable interrupt input capability for all eight bits of port P1 and P2.

• Read/write access to port-control registers is supported by all instructions.

• Each I/O has an individually programmable pullup/pulldown resistor.

Watchdog Timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.

Comparator_A+

The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,

battery-voltage supervision, and monitoring of external analog signals.

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Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 14. Timer_A3 Signal Connections

INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER

DEVICE INPUT MODULE MODULE

OUTPUT SIGNAL INPUT NAME BLOCK

DW, PW, DGV RGE SIGNAL DW, PW, DGV RGE

13 - P1.0 13 - P1.0 TACLK TACLK

ACLK ACLK

Timer NA

SMCLK SMCLK

9 - P2.1 7 - P2.1 INCLK INCLK

14 - P1.1 14 - P1.1 TA CCI0A 14 - P1.1 14 - P1.1

10 - P2.2 8 - P2.2 TA CCI0B 18 - P1.5 18 - P1.5

CCR0 TA

VSS GND

VCC VCC

15 - P1.2 15 - P1.2 TA1 CCI1A 11 - P2.3 10 - P2.3

CAOUT

CCI1B 15 - P1.2 15 - P1.2

(internal) CCR1 TA1

VSS GND 19 - P1.6 20 - P1.6

VCC VCC

16 - P1.3 16 - P1.3 TA2 CCI2A 12 - P2.4 11 - P2.4

ACLK (internal) CCI2B 16 - P1.3 16 - P1.3

CCR2 TA2

VSS GND 20 - P1.7 21 - P1.7

VCC VCC

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Peripheral File Map

Table 15. Peripherals With Word Access

MODULE REGISTER NAME SHORT NAME ADDRESS OFFSET

Timer_A Capture/compare register TACCR2 0x0176

Capture/compare register TACCR1 0x0174

Capture/compare register TACCR0 0x0172

Timer_A3 register TAR 0x0170

Capture/compare control TACCTL2 0x0166

Timer_A3 control TACTL 0x0160

Timer_A3 interrupt vector TAIV 0x012E

Flash Memory Flash control 3 FCTL3 0x012C

Flash control 2 FCTL2 0x012A

Flash control 1 FCTL1 0x0128

Watchdog Timer+ Watchdog/timer control WDTCTL 0x0120

Table 16. Peripherals With Byte Access

MODULE REGISTER NAME SHORT NAME ADDRESS OFFSET

Comparator_A+ Comparator_A port disable CAPD 0x005B

Comparator_A control 2 CACTL2 0x005A

Comparator_A control 1 CACTL1 0x0059

Basic Clock Basic clock system control 3 BCSCTL3 0x0053

Basic clock system control 2 BCSCTL2 0x0058

Basic clock system control 1 BCSCTL1 0x0057

DCO clock frequency control DCOCTL 0x0056

Port P2 Port P2 resistor enable P2REN 0x002F

Port P2 selection P2SEL 0x002E

Port P2 interrupt enable P2IE 0x002D

Port P2 interrupt edge select P2IES 0x002C

Port P2 interrupt flag P2IFG 0x002B

Port P2 direction P2DIR 0x002A

Port P2 output P2OUT 0x0029

Port P2 input P2IN 0x0028

Port P1 Port P1 resistor enable P1REN 0x0027

Port P1 selection P1SEL 0x0026

Port P1 interrupt enable P1IE 0x0025

Port P1 interrupt edge select P1IES 0x0024

Port P1 interrupt flag P1IFG 0x0023

Port P1 direction P1DIR 0x0022

Port P1 output P1OUT 0x0021

Port P1 input P1IN 0x0020

Special Function SFR interrupt flag 2 IFG2 0x0003

SFR interrupt flag 1 IFG1 0x0002

SFR interrupt enable 2 IE2 0x0001

SFR interrupt enable 1 IE1 0x0000

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6 MHz 12 MHz 16 MHz

1.8 V 2.2 V 2.7 V 3.3 V 3.6 V Supply Voltage − V

SystemFrequency−MHz

Supply voltage range during flash memory programming

Supply voltage range during program execution Legend :

Absolute Maximum Ratings

⁽¹⁾

Voltage applied at VCCto VSS -0.3 V to 4.1 V

Voltage applied to any pin⁽²⁾ -0.3 V to (V_CC+ 0.3 V)

Diode current at any device terminal ±2 mA

Unprogrammed device -55°C to 150°C

Storage temperature, T_stg⁽³⁾

Programmed device -55°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. The JTAG fuse-blow voltage, V_FB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

Recommended Operating Conditions

⁽¹⁾

MIN NOM MAX UNIT

During program execution 1.8 3.6

VCC Supply voltage, AVCC= DVCC= VCC V

During flash memory programming 2.2 3.6

V_SS Supply voltage, AV_SS= DV_SS= V_SS 0 V

I version -40 85

T_A Operating free-air temperature °C

T version -40 105

VCC= 1.8 V, Duty cycle = 50%±10% 0 6

Processor frequency (maximum MCLK

fSYSTEM frequency)^{(2) (1)} VCC= 2.7 V, Duty cycle = 50%±10% 0 12 MHz

(seeFigure 1) V_CC ≥3.3 V, Duty cycle = 50%±10% 0 16

(1) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

(2) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.

NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC

of 2.2 V.

Figure 1. Operating Area

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0.0 1.0 2.0 3.0 4.0 5.0

0

fDCO– DCO Frequency – MHz

ActiveModeCurrent–mA

V_CC= 3 V

4 8 12 16

V_CC= 2.2 V

T = 85°CA

T = 25°CA

T = 85°CA

T = 25°C_A

0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0

1.5

V_CC– Supply Voltage – V

ActiveMode Current–mA

f_DCO= 16 MHz

f_DCO= 12 MHz

f_DCO= 8 MHz

f_DCO= 1 MHz

2.0 2.5 3.0 3.5 4.0

Active Mode Supply Current (into DV

_CC

+ AV

_CC

) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(1) (2)}

PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT

f_DCO= f_MCLK= f_SMCLK= 1 MHz, 2.2 V 250 300

fACLK= 32768 Hz, Program executes in flash, Active mode (AM)

IAM,1MHz BCSCTL1 = CALBC1_1MHZ, µA

current (1 MHz) DCOCTL = CALDCO_1MHZ, 3 V 350 410

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

f_DCO= f_MCLK= f_SMCLK= 1 MHz, 2.2 V 200

fACLK= 32768 Hz, Program executes in RAM, Active mode (AM)

IAM,1MHz current (1 MHz) BCSCTL1 = CALBC1_1MHZ,DCOCTL = CALDCO_1MHZ, 3 V 300 µA

f_MCLK= f_SMCLK= f_ACLK= 32768 Hz / 8 -40°C to 85°C 2 5

2.2 V

= 4096 Hz,

105°C 6

f_DCO= 0 Hz,

-40°C to 85°C 3 9

Active mode (AM) Program executes in flash,

I_AM,4kHz µA

current (4 kHz) SELMx = 11, SELS = 1,

3 V DIVMx = DIVSx = DIVAx = 11,

105°C 9

f_MCLK= f_SMCLK= f_{DCO(0, 0)}≈100 kHz, 2.2 V 60 85

fACLK= 0 Hz, Active mode (AM)

I_AM,100kHz Program executes in flash, µA

current (100 kHz) RSELx = 0, DCOx = 0, CPUOFF = 0, 3 V 72 95

SCG0 = 0, SCG1 = 0, OSCOFF = 1 (1) All inputs are tied to 0 V or V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.

Typical Characteristics - Active-Mode Supply Current (Into V

_CC

)

ACTIVE-MODE CURRENT

vs ACTIVE-MODE CURRENT

SUPPLY VOLTAGE vs

T_A= 25°C DCO FREQUENCY

Figure 2. Figure 3.

(16)

Low-Power-Mode Supply Currents (Into V

_CC

) Excluding External Current

^{(1) (2)}

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

f_MCLK= 0 MHz, 2.2 V 65 80

fSMCLK= fDCO= 1 MHz, f_ACLK= 32768 Hz, Low-power mode 0

ILPM0,1MHz BCSCTL1 = CALBC1_1MHZ, µA

(LPM0) current⁽³⁾ DCOCTL = CALDCO_1MHZ, 3 V 85 100

f_MCLK= 0 MHz, 2.2 V 37 48

fSMCLK= fDCO(0, 0)≈100 kHz, Low-power mode 0 f_ACLK= 0 Hz,

ILPM0,100kHz µA

(LPM0) current⁽³⁾ RSELx = 0, DCOx = 0, 3 V 41 52

f_MCLK= f_SMCLK= 0 MHz, -40°C to 85°C 22 29

2.2 V

f_DCO= 1 MHz, f_ACLK= 32768 Hz, 105°C 31

Low-power mode 2 BCSCTL1 = CALBC1_1MHZ,

I_LPM2 (LPM2) current⁽⁴⁾ DCOCTL = CALDCO_1MHZ, -40°C to 85°C 25 32 µA

3 V CPUOFF = 1, SCG0 = 0, SCG1 = 1,

105°C 34

OSCOFF = 0

-40°C 0.7 1.2

25°C 0.7 1

2.2 V

85°C 1.6 2.3

fDCO= fMCLK= fSMCLK= 0 MHz,

105°C 3 6

Low-power mode 3 f_ACLK= 32768 Hz,

I_LPM3,LFXT1 µA

(LPM3) current⁽⁴⁾ CPUOFF = 1, SCG0 = 1, SCG1 = 1, -40°C 0.9 1.2

OSCOFF = 0

25°C 0.9 1.2

85°C 3 V 1.6 2.8

105°C 3 7

-40°C 0.1 0.5

fDCO= fMCLK= fSMCLK= 0 MHz,

25°C 0.1 0.5

Low-power mode 4 f_ACLK= 0 Hz,

ILPM4 2.2 V/3 V µA

(LPM4) current⁽⁵⁾ CPUOFF = 1, SCG0 = 1, SCG1 = 1, 85°C 0.8 1.9

OSCOFF = 1

105°C 2 4

(1) All inputs are tied to 0 V or V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.

(3) Current for brownout and WDT clocked by SMCLK included.

(4) Current for brownout and WDT clocked by ACLK included.

(5) Current for brownout included.

(17)

Schmitt-Trigger Inputs (Ports P1, P2)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

0.45 V_CC 0.75 V_CC

V_IT+ Positive-going input threshold voltage 2.2 V 1 1.65 V

3 V 1.35 2.25

0.25 VCC 0.55 VCC

VIT- Negative-going input threshold voltage 2.2 V 0.55 1.20 V

3 V 0.75 1.65

2.2 V 0.2 1

V_hys Input voltage hysteresis (V_IT+ - V_IT-) V

3 V 0.3 1

For pullup: VIN= VSS,

RPull Pullup/pulldown resistor 20 35 50 kΩ

For pulldown: V_IN= V_CC

C_I Input capacitance V_IN= V_SSor V_CC 5 pF

Inputs (Ports P1, P2)

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT

Port P1, P2: P1.x to P2.x, External trigger pulse width to

t_(int) External interrupt timing 2.2 V/3 V 20 ns

set interrupt flag⁽¹⁾

(1) An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int)is met. It may be set with trigger signals shorter than t_(int).

Leakage Current (Ports P1, P2)

I_lkg(Px.y) High-impedance leakage current ^{(1) (2)} 2.2 V/3 V ±50 nA

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.

(18)

Outputs (Ports P1, P2)

I_OH(max)= -1.5 mA⁽¹⁾ V_CC- 0.25 V_CC

2.2 V

I_OH(max)= -6 mA⁽²⁾ V_CC- 0.6 V_CC

V_OH High-level output voltage V

I_OH(max)= -1.5 mA⁽¹⁾ V_CC- 0.25 V_CC

IOH(max)= -6 mA⁽²⁾ 3 V VCC- 0.6 VCC

IOL(max)= 1.5 mA⁽¹⁾ VSS VSS+ 0.25

2.2 V

I_OL(max)= 6 mA⁽²⁾ V_SS V_SS+ 0.6

V_OL Low-level output voltage V

I_OL(max)= 1.5 mA⁽¹⁾ V_SS V_SS+ 0.25

I_OL(max)= 6 mA⁽²⁾ 3 V V_SS V_SS+ 0.6

(1) The maximum total current, IOH(max)and IOL(max), for all outputs combined, should not exceed±12 mA to hold the maximum voltage drop specified.

(2) The maximum total current, IOH(max)and IOL(max), for all outputs combined, should not exceed±48 mA to hold the maximum voltage drop specified.

Output Frequency (Ports P1, P2)

2.2 V 10

f_Px.y Port output frequency (with load) P1.4/SMCLK, C_L= 20 pF, R_L= 1 kΩ^{(1) (2)} MHz

3 V 12

2.2 V 12

fPort_CLK Clock output frequency P2.0/ACLK, P1.4/SMCLK, CL= 20 pF⁽²⁾ MHz

3 V 16

(1) Alternatively, a resistive divider with two 0.5-kΩresistors between VCCand VSSis used as load. The output is connected to the center tap of the divider.

(2) The output voltage reaches at least 10% and 90% VCCat the specified toggle frequency.

(19)

V_OL− Low-Level Output Voltage − V 0.0

5.0 10.0 15.0 20.0 25.0

0.0 0.5 1.0 1.5 2.0 2.5

V_CC= 2.2 V P2.4

T_A= 25°C

T_A= 85°C

OLI−Typical Low-Level Output Current−mA

V_OL− Low-Level Output Voltage − V 0.0

10.0 20.0 30.0 40.0 50.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 V_CC= 3 V

P2.4 T_A= 25°C

T_A= 85°C

OLI−Typical Low-Level Output Current−mA

V_OH− High-Level Output Voltage − V

−25.0

−20.0

−15.0

−10.0

−5.0 0.0

0.0 0.5 1.0 1.5 2.0 2.5

V_CC= 2.2 V P2.4

T_A= 25°C T_A= 85°C

OHI−Typical High-Level Output Current−mA

V_OH− High-Level Output Voltage − V

−50.0

−40.0

−30.0

−20.0

−10.0 0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 V_CC= 3 V

P2.4

T_A= 25°C T_A= 85°C

OHI−Typical High-Level Output Current−mA

Typical Characteristics - Outputs

One output loaded at a time.

TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT

vs vs

LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE

TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs vs

HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE

(20)

0 1

t d(BOR) VCC

V(B_IT−)

Vhys(B_IT−)

V_CC(start)

POR/Brownout Reset (BOR)

^{(1) (2)}

0.7×

V_CC(start) SeeFigure 8 dV_CC/dt≤3 V/s V

V(B_IT-)

SeeFigure 8through

V_{(B_IT-)} dV_CC/dt≤3 V/s 1.71 V

Figure 10

-40°C to 85°C 70 130 180

Vhys(B_IT-) SeeFigure 8 dVCC/dt≤3 V/s mV

105°C 70 130 210

td(BOR) SeeFigure 8 2000 µs

Pulse length needed at

t(reset) RST/NMI pin to accepted 2.2 V/3 V 2 µs

reset internally

(1) The current consumption of the brownout module is already included in the I_CCcurrent consumption data. The voltage level V(B_IT-)+ Vhys(B_IT-)is≤1.8 V.

(2) During power up, the CPU begins code execution following a period of t_d(BOR)after V_CC= V_{(B_IT-)}+ V_{hys(B_IT-)}. The default DCO settings must not be changed until VCC ≥VCC(min), where VCC(min)is the minimum supply voltage for the desired operating frequency.

Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage

(21)

VCC(drop) VCC 3 V

t pw

0 0.5 1 1.5 2

0.001 1 1000

Typical Conditions

1 ns 1 ns

t_pw− Pulse Width − µs VCC(drop)−V

t_pw− Pulse Width − µs V_CC= 3 V

VCC

0 0.5 1 1.5 2

VCC(drop)

t pw

t_pw− Pulse Width − µs VCC(drop)−V

3 V

0.001 1 1000 t_f t_r

t_pw− Pulse Width − µs t_{f =}t_r

Typical Conditions V_CC= 3 V

Typical Characteristics - POR/Brownout Reset (BOR)

Figure 9. V_CC(drop)Level With a Square Voltage Drop to Generate a POR/Brownout Signal

Figure 10. VCC(drop)Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

(22)

DCO(RSEL,DCO) DCO(RSEL,DCO+1) average

DCO(RSEL,DCO) DCO(RSEL,DCO+1)

32 × f × f

f =

MOD × f + (32 – MOD) × f

Main DCO Characteristics

• All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15.

• DCO control bits DCOx have a step size as defined by parameter S

_DCO

.

• Modulation control bits MODx select how often f

DCO(RSEL,DCO+1)

is used within the period of 32 DCOCLK cycles. The frequency f

DCO(RSEL,DCO)

is used for the remaining cycles. The frequency is an average equal to:

DCO Frequency

PARAMETER TEST CONDITIONS V_CC MIN TYP MAX UNIT

RSELx<14 1.8 3.6

VCC Supply voltage range RSELx = 14 2.2 3.6 V

RSELx = 15 3.0 3.6

f_DCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 2.2 V/3 V 0.06 0.14 MHz

fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 2.2 V/3 V 0.14 0.28 MHz

f_DCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3 V 12.0 18.5 MHz

f_DCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3 V 16.0 26.0 MHz

Frequency step between

SRSEL range RSEL and RSEL+1 SRSEL= fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) 2.2 V/3 V 1.55 ratio Frequency step between tap

SDCO SDCO= fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) 2.2 V/3 V 1.05 1.08 1.12 ratio

DCO and DCO+1

Duty cycle Measured at P1.4/SMCLK 2.2 V/3 V 40 50 60 %

(23)

Calibrated DCO Frequencies - Tolerance at Calibration

Frequency tolerance at calibration 25°C 3 V -1 ±0.2 +1 %

BCSCTL1 = CALBC1_1MHZ,

fCAL(1MHz) 1-MHz calibration value DCOCTL = CALDCO_1MHZ, 25°C 3 V 0.990 1 1.010 MHz

Gating time: 5 ms

f_CAL(8MHz) 8-MHz calibration value DCOCTL = CALDCO_8MHZ, 25°C 3 V 7.920 8 8.080 MHz

Gating time: 5 ms

Gating time: 2 ms

Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C

PARAMETER TEST CONDITIONS T_A V_CC MIN TYP MAX UNIT

1-MHz tolerance over

0°C to 85°C 3 V -2.5 ±0.5 +2.5 %

temperature 8-MHz tolerance over

0°C to 85°C 3 V -2.5 ±1 +2.5 %

temperature

12-MHz tolerance over 0°C to 85°C 3 V -2.5 ±1 +2.5 %

temperature

16-MHz tolerance over

0°C to 85°C 3 V -3 ±2 +3 %

temperature

2.2 V 0.97 1 1.03

f_CAL(1MHz) 1-MHz calibration value DCOCTL = CALDCO_1MHZ, 0°C to 85°C 3 V 0.975 1 1.025 MHz

Gating time: 5 ms

3.6 V 0.97 1 1.03

2.2 V 7.76 8 8.4

f_CAL(8MHz) 8-MHz calibration value DCOCTL = CALDCO_8MHZ, 0°C to 85°C 3 V 7.8 8 8.2 MHz

Gating time: 5 ms 3.6 V 7.6 8 8.24

2.2 V 11.7 12 12.3

fCAL(12MHz) 12-MHz calibration value DCOCTL = CALDCO_12MHZ, 0°C to 85°C 3 V 11.7 12 12.3 MHz

Gating time: 5 ms

3.6 V 11.7 12 12.3

BCSCTL1 = CALBC1_16MHZ, 3 V 15.52 16 16.48

fCAL(16MHz) 16-MHz calibration value DCOCTL = CALDCO_16MHZ, 0°C to 85°C MHz

3.6 V 15 16 16.48

Gating time: 2 ms

(24)

Calibrated DCO Frequencies - Tolerance Over Supply Voltage V

_CC

1-MHz tolerance over V_CC 25°C 1.8 V to 3.6 V -3 ±2 +3 %

16-MHz tolerance over VCC 25°C 3 V to 3.6 V -3 ±2 +3 %

f_CAL(1MHz) 1-MHz calibration value DCOCTL = CALDCO_1MHZ, 25°C 1.8 V to 3.6 V 0.97 1 1.03 MHz

Gating time: 5 ms

fCAL(8MHz) 8-MHz calibration value DCOCTL = CALDCO_8MHZ, 25°C 1.8 V to 3.6 V 7.76 8 8.24 MHz

Gating time: 5 ms

fCAL(12MHz) 12-MHz calibration value DCOCTL = CALDCO_12MHZ, 25°C 2.2 V to 3.6 V 11.64 12 12.36 MHz

Gating time: 5 ms

f_CAL(16MHz) 16-MHz calibration value DCOCTL = CALDCO_16MHZ, 25°C 3 V to 3.6 V 15 16 16.48 MHz

Gating time: 2 ms

Calibrated DCO Frequencies - Overall Tolerance

1-MHz tolerance I: -40°C to 85°C

1.8 V to 3.6 V -5 ±2 +5 %

overall T: -40°C to 105°C

8-MHz tolerance I: -40°C to 85°C 1.8 V to 3.6 V -5 ±2 +5 %

overall T: -40°C to 105°C

12-MHz I: -40°C to 85°C

2.2 V to 3.6 V -5 ±2 +5 %

tolerance overall T: -40°C to 105°C

16-MHz I: -40°C to 85°C

3 V to 3.6 V -6 ±3 +6 %

tolerance overall T: -40°C to 105°C

1-MHz I: -40°C to 85°C

f_CAL(1MHz) DCOCTL = CALDCO_1MHZ, 1.8 V to 3.6 V 0.95 1 1.05 MHz

calibration value T: -40°C to 105°C

Gating time: 5 ms

8-MHz I: -40°C to 85°C

fCAL(8MHz) DCOCTL = CALDCO_8MHZ, 1.8 V to 3.6 V 7.6 8 8.4 MHz

calibration value Gating time: 5 ms T: -40°C to 105°C BCSCTL1 = CALBC1_12MHZ,

12-MHz I: -40°C to 85°C

fCAL(12MHz) calibration value DCOCTL = CALDCO_12MHZ, T: -40°C to 105°C 2.2 V to 3.6 V 11.4 12 12.6 MHz Gating time: 5 ms

16-MHz I: -40°C to 85°C

f_CAL(16MHz) DCOCTL = CALDCO_16MHZ, 3 V to 3.6 V 15 16 17 MHz

calibration value T: -40°C to 105°C

Gating time: 2 ms

(25)

T – Temperature – °C_A 0.97

0.98 0.99 1.00 1.01 1.02 1.03

-50

Frequency–MHz

V_CC= 1.8 V

V_CC= 2.2 V V_CC= 3 V

V_CC= 3.6 V

-25 0 25 50 75 100

V_CC– Supply Voltage – V 0.97

0.98 0.99 1.00 1.01 1.02 1.03

1.5

Frequency–MHz T = 105°CA

2.0 2.5 3.0 3.5 4.0

T = 85°C_A T = 25°C_A

T = -40°C_A

Typical Characteristics - Calibrated 1-MHz DCO Frequency

CALIBRATED 1-MHz FREQUENCY CALIBRATED 1-MHz FREQUENCY

vs vs

TEMPERATURE SUPPLY VOLTAGE

(26)

DCO Frequency − MHz 0.10

1.00 10.00

0.10 1.00 10.00

DCO WakeTime−µs

RSELx = 0 to 11

RSELx = 12 to 15

Wake-Up From Lower-Power Modes (LPM3/4)

BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ 2

BCSCTL1 = CALBC1_8MHZ, 2.2 V/3 V 1.5

DCOCTL = CALDCO_8MHZ DCO clock wake-up time

t_DCO,LPM3/4 µs

from LPM3/4⁽¹⁾ BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ 1 BCSCTL1 = CALBC1_16MHZ,

3 V 1

DCOCTL = CALDCO_16MHZ

CPU wake-up time from 1 / fMCLK +

t_CPU,LPM3/4

LPM3/4⁽²⁾ tClock,LPM3/4

(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK).

(2) Parameter applicable only if DCOCLK is used for MCLK.

Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4

DCO WAKE-UP TIME FROM LPM3 vs

DCO FREQUENCY

Figure 13.

(27)

Crystal Oscillator LFXT1, Low-Frequency Mode

⁽¹⁾

LFXT1 oscillator crystal

f_LFXT1,LF XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V 32768 Hz

frequency, LF mode 0, 1 LFXT1 oscillator logic level

fLFXT1,LF,logic square wave input frequency, XTS = 0, LFXT1Sx = 3 1.8 V to 3.6 V 10000 32768 50000 Hz LF mode

XTS = 0, LFXT1Sx = 0,

f_LFXT1,LF= 32768 Hz, C_L,eff= 6 pF 500 Oscillation allowance for

OALF kΩ

LF crystals XTS = 0, LFXT1Sx = 0,

f_LFXT1,LF= 32768 Hz, C_L,eff= 12 pF 200

XTS = 0, XCAPx = 0 1

XTS = 0, XCAPx = 1 5.5

Integrated effective load

CL,eff pF

capacitance, LF mode⁽²⁾ XTS = 0, XCAPx = 2 8.5

XTS = 0, XCAPx = 3 11

XTS = 0, Measured at P2.0/ACLK,

Duty cycle, LF mode 2.2 V/3 V 30 50 70 %

fLFXT1,LF= 32768 Hz Oscillator fault frequency,

f_Fault,LF XTS = 0, LFXT1Sx = 3⁽⁴⁾ 2.2 V/3 V 10 10000 Hz

LF mode⁽³⁾

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

(a) Keep the trace between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter.

(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the crystal that is used.

(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(4) Measured with logic-level input frequency but also applies to operation with crystals.

(28)

Crystal Oscillator LFXT1, High-Frequency Mode

⁽¹⁾

f_LFXT1,HF0 XTS = 1, LFXT1Sx = 0 1.8 V to 3.6 V 0.4 1 MHz

frequency, HF mode 0 LFXT1 oscillator crystal

fLFXT1,HF1 frequency, HF mode 1 XTS = 1, LFXT1Sx = 1 1.8 V to 3.6 V 1 4 MHz

1.8 V to 3.6 V 2 10

fLFXT1,HF2 XTS = 1, LFXT1Sx = 2 2.2 V to 3.6 V 2 12 MHz

frequency, HF mode 2

3 V to 3.6 V 2 16

1.8 V to 3.6 V 0.4 10

LFXT1 oscillator logic-level

fLFXT1,HF,logic square-wave input XTS = 1, LFXT1Sx = 3 2.2 V to 3.6 V 0.4 12 MHz

frequency, HF mode 3 V to 3.6 V 0.4 16

XTS = 1, LFXT1Sx = 0, f_LFXT1,HF= 1 MHz, C_L,eff= 15 pF 2700 Oscillation allowance for HF

OAHF crystals (seeFigure 14and 800 Ω

fLFXT1,HF= 4 MHz, CL,eff= 15 pF Figure 15)

f_LFXT1,HF= 16 MHz, C_L,eff= 15 pF 300 Integrated effective load

CL,eff capacitance, HF mode⁽²⁾ XTS = 1⁽³⁾ 1 pF

40 50 60

fLFXT1,HF= 10 MHz

Duty cycle, HF mode 2.2 V/3 V %

40 50 60

fLFXT1,HF= 16 MHz

fFault,HF Oscillator fault frequency⁽⁴⁾ XTS = 1, LFXT1Sx = 3⁽⁵⁾ 2.2 V/3 V 30 300 kHz

(1) To improve EMI on the XT2 oscillator the following guidelines should be observed:

(a) Keep the trace between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter.

(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.

(3) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag.

(5) Measured with logic-level input frequency, but also applies to operation with crystals.

(29)

Crystal Frequency – MHz 10

100 1000 10000 100000

0.1

OscillationAllowance–W

LFXT1Sx = 1

LFXT1Sx = 3

1 10 100

LFXT1Sx = 2

0 100 200 300 400 500 600 700 800

0

Crystal Frequency – MHz

XTOscillator Supply Current–µA

LFXT1Sx = 1

LFXT1Sx = 2

LFXT1Sx = 3

4 8 12 16 20

Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)

OSCILLATION ALLOWANCE OSCILLATOR SUPPLY CURRENT

vs vs

CRYSTAL FREQUENCY CRYSTAL FREQUENCY

CL,eff= 15 pF, TA= 25°C CL,eff= 15 pF, TA= 25°C

(30)

Timer_A

Internal: SMCLK, ACLK 2.2 V 10

fTA Timer_A clock frequency External: TACLK, INCLK MHz

3 V 16

Duty cycle = 50%±10%

t_TA,cap Timer_A capture timing TA0, TA1, TA2 2.2 V/3 V 20 ns

Comparator_A+

⁽¹⁾

over recommended operating free-air temperature range (unless otherwise noted)

2.2 V 25 40

I_(DD) CAON = 1, CARSEL = 0, CAREF = 0 µA

3 V 45 60

2.2 V 30 50

CAON = 1, CARSEL = 0, CAREF = 1/2/3,

I(Refladder/RefDiode) µA

No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 3 V 45 71

Common-mode input

V(IC) voltage range CAON = 1 2.2 V/3 V 0 VCC- 1 V

(Voltage at 0.25 V_CC PCA0 = 1, CARSEL = 1, CAREF = 1,

V(Ref025) 2.2 V/3 V 0.23 0.24 0.25

node) / VCC No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 (Voltage at 0.5 V_CC PCA0 = 1, CARSEL = 1, CAREF = 2,

V_(Ref050) 2.2 V/3 V 0.47 0.48 0.5

node) / VCC No load at P2.3/CA0/TA1 and P2.4/CA1/TA2

PCA0 = 1, CARSEL = 1, CAREF = 3, 2.2 V 390 480 540

SeeFigure 19and

V_(RefVT) No load at P2.3/CA0/TA1 and P2.4/CA1/TA2, mV

Figure 20 TA= 85°C 3 V 400 490 550

V_(offset) Offset voltage⁽²⁾ 2.2 V/3 V -30 30 mV

V_hys Input hysteresis CAON = 1 2.2 V/3 V 0 0.7 1.4 mV

T_A= 25°C, Overdrive 10 mV, 2.2 V 80 165 300

Without filter: CAF = 0⁽³⁾ ns

3 V 70 120 240

(seeFigure 16andFigure 17) Response time

t_(response)

(low-high and high-low) TA= 25°C, Overdrive 10 mV, 2.2 V 1.4 1.9 2.8

With filter: CAF = 1⁽³⁾ µs

3 V 0.9 1.5 2.2

(seeFigure 16andFigure 17)

(1) The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y)specification.

(2) The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The two successive measurements are then summed together.

(3) Response time measured at P2.2/CAOUT.

(31)

_ +

CAON

0 1

V+ 0

1 CAF

Low-Pass Filter

τ ≈ 2.0 µs

To Internal Modules

Set CAIFG Flag CAOUT V−

V_CC 1 0 V

0

Overdrive V_CAOUT

t_(response) V+

V−

400 mV

CASHORT

1

Comparator_A+

CASHORT = 1

CA1 CA0

VIN +

−

I_OUT= 10µA

Figure 16. Comparator_A+ Module Block Diagram

Figure 17. Overdrive Definition

Figure 18. Comparator_A+ Short Resistance Test Condition

(32)

T – Free-Air Temperature – °C_A 400

450 500 550 600 650

V–Reference Volts–mV(REFVT)

-45 -25 -5 15 35 55 75 95

V_CC= 3 V

Typical

V_CC= 2.2 V

Typical

T – Free-Air Temperature – °C_A 400

450 500 550 600 650

V–Reference Volts–mV(REFVT)

-45 -25 -5 15 35 55 75 95

V /VIN CC– Normalized Input Voltage – V/V 1

10 100

0

Short Resistance–kW

V_CC= 1.8 V

V_CC= 3.6 V V_CC= 2.2 V

V_CC= 3 V

0.2 0.4 0.6 0.8 1.0

Typical Characteristics - Comparator_A+

V(RefVT) V(RefVT)

vs vs

TEMPERATURE TEMPERATURE

VCC= 2.2 V VCC= 2.2 V

SHORT RESISTANCE vs

V_IN/V_CC

Figure 21.