Adaptive Linear Predictor FIR Filter Based on the Cyclone V FPGA With HPS to Reduce Narrow

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 63, NO. 3, JUNE 2016 1455

Adaptive Linear Predictor FIR Filter Based on the Cyclone V FPGA With HPS to Reduce Narrow

Band RFI in Radio Detection of Cosmic Rays

Zbigniew Szadkowski, Member, IEEE, and Dariusz Głas

Abstract—We are presenting a new approach to a filtering of radio frequency interference (RFI) in the Auger Engineering Radio Array (AERA), which studies the electromagnetic part of the extensive air showers. Radio stations can observe radio sig- nals caused by coherent emissions due to geomagnetic radiation and charge excess processes. AERA observes the frequency band from 30 to 80 MHz. This range is highly contaminated by human- made RFI. In order to improve the signal to noise ratio RFI filters are used in AERA to suppress this contamination. The fil- ter has already been tested with real AERA radio stations in the Argentinean Pampas with very successful results. The linear equa- tions were solved either in the virtual soft-core NIOS^®processor (implemented in the FPGA chip as a net of logic elements) or in the external Voipac PXA270M ARM processor. The NIOS^®processor is relatively slow (50 MHz internal clock), and the calculations per- formed in an external processor consume a significant amount of time for data exchange between the FPGA and the processor. Tests showed very good efficiency of the RFI suppression for station- ary (long-term) contaminations. However, we observed short-time contaminations, which could not be suppressed either by the IIR- notch filter or by the FIR filter based on the linear predictions. For the LP FIR filter, the refresh time of the filter coefficients was too long and the filter did not keep up with the changes in the con- tamination structure, mainly due to a long calculation time in a slow processors. We propose to use the Cyclone^®V SE chip with an embedded micro-controller operating with a 925 MHz inter- nal clock to significantly reduce the refreshment time of the FIR coefficients. First results in the laboratory are very promising.

Index Terms—Auger engineering radio array, FIR, FPGA, HPS, pierre auger observatory, trigger.

I. INTRODUCTION

M

AJOR progress on the powerful digital signal processing techniques has allowed for a very efficient radio detection of cosmic-ray air showers in many experiments such as LOPES [1], CODALEMA [2] or the Auger Engineering Radio Array (AERA) [3], which is situated within the Pierre Auger Observatory [4].

High-energy cosmic rays develop in the Earth’s atmosphere air showers avalanches of secondary particles. A detailed

Manuscript received June 29, 2015; revised February 26, 2016; accepted March 09, 2016. Date of current version June 21, 2016. This work was supported in part by the Polish National Center for Research and Development under NCBiR Grant No. ERA/NET/ASPERA/02/11 and in part by the National Science Centre (Poland) under NCN Grant No. 2013/08/M/ST9/00322.

The authors are with the University of Łód´z, Department of Physics and Applied Informatics, Faculty of High-Energy Astrophysics, 90-236 Łód´z, Poland (e-mail: zszadkow@kfd2.phys.uni.lodz.pl).

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNS.2016.2542070

registration and investigation of their features allows for an understanding of the properties of the primary cosmic ray, such as its energy, its incoming direction, and its composition.

Avalanches of charged particles propagating in the Earth’s magnetic field are deflected and generate a synchrotron radiation. The radio emission from air showers is strongly correlated with the local Earth magnetic field [5]. Askaryan [6], [7] predicted that we should expect an emission component related to the time-variation of the negative net charge excess in air showers. Both [1] and [2] confirmed these effects.

An efficient investigation of the ultra-high energy cosmic rays needs a very large aperture detection system, which could operate with a nearly 100% duty cycle.

The radio technique is especially appropriate for detecting ultra-high energy cosmic rays (UHECRs) in a large-scale array due to its high angular resolution, its sensitivity to the lon- gitudinal air-shower evolution, a nearly 100% duty cycle and relatively low costs. AERA installed already more than hundred radio stations [8]. Next generation (AERA++) considers 360 stations spread on300−400 km² with irregular 700–1000 m grid. Each radio station is equipped with a dual-polarized log- arithmic periodic dipole antenna (LPDA) optimized for receiv- ing radio signals in a frequency band centered at 56 MHz and with a bandwidth of about 50 MHz. These antennas were aligned such that one polarization direction pointed in the geomagnetic north-south (NS) direction with an accuracy of 0.6^◦, while the other polarization direction pointed in an east-west (EW) direction. For each polarization direction, NS and EW, the Pierre Auger Collaboration used analog electronics to amplify the signals and to suppress strong lines in the HF band below 25 MHz and in the FM-broadcast band above 90 MHz. A 12- bit digitizer running at a sampling frequency of 200 MHz was used for the analog-to-digital conversion of the signals. This electronic system was completed with a GPS, trigger and DAQ system [9].

For AERA, two types of shower triggers are performed:

externally by particle detectors as well as a radio self-trigger on the basis of a signal shape. The latter approach is much cheaper in realizing, but it is much more sophisticated and requires a good-quality signal.

II. LINEARPREDICTOR

The first kind of filter used by AERA was the median one, based on the Fast Fourier Transform (FFT) technique [10]. The second one, which is currently in use, is the infinite impulse

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1456 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 63, NO. 3, JUNE 2016

Fig. 1. Fourier spectra for ADC signals and filtered by the LP FIR filter withD = 128, for long-term data (256 events ×∼31ms 8s). The radio station LS009 and NS polarization is located in a relatively quiet region and only four mono-carriers are observed (graph a). These RFI are very efficiently suppressed by the LP FIR filter (graph b). However, for the noisy region e.g. radio station LS122 with EW polarization with significant contribution of non-stationary RFI (graph c), the RFI suppression supported by the external Voipac PXA270M ARM processor of even a single mono-carrier is almost negligible (graph d). The RFI in station LS124 (graph e), located also in a relatively noisy region, is suppressed much more efficiently (graph f) mainly due to coefficients calculated in the internal NIOS^® processor much faster than by the external one. The analog section of the Front-End contains the band-pass analog filter with cut-off frequencies∼25–∼80 MHz.

However, we see in (graph e) the RFI contribution in a frequency range∼20 MHz. This is probably due to a relatively soft slope of the frequency characteristics of the analog input filters.

response (IIR) notch filter [11], [12]. The proposed new filter is a finite impulse response (FIR) filter based on a linear prediction (LP). A periodic contamination hidden in a registered signal (digitized in the ADC) can be extracted and then subtracted to make the signal cleaner. The FIR filter requires a calculation ofn = 32, 64, or even 128 coefficients (which are dependent on a required speed or accuracy), by solving n linear equations with coefficients built from the covariance Toeplitz matrix. This matrix can be solved by the Levinson recursion, which is much faster than the Gauss procedure. Linear prediction is a mathematical operation where future values of a discrete time signal are estimated as a linear function of previous samples [13]. In the LP method, the covariances for 1024 ADC samples are calculated in the FPGA fast logic block.

Either the NIOS^® processor, or the external ARM-processor, solves the matrix of 32, 64 or 128 linear equations, and provides coefficients needed for the FIR filter. The calculated coefficients are then transferred to the fast logic block, updating appropriate registers. They are used as the FIR coefficients in the ADC data filtering. Finally, the predicted and delayed data (expected background) are subtracted from the ADC data to clean the signal from periodic contaminations (see Fig. 3).

Coefficients can be calculated by a virtual NIOS^® processor, and it takes 0.19 s for 64 stages of the filter. The LP filter has been tested for several variants of the parameters (32, 48, 64 stages; 1, 32, 128 delay length; 14, 18 bit coefficients). Laboratory tests show very high efficiency for the filter when data is contaminated by a narrow-band RFI. The power

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SZADKOWSKI AND GŁAS: ADAPTIVE LINEAR PREDICTOR FIR FILTER BASED ON THE CYCLONE V FPGA WITH HPS 1457

Fig. 2. Simulated Fourier spectra for original (left) and filtered (right) non-stationary RFI. Average non-stationary RFI length is 50 ms and refreshment time of 64 coefficients is 10 ms. The 1st row shows the suppression for 5 mono-carriers spread on a wide frequency range with non-stationary RFI at around 20 MHz.

The suppression efficiency of mono-carriers as well as for RFI with duration time longer than the refreshment time is really high. Although, we observe an artificial amplification for a non-stationary RFI with a factor of∼2 (graph b). If mono-carriers are concentrated in a more narrow frequency range (graph c), their suppression is still high, however,RFInsis suppressed much worse (graph d) with also artificial amplifications.

Fig. 3. The data flow of the FIR filter based on the LP method.

consumption of the 32-stage LP FIR filter is on a similar level as the IIR filter: nevertheless, the LP FIR is superior due to its adaptive features.

The noise floor at the Pampas is rather sophisticated. In the “quiet” regions only RFI related to several mono-carriers appears (Fig. 1(a)). These type of RFI can be suppressed by the LP FIR filter with a high efficiency (Fig. 1(b)). However, in the “noisy” regions with a substantial contribution of non- stationary RFI (Fig. 1(c)), the efficiency of the LP FIR filter dramatically decreases (Fig. 1(d)). This RFI was filtered by the FIR filter with coefficients calculated in the external Voipac PXA270M ARM processor. ADC samples were transferred from the FPGA to the external processor and after calculation corresponding LP coefficients were transferred back to the FPGA. This very time-consuming process significantly enlarge the refreshment time which causes that the suppression factor is almost negligible (Fig. 1(d)). However, if the coefficients

were calculated in the internal NIOS^®processor, contaminated data from the radio station LS124NS (Fig. 1(e)) were cleaned with much higher efficiency (Fig. 1(f)) both for stationary RFI (from∼45 to ∼80 MHz) and non-stationary RFI around 22 MHz.

A change of the calculation process from an external to an internal FPGA processor (even soft-core NIOS^®) improves the suppression factor. This is a main motivation to use the HPS with 925 MHz clock to reduce calculation time on a level of magnitude. The non-stationary RFI corresponds to relatively short contaminations, which duration time is shorter than a calculation time needed to refresh the LP coefficients.

III. SIMULATIONS OF THESUPPRESSION FORVARIOUS

AVERAGELENGTHS OFNON-STATIONARYRFI We attempted to improve the non-stationary RFI suppression by shorting a refreshment rate of the FIR coefficients.

This means that the coefficients have to be calculated much faster. The NIOS^® processor can work with a maximum 100 MHz (recommended 50 MHz). The new approach is to use a Cyclone^® V SoC HPS with an embedded ARM processor.

This processor works with a 925 MHz clock, and calculations can be shortened on a level of magnitude. Our first estimations and laboratory measurements show that the refreshment time of the coefficients is small enough to recognize and suppress non-stationary RFI. Nevertheless, this approach has to be confirmed in real Pampas condition in the field. The Pierre Auger

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Fig. 4.FFT for original and filtered non-stationary RFI. Average non-stationary RFI length is 20 ms (1st row) and 10 ms (2nd row), respectively. The refreshment time of 64 coefficients is 10 ms (Conditions for the HPS). We can see that theFFT remains without changes only for a processing time of

∼10 ms.

Collaboration plans to equip the next radio stations with new Front-End Boards based on Cyclone^®V HPS SoC FPGAs. The prototype design is in progress and we expect the field test of the new AERA board by the end of 2016.

We first simulated a response of the LP filter for short-time contaminations. As we expected, if the calculation time is much shorter than the contamination duration, the suppression efficiency is high (Fig. 2). For the refreshmenttime = 10 ms and 50 ms non-stationary RFI by an existence of several mono- carriers a total suppression is very efficient independently of the width of frequency range, where mono-carriers appear (Fig. 2(a) - for wide and Fig. 2(b) for narrower frequency ranges). In both cases mono-carriers are suppressed almost to negligible levels. Non-stationary RFI remain not touched for the refreshment time of 10 ms, but is suppressed efficiently.

In addition, we observe in the spectra some jumps related to transient states.

The suppression factor highly depends on the ratio of refreshment time of the LP coefficients to the average length of RFI.

Fig. 4 show that for relatively short RFI (20 ns) withTref = 10 ms (Fig. 4(b)) the suppression efficiency of non-stationary RFI starts being problematic and for 10 ms non-stationary RFI are not suppressed at all (Fig. 4(d)).

The next important factor is the probability that data used for recalculation of the LP filter coefficients was taken when the RFI occurs. If this does not happen, the LP coefficients are calculated using noise data and it is not expected that the LP filter can suppress the RFI in this case. If the refreshment time of the LP filter is longer than the length of the RFI, the suppression depends on the similarity of the following RFI. In

order to estimate the efficiency of the filter we calculated the suppression factor defined as follows:

SF =

F F Ti,original−

F F Ti,f iltered

F F Ti,original

(1)

In this case, when the RFI length is longer than the LP refreshment time, we observe significant suppression of SF = 89%

(Fig. 2).

If the calculation time is shorter than the RFI interval, we can see that the suppression is negligible during the calculation only. When the new LP coefficients are reloaded, the contribution of the RFI in a signal dramatically decreases (Fig. 2(b) and (d)).

Generally, the suppression strongly depends on when the calculation of the new LP coefficients starts. If the calculation starts just after the new RFI appears we can suppress about half of the amplitude. In the worst case scenario, the calculation may stop just before the new RFI appears. In this case, the next calculation will be made in the middle of the RFI and the suppression begins at the end or just after the RFI disappears.

Nevertheless, simulations confirm perfectly that shorter refreshment time of the LP FIR coefficients significantly improves an suppression efficiency of short-time contaminations. For 100 ms RFI SF= 72%, and for 50 ms RFI SF = 59%.

Our goal is to implement the LP FIR filter into the Cyclone V SE SoC FPGA with LP coefficients calculated by internal HPS to significantly reduce the refreshment time and to suppress short-term non-stationary RFI in real Pampas conditions.

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(a)

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Fig. 5. Example of non-stationary RFI for two selected frequencies 33.2 MHz (NS polarization) and 35.2 MHz (EW polarization).

IV. NON-STATIONARYRFI

Radio stations send the data of all candidate pulses to the Central Data Acquisition System (CDAS), which determine whether a multiplet of three of more stations has been triggered within the same short time interval. The CDAS reconstructs online a direction of a shower and allows a rejection of well- known sources of transient RFI. The data rate is on a level of 10 Hz. All these events are stored to disk for later offline analysis of cosmic-ray events identification.

The trigger rate of the self-triggered stations should be higher than 10 Hz to provide a sufficient rate for the CDAS responsi- ble also for a rejection of uncorrelated pulses. The maximum trigger rate of the stations is∼700 Hz and the typical rate for the stations to work properly lies around 200 Hz.

Real data from Pampas shown in Fig. 1 correspond to a period of ∼8 seconds. 256 series registered in ∼8 s give an average interval between events on a level of∼30 milliseconds.

This is a higher rate than a standard one, however, it allows a more precise estimation of a duration of non-stationary RFI.

Fig. 5 shows an evolution of RFI in∼4 s interval for the non- stationary RFI region for NS and EW polarizations. We can see that usually RFI appears in single or two events, rarely in 3 or more. It means that a duration of the non-stationary RFI is usually less than 60 ms.

Fig. 6 shows duration intervals of non-stationary RFI as a function of thresholdThr = 20, 10 or 5:

F F T > T hr∗N

k=1F F Ti

/N

N is a number of considered events.

Fig. 6. Example of non-stationary RFI for two selected frequencies 33.2 MHz (NS polarization) and 35.2 MHz (EW polarization).

For ∼10⁵ FFT bins only less than 1% give peaks above our thresholds. These peaks correspond to non-stationary RFI.

Depending on a threshold a duration of this type of RFI does not exceed several time intervals between registered events i.e.

30 - 150 ms.

The linear equations were solved either in the external Voipac PXA270M ARM processor or in the virtual soft-core NIOS^® processor (implemented in the FPGA chip as a net of logic elements). External processor consumes a lot of time for a data exchange with the FPGA. The refreshment time is on a level of seconds. The NIOS^® processor exchanges data internally in the FPGA, however, it operates (according to the Altera^® recommendation) with 50 MHz clock and it is relatively slow.

The refreshment time in the NIOS^® mode is on a level hundreds milliseconds (depending on the FIR length in the linear predictor).

The HPS providing FIR coefficients much faster allows a much more efficient RFI suppression also for short-term contaminations (non-stationary RFI).

FIR coefficients in the linear predictor were calculated by the external ARM processor on the internal NIOS soft-core one.

The minimal refreshment time available in these techniques was 190 ms. This is in a good agreement with cleaned data. We do not observe longer RFI contaminations, because they were suppressed by the LP filter.

V. HPS PROGRAMMING ANDTESTING

So far, the virtual processor NIOS^® could work with the maximum frequency of 100 MHz (for the calculations we used 80 MHz). The refreshment time of the coefficients calculated by the NIOS^®was about 190 ms (for 32 stages). The Cyclone^® V SoC HPS with an embedded ARM processor could work with a maximum frequency of 925 MHz. This means that the calculation time of the coefficients could be decreased about ten times. For programming and testing the HPS, we used the DS-5 platform. This platform contains all the tools necessary to connect and program the Cyclone^®V SoC HPS with an embedded ARM processor. The communication between the computer with DS-5 software and the development kit was provided by the USB cable. The default clock frequency used for testing the software was 400 MHz, but we decided to increase it to

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800 MHz in order to fully use the possibilities of the ARM processor. Increasing the clock frequency was a relatively easy step. Instead of changing the phase locked loop (PLL) settings (which required a complex handling of registers), we changed the PLL input clock, which is possible with one command.

The testing consists of calling the Levinson procedure 1000 times for 64 and 32 stages, respectively. The Levinson procedure solves the covariance matrix and produces a vector of coefficients as an output. The time for solving the covariance matrix highly depends on the filter length. The calculation time of the coefficients for 64 length LP filter in Cyclone^® V SoC HPS is about 19 ms and it depends on the data in the covariance matrix. If we change the filter length from 64 to 32 coefficients, the covariance matrix reduces its size from64 × 64 to 32 × 32 and the calculation time decreases four times to about 5 ms. However, the reduction of the number of coefficients also reduces the efficiency of the LP filter.

The communication between the HPS and FPGA is provided by two bridges: HPS-to-FPGA bridge and lightweight HPS-to- FPGA bridge. The HPS-to-FPGA bridge can send a maximum of 128 bits of data in a single clock cycle. The lightweight bridge can send only 32 bits of data. The coefficients are 12 bit data, which means that we can send up to 10 coefficients in a single clock cycle. The 8 bits that are left can be used for con- trol flags. The transmission of the 64 coefficients will be done in seven clock cycles, and 32 coefficients can be sent in four clock cycles. The virtual NIOS^® processor allowed us to send one coefficient per clock cycle.

VI. FPGA OPTIMIZATION

A continuous stream of data is assumed to be contaminated with narrow-band RFI and is represented by the sampless(i).

It is our goal to design an FIR filter with coefficientsai such that the narrow-band RFI in the resulting signale(i) is reduced as much as possible. The filter can be described as

e(i) = s(i) −

p n=1

ans(i − D − n) (2)

wherep is the number of coefficients and D is the delay-line.

The delay-lineD implies that there is a gap between the samples that are used for the prediction and the sample that is to be predicted. This delay-line is necessary to allow transient signals to pass through the filter unaltered.

The method described here first makes a prediction ˆs(i) of the sampless(i) with

ˆs(i) =

p n=1

ans(i − D − n) (3)

Subsequently the prediction is subtracted from the original signals(i) such that

e(i) = s(i) − ˆs(i) (4)

We are now left with the task of finding the optimal solution of the predictor coefficientsai. An effective way of obtaining

TABLE I

CALCULATIONTIMES INMILLI-SECONDS OFCOVARIANCECOEFFICIENTS RRANRBIN THEDOUBLELOOP FROMEQS. 11AND12

Fig. 7. A structure of the fast logic block supporting the covariance calculations. The Altera’s^® procedure supporting a multiplication of two variables with a simultaneous summation of partial products.

the best solution is to assume Gaussianity and minimize the estimated mean square error,

E = 1 N

N−1 i=0

e²(i) = 1 N

N−1

i=0

{s(i) − ˆs(i)}² (5)

whereN is a number large enough to obtain convergence of this estimate. In our present caseN should be at least a thousand samples or more. In order to obtain the best values ofai, the mean square error is minimized by the requirement that,

∂

∂aiE = 0 (6)

which yields the following system ofp equations,

N−1

i=0

s(i − D − n)s(i) =

N−1

i=0

p m=1

ams(i − n)s(i − m) (7)

We can now define the covariance r^∗(n) =

N−1 i=0

s(i − n − D)s(i) (8)

R(m, n) ≡ r(|m − n|) =

N−1

i=0

s(i − n)s(i − m) (9)

and rewrite equation (7) in vectorial form as,

r^∗= Ra (10)

where the vector r^∗ and the symmetric Toeplitz (diagonal- constant) matrixR are known from Eqs. (8) and (9). The special properties of the matrixR allow it to be represented by the p- dimensional vectorr. Solving for a yields the coefficients of the filter from equation (2).

For a single procedure, the time is only 5 and 19 ms, respectively, which is much shorter than what is required for the NIOS^®-based calculations.

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Fig. 8. A structure of the fast logic block calculating covariances. The Altera^®procedures supporting a multiplication of two variables with a simultaneous summation of partial products. An implementation of 32 or 64 above FPGA fast logic blocks in parallel dramatically reduces calculation time especially in comparison to calculations performed in the NIOS^®soft-core processor.

By re-indexing Eq. (7), we get the following double loop in the C code:

for(i = 0; i < p; i + +){

for(j = 0; j < N − p − D; j + +){

rr[i]+ = s[j + i]∗s[j]; (11)

rb[i]+ = s[j + i]∗s[j + p + D]; }} (12) In the previous approaches [14]–[16] covariances were calculated by the NIOS^® or ARM processors. This process is relatively time consuming.

However, Table I shows that for the HPS support calculation times are relatively very long. For considered parametersp = 32 or 64 and N = 1024, they reach an unacceptable level of more than hundreds of milli seconds, much longer than solving the procedure itself.

When time is an important factor, the covariance coefficients can be calculated directly in the fast FPGA logic. Terms s[j] are a direct output of the ADC. Index j denotes that ADC data is performed N-p-D times according the second loop in Eqs. (11) and (12). Termss[j + p + D] correspond to ADC data delayed in a pipelined chain of a (p + D) length. The first loop (indexed by i) iterates rr[i] and rb[i] coefficients.

Originally, in development kits equipped in the Cyclone^® III and Cyclone^® IV FPGAs, we used internal Altera’s^® IP function - ALTMULT_ACCUM(MAC) (Fig. 7). However, Cyclone^®V family is not longer supported by this function, so we had to replace this IP function by custom block as shown in Fig. 8. In 5CEFA9F31I7 Cyclone^® V FPGA the registered performance of the block calculating rr and rb coefficients is bigger than 200 MHz. ADC samples are taken from the stream in the fly. No additional storage is needed.

Fig. 8 shows a single chain (a single value of i index) calculating either r or rb. Terms s[j + i] correspond to ADC data delayed on i clock cycles in a pipelined shift registers.

RAM-based shift registers are a separate structure and utilize additional 46 M10 K memory blocks.

Forp = 32, for example, we need 64 chains of those shown in Fig. 8. The multiplier procedure from Fig. 8 utilizes only a single18 × 194 embedded DSP block. For 5CSEA6 family of Cyclone V SoC with 22418 × 19 DSP multipliers the resources allow an implementation of this structure for 64 stages of the FIR filter.

The FPGA communicates with the HPS by a 128-bit bridge.

64 outputs (for only FIR 32 stages) of 38-bit accumulators have to be multiplexed. To a 128-bit FPGA-HPS bridge, only three accumulator outputs can be connected simultaneously.

The entire covariance coefficients transfer requires 22 steps.

However, a single step takes only a few micro-seconds. The total procedure of calculation and data transfer to the HPS to create the Toeplitz matrix is less than100 µs.

The inverse process is a transfer of 32 or 64 14-bit coefficients from the HPS to the FIR filter that also requires less than 100 µs. It means that a refreshment time can be reached on the level of 5 ms for a 32-stage filter.

VII. CONCLUSIONS

The linear predictor is an adaptive filter, but it has a limita- tion in its adaptation. The result of the simulations show that the LP filter works fine if the refreshment time of the coefficients is lower than the time of changes in the signal. Using the ARM processor allow us to suppress a 20 ms length non-stationary RFI. However, the reduction of the refreshment time of the LP filter also gives us a better chance of not increasing RFIs, which are shorter than 20 ms, by increasing the chance that the LP filter will be refreshed using data from the gap between the RFIs.

AERA plans to upgrade the Front-End Boards for the installa- tion of the next hundreds of radio stations. Cyclone^®V SE with the ARM processor is a very good candidate for an upgrade.

The LP filter based on the HPS is a natural solution for future systems based on self-trigger concepts, where the cleaning of signals is a crucial topic.

ACKNOWLEDGMENT

The authors would like to thank the Pierre Auger Collaboration for providing the infrastructure for tests and measurements.

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