Description
The CXA1898Q is an IC developed for analog signal processing in tape recorders. Processing for both the recording and playback systems is achieved on one chip.
Features
• Recording equalizer Gp and Fp can be adjusted externally.
• Recording mute function
• AGC (Automatic Gain Control)
• Comparator for AMS (Automatic Music Sensor)
• Recording/playback equalizer amplifier with 1.7 times speed switching
• 11-bit serial data interface
Absolute Maximum Ratings
• Supply voltage VCC 12 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation PD 735 mW
Operating Conditions
Supply voltage VCC 6.5 to 10.0 V
Structure
Bipolar silicon monolithic IC
Applications
All analog signal processing in the cassette decks of tape recorders and compact music centers
(Applicable to Sankyo Seiki mfg. Co., Ltd.
YK47R-KF202 R/P head or equivalent)
Recording/Playback Equalizer Amplifier
48 pin QFP (Plastic)
Block Diagram and Pin Configuration (Top View)
IREF
PB OUT2
PB FB22
PB FB12
PB INB2
PB INA2
PB INA1
PB INB1
PB FB11
PB FB21
PB OUT1
AMS GAIN
CLK
LATCH
M2
M1
PL2
PL1
BPB
BPA
PB MUTE
SPEED
R MUTE2
R MUTE1
MUTE
IREF PBEQ CTLRECEQ CTLRECEQ SHIFT REGISTERS
GND
AGC RECEQ
10k 40k 10k
40k
AGC GAIN 19.5dB
GND
GND
GND 210k
210k
70k
70k 70k
70k
210k
210k
AMS
IL T D L L 1 1 1 1 I
GND
GND
GND GND GND GND GND GND GND GND GND GND
D11 D11 D9 D7 D6 D5 D4 D3 D2 D1
D8 D10 D9 DECK A/B
D10 SPEED D9 B EQ AGC OFF A EQ
D8
SPEED B EQ
AGC GAIN 19.5dB
RFC VCC VG GND AGC TC AGC IN2 REC IN2 AGC OUT2 REC OUT2 D GND XRESET DATA
GND
GND GND
GND GND
GND GND 40 39 38 37
41
42
43
44
45
46
47
48
2 3 4 5 6 7 8 9 10 11 12
1
25 26 27 28 29 30
36 35 34 33 32 31
14 15 16 17 18 19 20 21 22 23 24
13
LATCHES
Pin Description Pin
No.
6 31
Symbol DC
voltage I/O Equivalent circuit Description
AGC IN1
AGC IN2 4.0V I
AGC signal input.
Input resistance changes between 47kΩand 3kΩ I/O
resistance
50kΩ
VCC
147 3k
47k
× 4
VCC
GND VGS
6 31
7 30
REC IN1
REC IN2 4.0V I Recording equalizer
input.
50kΩ
8 29
AGC OUT1
AGC OUT2 4.0V O
AGC output pin.
AGC is applied at –11dBm or more.
147Ω
9 28
REC OUT1
REC OUT2 4.0V O Recording equalizer
output.
147Ω
7 30
VCC
147
50k
VCC
GND VGS
23k
1.8k
VGS GND
8 29
VCC
147 500 18.8k
× 4
VCC
GND
VGS
GND GND
× 2
47.8k
5.3k 500
VGS
9 28
VCC
147
40k 500
× 10
VCC
GND
× 3
500
× 2 5p
10 A EQ — I
A deck equalizer switch.
Low: 120µs EQ High: 70µs EQ
— 10
VCC
147
GND GND
VCC
11 B EQ
2.5V (when open)
I
B deck equalizer switch.
Low: Normal Tape, 120µs EQ High: CrO2Tape, 70µs
EQ
Medium: Metal Tape, 70µs EQ 53kΩ
12 RMUTE1 I — I
Recording mute ON/OFF switch.
Low: Mute OFF High: Mute ON
∗Fader function is realized by the external time constant circuit.
Connects Pin 13 (RMUTE1).
—
13 14
R MUTE1 R MUTE2
Output for recording mute ON/OFF switch control signal.
Outputs D11 from Pin
VCC
147 50k
VCC
GND
GND 5k
5k 11
× 2
12 VCC
147
GND
GND
VCC
20k
× 2 20k
2.7V 50µA
VDD
Pin
No. Symbol DC
voltage I/O I/O Equivalent circuit Description
resistance
17 BPA
5.0V (when reset) (when Pin 25 (DATA) is set to high)
O
Outputs D6 from Pin 25 (DATA).
18 BPB Outputs D5 from
Pin 25 (DATA).
19 PL1 Outputs D4 from
Pin 25 (DATA).
20 PL2 Outputs D3 from
Pin 25 (DATA).
21 M1 Outputs D2 from
Pin 25 (DATA).
22 M2 Outputs D1 from
Pin 25 (DATA).
—
× 4 VDD
GND
GND
VCC
× 4 10k
20k 17
18 19 20 21 22
23 LATCH
26 XRESET
— I
Serial data interface latch input.
Serial data interface reset input.
Low: Reset.
At this time serial data outputs (Pins 13 to 22) are all open (high).
—
32 AGC TC 0.0V —
Connects a resistor and capacitor for
determining AGC attack/recovery time constants.
—
2k
GND
VCC
10.5k 25µA
23 26
GND
100µA
5p 24k
× 4
24 25
4k
GND
VCC
10.5k 25µA
GND
100µA
× 4 24k
32 VCC
GND GND
VCC
× 2 200
100k 500
500
× 2
147 × 2
× 4 200 5k
24 CLK
25 DATA
— I
Serial data interface clock input.
Serial data interface serial data input.
— Pin
No. Symbol DC
voltage I/O I/O Equivalent circuit Description
resistance
34 VG 4.0V —
Signal reference voltage. Connects a capacitor for ripple rejection.
60kΩ 34
VCC
147
45k 30k
× 4 VCC
GND GND
500
500
× 2 30k
× 2
To each VSG
35 VCC 8.0V — — Power supply.
36 RFC 8.0V —
Connects a resistor and capacitor for obtaining stable voltage with power supply ripple rejected.
—
38 47
PB OUT2
PB OUT1 2.8V O Playback equalizer
output.
147Ω
35 VCC
36 VCC
147
VCC
GND
× 3
× 250
× 3
To each RFS
38 47
VCC
147 5k
VCC
GND
× 2
× 3
× 2
× 6 500
500 5p
Pin
No. Symbol DC
voltage I/O I/O Equivalent circuit Description
resistance
39 46
PB FB22
PB FB21 2.8V —
Connects a capacitor for determining playback equalizer time constants, such as 120µs and 70µs.
— 39
46 VCC
147 × 3
GND
2k 2k
GND GND
× 4 7k × 3
× 4 RFS
40 45
PB INB2 PB INA2 PB INA1 PB INB1
1.4V — Playback equalizer
negative feedback.
105kΩ
41 42 43 44
0.0V I Playback equalizer
input.
70kΩ
48 AMS GAIN 3.5V —
Connects a resistor for determining AMS signal detection level and a capacitor for determining HPF cut-off frequency.
—
40 41
42 43 44
45 70k
5p VCC
147
GND
VCC
GND
× 6 VCC
GND
1k 1k210k
210k 147 VCC
RFS
× 2 10k
10k
× 6
48 VCC
147
GND
VCC
GND 100k 10µ
PB FB12 PB FB11
Note)
The resistance of open collector outputs (Pins 2 and 13 to 22) can be also connected to VCC. Pin
No. Symbol DC
voltage I/O I/O Equivalent circuit Description
resistance
Electrical Characteristics
(Ta = 25°C, VCC= 8.0V, VDD= 5.0V, refer to Electrical Characteristics Measurement Circuit) Item
Operating voltage Current consumption
AGC
Measurement conditions Min. Typ. Max. Unit
AMSPlaybackequalizeramplifierblock
VCC
NORM–NS, VCC= 8V, No signal Pin 32 external R300kΩ/ /C47µF f = 1kHz, Vin = –25dBm
Pin 32 external R300kΩ/ /C47µF f = 1kHz, Vin = –15dBm
Pin 32 external R300kΩ/ /C47µF f = 1kHz, Vin = 0dBm
Pin 32 external R300kΩ/ /C 47µF f = 1kHz, Vin = –25dBm
Pin 48 external R9.1kΩ, C0.015µF Pin 1 external R100kΩ/ /C0.1µF f = 5kHz, 0dB = –21dBm
(at PBEQ reference output level) f = 315Hz, Vin = –70dBm
Reference for frequency response f = 2.7kHz, Vin = –58.5dBm at 120µs–NS, 315Hz f = 4.5kHz, Vin = –53.8dBm at 120µs–NS, 315Hz f = 5.3kHz, Vin = –52.5dBm at 120µs–NS, 315Hz f = 9.1kHz, Vin = –47.8dBm at 120µs–NS, 315Hz 120µs–NS, RL= 2.7kΩ f = 1kHz, THD + N = 1%
120µs–NS, RL= 2.7kΩ f = 1kHz, Vin = –56.4dBm 120µs–NS, Rg = 2.2kΩ
"A" weighting filter 120µs–NS, Rg = 70kΩ AGC ON output level
AGC ON channel balance
AGC ON distortion AGC OFF output level
No signal detection threshold level
120µs–NS
frequency response 120µs–NS
frequency response 70µs–NS
frequency response 120µs–HS
frequency response 70µs–HS
frequency response Signal handling Total harmonic distortion S/N ratio
Output offset voltage
6.5 13.5 –13.0
–2.0
—
–7.5
–11.5
–23.0
–0.1
–0.1
1.8
2.1
–10.0
—
55.0 2.4
8.0 18.0 –11.0
0.0
0.3
–5.5
–8.2
–21.0
1.3
1.7
3.0
3.6
–6.0
0.3
62.0 2.7
10.0 22.5 –9.0
2.0
1.5
–3.5
—
–19.0
2.9
2.9
4.8
5.1
—
0.7
— 3.2
V mA dBm
dB
%
dBm
dB
dBm
dB
dBm
%
dB V
dB –26.4
— 1.5
1.1
7.3
16.4
4.2
9.7
18.2
5.7
8.9
15.8
1.7
12.3
19.5
6.0
16.0
22.5
7.3
14.0
19.7 –27.9
–10.0 0.0
–0.2
5.7
13.4
3.0
8.4
15.8
4.5
7.4
13.7
0.2
10.5
16.7
4.9
14.2
20.0
6.1
12.4
17.4 NORM–NS, 315Hz, input level at which
reference output can be obtained NORM–NS, 315Hz
NORM-NS, 315Hz, Output difference 1ch–2ch for –27.9dBm input
f = 3kHz
at NORM–NS, 315Hz, reference output –20dB f = 8kHz
at NORM–NS, 315Hz, reference output –20dB f = 12kHz
at NORM–NS, 315Hz, reference output –20dB f = 3kHz
at NORM–NS, 315Hz, reference output –20dB f = 8kHz
at NORM–NS, 315Hz, reference output –20dB f = 12kHz
at NORM–NS, 315Hz, reference output –20dB f = 3kHz
at NORM–NS, 315Hz, reference output –20dB f = 8kHz
at NORM–NS, 315Hz, reference output –20dB f = 12kHz
at NORM–NS, 315Hz, reference output –20dB f = 5kHz
at NORM–NS, 315Hz, reference output -20dB f = 15kHz
at NORM–NS, 315Hz, reference output –20dB f = 20kHz
at NORM–NS, 315Hz, reference output –20dB f = 5kHz
at NORM–NS, 315Hz, reference output –20dB f = 15kHz
at NORM–NS, 315Hz, reference output –20dB f = 20kHz
at NORM–NS, 315Hz, reference output –20dB f = 5kHz
at NORM–NS, 315Hz, reference output –20dB f = 15kHz
at NORM–NS, 315Hz, reference output –20dB f = 20kHz
at NORM–NS, 315Hz, reference output –20dB
–29.4
— –1.5
–1.3
3.7
10.4
1.8
6.7
13.2
3.3
5.9
11.3
–0.7
8.3
13.5
3.6
12.0
17.0
4.9
10.5
14.7 Reference input level
Reference output level Channel balance NORM–NS
frequency response NORM–NS
frequency response NORM–NS
frequency response CrO2–NS
frequency response CrO2–NS
frequency response CrO2–NS
frequency response METAL–NS
frequency response METAL–NS
frequency response METAL–NS
frequency response NORM–HS
frequency response NORM–HS
frequency response NORM–HS
frequency response CrO2–HS
frequency response CrO2–HS
frequency response CrO2–HS
frequency response METAL–HS
frequency response METAL–HS
frequency response METAL–HS
frequency response
Recordingequalizeramplifierblock
Item Measurement conditions Min. Typ. Max. Unit
dBm
Item
Recordingequalizeramplifierblock
Measurement conditions Min. Typ. Max. Unit NORM–NS, RL2.7kΩ
f = 1kHz, THD = 1%
NORM–NS, RL2.7kΩ f = 1kHz, 0dB
NORM–NS, Rg = 5.1kΩ
"A" weighting filter NORM–NS
NORM–NS, f = 1kHz 8dB, Pin 12 = 3.5V NORM–NS, f = 1kHz 8dB, Pin 12 = 2.0V A-EQ (Pin 10) A-EQ (Pin 10) B-EQ (Pin 11) B-EQ (Pin 11) B-EQ (Pin 11) RMUTE1-I (Pin 12) RMUTE1-I (Pin 12) Signal handling
Total harmonic distortion
S/N ratio
Output offset voltage Mute characteristics 1
Mute characteristics 2
8.0
—
57.0 3.6
—
–8.3 0.0 2.5 0.0 2.2 4.2 0.0 3.5
8.8
0.2
60.6 4.0 –100
–7.0
—
—
—
—
—
—
—
—
0.5
— 4.4 –80
–4.3 0.5 VCC
0.5 2.8 VCC
0.5 VCC
dB
%
dB V
Control voltage low level 1 Control voltage high level 1 Control voltage low level 2 Control voltage medium level 1 Control voltage high level 2 Control voltage low level 3 Control voltage high level 3
Note) NORM–NS : NORMAL TAPE–NORMAL SPEED NORM–HS : NORMAL TAPE–HIGH SPEED CrO2–NS : CrO2TAPE–NORMAL SPEED CrO2–HS : CrO2TAPE–HIGH SPEED
METAL–NS : METAL TAPE–NORMAL SPEED METAL–HS : METAL TAPE–HIGH SPEED 120µs–NS : EQ = 120µs–NORMAL SPEED 120µs–HS : EQ = 120µs–HIGH SPEED 70µs–NS : EQ = 70µs–NORMAL SPEED 70µs–HS : EQ = 70µs–HIGH SPEED
dB
V
Item
11-bitserialdatainterfaceblock
Measurement conditions Min. Typ. Max. Unit
VIL (LATCH/CLK/DATA/XRESET) (Pins 23, 24, 25, 26)
VIH(LATCH/CLK/DATA/XRESET) (Pins 23, 24, 25, 26)
VOL, IOL= 2mA (max) (Pins 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
IOZ Leak current which flows to the output pin when Ioz output is open; applied voltage is 10V.
(1) fCK
(2)
t
WC(3)
t
WR(4)
t
SDK(DATA →CLK)(5)
t
HCD(CLK →DATA)(6)
t
WD(7)
t
SLD(LATCH →DATA)(8)
t
HCL(CLK →LATCH)(9)
t
HLC(LATCH →CLK) Low level inputvoltage
High level input voltage
Low level output voltage
High level output off- leak current
Maximum clock frequency Minimum clock pulse width
Minimum reset pulse width
Minimum data setup time
Minimum data hold time
Minimum data pulse width
Minimum latch setup time
Minimum latch hold time
Minimum clock hold time
0.0
3.5
0.0
—
500
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.5
VDD
0.5
1.0
— 1.0
1.0
1.0
1.0
2.0
1.0
1.0
1.0
Note) • VDDis CPU supply voltage 5.0V.
• The maximum value for VDDis Pin 35 (VCC) voltage.
• For high level output off leak current, VCCis 10.0V.
µs V
µA
kHz
Timing Chart for 11-bit Serial Data Interface
tWC
tWC
tWD
tHCD
tSDK
1.5V 3.5V
D1 D2
1.5V 3.5V
1.5V
tSLD
3.5V
3.5V tHCL
D10 D11
tHLC
CLK
DATA
LATCH
CLK
DATA
AMS F IL
AMS O UT
AMS G ND
FP C AL
GP C AL
AGC IN 1
REC I N1
AGC OU T1
REC O UT 1
A EQ B EQ RMUT E1 I
CXA1898Q 1415161718
1920
21
22
23
24 13 234567891011121
RFC V CC
VG GND
AGC TC
AGC IN 2
REC I N2
AGC OU T2
REC O UT 2
D GN D
XRESET DAT
252627282930363534313233 A 37 38 39 40 41 42 43 44 45 46 47 48
IREF PB OUT2 PB FB22 PB FB12 PB INB2 PB INA2 PB INA1 PB INB1 PB FB11 PB FB21 PB OUT1 AMS GAIN
10k 0.1µ 10k 10k 0.1µ
0.1µ
2.2µ
4.7µ
0.47µ
0.47µ 2.7k
10k 5.1k
5.1k 0.1µ
S7F S12D
S20
27k
27k
100k
4.2V2.0V2.5V3.5V5.0V0.5V
S39
100 S18B S22A S22B 10k 100
S16 10k
10k S14B S25
S26 S24
S23 S27
S28A REC M UT E
S28B ON OFF MET AL
CrO 2
NORM B EQ
A EQ 120µs
70µs
S18A 47k 390k
0.1µ0.47µ
S7D S11
2.2k377k
0.1µ 0.47µ
S7C S10
2.2k377k
0.1µ 0.47µ S7B S92.2k377k 0.1µ 0.47µ
S7A S82.2k377k 10047µ 9.1k2.2µ2.7kS12B 0.015µ
0.018µ
100 S14A
10047µ
0.018µ
2.2µ2.7kS12A
12k
0.1µ S12C
10µ 1k
0.1µ 10µ 10µ 47µ
300k 5.1k 2.7k
0.47µ 0.47µ 4.7µ 2.2µ
5.1k S7E
0.1µ 10k
S19 S17A
47k 390k
8.0V
S15 10k
S13B 10k
S13A 100
S17B 100
S21A 100 S21B
10k XRESET
DAT A
CLK LATCH S3810k 2k
100k 0.1µ
S3710k 2k S3610k 2k S3510k 2k S3410k 2k S3310k 2k S3210k 2k S3110k 2k S3010k 2k S2910k 2k DC OUTPUTGND
GND
S501 S502 S503 S504 S505
AC OUTPUT
100k
BUF 30dB AMP "A" Weighting Filter Audio (22.2Hz-22.2kHz) Filter 1kHz Band Pass Filter (20dB)
TL072 GND600
ATT –6dB
S1BS1A
ATT –9dB
S3BS3A
ATT –17dB
S6BS6A
ATT –29dB
S4BS4A
ATT –40dB
S2BS2A AC INPUT CLK LATCH M2 M1 PL2 PL1 BPB BPA PB MUTE SPEED R MUTE2 R MUTE1
Application Circuit
IREF
PB OUT2
PB FB22
PB FB12
PB INB2
PB INA2
PB INA1
PB INB1
PB FB11
PB FB21
PB OUT1
AMS GAIN
CLK
LATCH
M2
M1
PL2
PL1
BPB
BPA
PB MUTE
SPEED
R MUTE2
R MUTE1
MUTE
IREF PBEQ CTLRECEQ CTLRECEQ LATCHES
47k
47k
47k
47k
47k
47k
47k
47k
47k 47k 47k
GND 47k
SHIFT REGISTERS
GND
AGC RECEQ
10k
40k
10k
40k
AGC GAIN 19.5dB
GND
GND
GND 210k
210k
70k
70k
70k
70k
210k 210k
AMS
AMS FIL AMS OUT AMS GND FP CAL GP CAL AGC IN1 REC IN1 AGC OUT1 REC OUT1 A EQ B EQ RMUTE1 I
GND
GND
GND GND GND GND GND GND GND GND GND GND
D11 D11 D9 D7 D6 D5 D4 D3 D2 D1
D8 D10 D9 DECK A/B D10 SPEED D9 B EQ A EQ AGC OFF D8
SPEED B EQ
AGC GAIN 19.5dB
RFC VCC VG GND AGC TC AGC IN2 REC IN2 AGC OUT2 REC OUT2 D GND XRESET DATA
DECK-A PB-HEAD BIas OSC
REC PB
GND
REC PB
GND
10k 12mH
820p 180p
150p GND
10k
12mH 820p
180p 150p GND
R/P-HEAD DECK-B
12k
10k 2.2µ
0.018µ 47µ 100 GND
GND
GND
47µ 100 GND
0.018µ
10k 2.2µ GND
1k 0.1µ
0.1µ 100k
100k
27k 27k 0.47µ 0.1µ 4.7µ
10k 2.2µ
0.1µ
10k GND
GND
GND GND
VDD or VCC 1k
0.47µ 2.7k 0.1µ
4.7µ 10k
2.2µ 100µ
GND
100k GND GND VDD
2.2µ 2.2meg
47µ GND GND VCC GND
GND
GND
GND GND
GND GND
GND GND 40 39 38 37
41
42
43
44
45
46
47
48
14 15 16 17 18 19 20 21 22 23 24
13
2 3 4 5 6 7 8 9 10 11 12
1
26 25 28 27
29
36 35 34 33 32 31 30
GND GND
2.7k
10µ 47µ
VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC
1. System control mode
Playback and recording equalizer
(1) Playback equalizer (120µs/70µs)
DECK-AB (serial data D10 (Pin 25))
A-EQ (Pin 10) B-EQ (Pin 11)
L H L M/H
L
H
120µs (A DECK)
70µs
(A DECK) According to A EQ control 120µs
(B DECK)
70µs (B DECK) According to B EQ control
(2) Recording equalizer (Normal, CrO2, Metal) B-EQ (Pin 11)
REC MODE
L Normal (Type I)
M CrO2(Type II)
H Metal (Type IV)
(3) Recording mute (Pin 12) Rec Mute
Control voltage
Mute OFF GND ≤VCL ≤0.5V
–7dB attenuation 2.0V
Mute ON 3.5V ≤VCH ≤VCC
Muting is achieved by varying the recording equalizer amplifier gain just like an electronic volume, according to the DC voltage applied to the REC MUTE pin.
(4) FP CAL (Pin 4)
The standard resistor setting is 27kΩ, but when resistance value is larger, fo (Hz) is low, and when resistance value is smaller, fo (Hz) is high.
(5) Gp Cal (Pin 5)
The standard resistor setting is 27kΩ, but when resistance value is larger, gain is larger, and when resistance value is smaller, gain is smaller.
2. 11-bit serial data interface
• The DATA signal is taken in at the rising edge of the CLK signal.
• The DATA signal is taken in to the internal shift register when the LATCH signal is low.
(Outputs (Pins 13 to 22) hold the previous value while the LATCH signal is low.)
• The internal shift register data is latched and output in parallel at the rising edge of the LATCH signal.
(Internal shift register data is loaded while the LATCH signal is high.)
• The CLK signal of 11th bit should fall after the LATCH signal rises.
• Reset is done when the XRESET pin is low. (asynchronous method) Outputs (Pins 13 to 22) are all high (open) during reset.
D1 D2 D3 D4 D5 D6 D7
M2 M1 PL2 PL1 BPB BPA PB-MUTE
Pin 22 Pin 21 Pin 20 Pin 19 Pin 18 Pin 17 Pin 16
L L L L L L L
H (OPEN) H (OPEN) H (OPEN) H (OPEN) H (OPEN) H (OPEN) H (OPEN) Output pin Input set at low Input set at high
Output DATA
(Pin 25) Control signal
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
CLk (Pin 24)
DATA (Pin 25)
LATCH (Pin 23)
XRESET (Pin 26)
D11
• Make sure that RFC is 5.5V or more and XRESET is 1.5V or less, and 1µs or more when resetting by applying CR time constant to XRESET (Pin 26) and turning power ON.
• When resetting with CPU or other when power is turned ON
• Examples of AGC control during timer recording
(1) Resets when power is turned ON (AGC function operates).
(2) AGC is turned OFF after AGC inputs (Pins 6 and 31) rise.
(External capacitor charge of AGC TC is discharged.) (3) AGC is turned ON and timer recording begins.
1µs or more 1.5V or less
5.5V or more RFC (Pin 36)
XRESET (Pin 26)
1µs or more
5.0V 5.5V or more
RFC (Pin 36)
XRESET (Pin 26)
0V
Circuit Diagram for 11-bit Serial Data Transfer Evaluation Tool
D12
H L
D13
H L
D14
H L
D15
H L 6 8
9 10 11 13 12 14
2 3 4 5 6 7
1
XQ2
Q2
XPR2
CLK2
D2
XR2
VDD VSS
XQ1
Q1
XPR1
CLK1
D1XR1
74HC74 (1)
8 9 10 11 13 12 14
2 3 4 5 6 7
1
XQ2
Q2
XPR2
CLK2
D2
XR2
VDD VSSXQ1Q1
XPR1
CLK1
D1XR1
74HC74 (2)
8 9 10 11 12 13 14
2 3 4 5 6 7
1
XQ2
Q2
XPR2
CLK2
D2
XR2
VDD VSSXQ1Q1
XPR1
CLK1
D1XR1
74HC74 (3)
8 9 10 11 12 13 14
2 3 4 5 6 7
1
XQ2
Q2
XPR2
CLK2
D2
XR2
VDD VSSXQ1Q1
XPR1
CLK1
D1XR1
74HC74 (4)
8 9 10 11 12 13 14
2 3 4 5 6 7
1
Y3
A3
B3
Y4
A4
B4
VDD VSSY2B2A2Y1B1
A1
74HC00
8 9 10 11 12 13 14
2 3 4 5 6 7
1
Y3
A3
B3
Y4
A4
B4
VDD VSSY2B2A2Y1B1
A1
74HC08 (2) 8
9 10 11 12 13 14
2 3 4 5 6 7
1
Y3
A3
B3
Y4
A4
B4
VDD VSSY2B2A2Y1B1
A1
74HC08 (1) 8
9 10 11 12 13 14
2 3 4 5 6 7
1
Y4
A4
Y5
A5
Y6
A6
VDD VSSY3A3Y2A2Y1
A1
74HC04 R5 10k
ONOFF START 3
ON OFF
RESET
C50.1µ
4
C120.1µ
C90.1µ
C80.1µ
R3 10k
R6 10k
C40.1µ
15
C140.1µ C130.1µ C200.1µ
5
13
100R16
12
1
14
8 9 10 11 12 13 14
2 3 4 5 6 7
1
Q1
CLOCK
RESET
Q9
Q8
Q10
Q11
VDD VSSQ2Q3Q4Q7Q5Q6
Q12
74HC4040 15
16
8 9 10 11 12 13 14
2 3 4 5 6 7
1
XA2
B2
XRES2
XQ2
Q1
C1
R/C1
VDD VSS
R/C2
C2
Q2XQ1
XRES1
B1XA1
74HC123 15 16
8 9 10 11 12 13 14
2 3 4 5 6 7
1
B0
A0
B1
A1
A2
B2
A3
VDD VSS
A<BOUT
A=BOUT
A>BOUT
A>BIN
A=BIN
A<BIN
B3
74HC85 15 16
9 10 11 12 13
14 XLOA
ENA 1
RESET
Q9
Q8
Q10
Q11
VDD
15
16 14 13 12 11 10 9
QH
SERIAIN
A
B
C
D
CLK2
VDD
15 16
C190.1µ C180.1µ 1248
H L
H L
H L
H L
D4
H L
D5
H L
D6
H L
D7
H L
9 10 11 12 13
14D C B A IN SERIA QH
CLK2
VDD
15 16
C170.1µ
C110.1µ C100.1µ 8
17
68k R17 11
C16 4.7µ C15 1000P R13 2.2k
1
R7220 R8220 R15220R14220
R1110k R1210k 9
16
R11M R2
220 C6
15P C7
15P
4.4MHz 220 R4 220 R9 2
LATCH
CLK
DATA
XRESET
DGND
5V
SW GND
GND 100µ/25V
C21
15 16
19
100 R18
DGND EXCLK
C30.1µ C20.1µC0.1µ
EXCLK250kHz 500kHz 100 R19
100 R10
DummyD1D2D3D4D5D6D7D8D9D10D11
2µs
COUNT RESET
CLOCK STOP (14) RESET/CLOCK STOP and COUNT RESET (15) DATA HC165 (16) CLOCK (17) = (8) (18) (19) LATCH(13)(12)(11) HC123(10) A = B, H(9)
(8) CLK GATE CONT.
(7) S/L
(6) = (4)
(5)
(4)
(3) START PULSE
(2) CLK
(1) CLK
3. AMS
(1) AMS output logic
AMS OUT (Pin 2) is an open collector output pin. When a 2.2kΩresistor is connected to VDD: Low : approximately 0.5V (IOL= 2mA (max.))
High : VDD
Fig. 1 shows the AMS block diagram.
Fig. 1 AMS Block Diagram
Fig. 2 shows the frequency response of the signal output from HPF.
Detection status AMS OUT (Pin 2)
Signal detection L
No signal detection H
2 3
1 48
PB OUT1
PB OUT2
20k20k
SA
LPF DET
25kHz
100k
GND VDD VDD VDD GND
AMS GND AMS OUT
AMS FIL
C1R1 R2 C2 R3
HPF
AMS GAIN Inside IC
fC
G
GAIN (dB)
(2) AMS level setting
The AMS level is set by adjusting HPF gain and cut-off frequency with the external resistor and capacitor at Pin 48.
G and fc in Fig. 2 are obtained from the following formula.
G = 20log (1 + 100k/R) [dB] – (1) fc = 1/ (2 • π• C • R) [Hz]
Full-wave rectifier is applied for the signal at DET.
Signal detection time is set by the time constant of Pin 1 external resistor and capacitor.
DET signal detection level:
= –7.5dBm (typ.)
= playback equalizer reference output level + AMS level + HPF gain – (2) Playback equalizer reference output level of –21dBm is 0dB.
Ex.)
To set AMS level at –25dB, determine and set the constant for Pin 48 external resistor.
(Calculate assuming PBOUT1 = PBOUT2) First, get the required HPF gain from formula (2).
–7.5dBm = –21dBm + (–25dB) + HPF gain, so HPF gain = 38.5dB.
Next, get Pin 48 external resistance from formula (1).
38.5dB = 20log (1 + 100k/R), so R ≈1.2kΩ,
and external resistance is 1.2kΩ.
Quiescent current consumption vs. Supply voltage
VCC-Supply voltage (V) 25
24 23 22 21 20 19 18 17 16 15
ICC-Quiescent current consumption (mA)
6 7 8 9 10 11
Example of Representative Characteristics
PB IN PB FB1 PB FB2 PB OUT
Playback equalizer frequency response 65
60 55 50 45 40 35 30 25
GAIN (dB)
120µs – NS 120µs – HS 70µs – NS 70µs – HS
M VCC = 8V
0.018µ
2.2k0.47µ 47µ
100 2.2µ
Recording equalizer frequency response
Frequency (Hz) 30
28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 –2
Output response (dB)
20 50 100 200 500 1k 2k 5k 10k 20k 50k VCC = 8V
0dB = NORM – NS, 315Hz, –30dBm (Tape) (Speed) NORM–
CrO2–
METAL–
NS NS NS
30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0
–220 50 100 200 500 1k 2k 5k 10k 20k 50k VCC = 8V
0dB = NORM – NS, 315Hz, –30dBm (Tape) (Speed) NORM–
CrO2–
METAL–
HS HS HS
Recording equalizer frequency response
Frequency (Hz)
Output response (dB)
RMUTE1 (Pin 1) voltage
0.0 1.0 2.0 3.0 4.0 5.0 6.0
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Output level vs. Mute voltage VCC = 8V
(Tape) (Speed) NORM– NS
0dB = reference output level +8dB f = 1kHz
Output level (dB)
AMS no signal detection level frequency response 30
25 20 15 10 5
VCC = 8V 120µs – NS AMS OUT 5V
0dB = –21dBm, 315Hz (playback equalizer reference output level)
A : Pin 48 for R9.1k, C0.015µ B : Pin 48 for R1k, C0.1µ
AMS GAIN AMS FIL AMS OUT
A : 0.015µ 9.1k B : 0.1µ 1k
AGC Output response 10
5
0
–5
–10
–15
Output level (dBm)
–35 –30 –25 –20 –15 –10 –5
Input level (dBm) AGC OFF
AGC ON VCC = 8V
1kHz
32
47µ 300k
AGC TC
Recording equalizer total harmonic distortion
–15 –10 –5 0 5 10
Output level (dB)
T.H.D. + Noise (%)
2.0
1.0
0.5
0.2
0.1
VCC = 8V Norm – NS mode RL = 2.7kΩ 1kHz
0dB = –10dBm
Playback equalizer total harmonic distortion
–30 –25 –20 –15 –10 –5
Output level (dB)
T.H.D. + Noise (%)
2.0
1.0
0.5
0.2
0.1
VCC = 8V 120µs – NS mode RL = 2.7kΩ 1kHz
Package Outline Unit: mm
SONY CODE EIAJ CODE JEDEC CODE
M
PACKAGE STRUCTURE
PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY
48PIN QFP (PLASTIC)
15.3 ± 0.4
12.0 – 0.1+ 0.4
0.8 0.3 – 0.1+ 0.15
± 0.12 13
24 25
36
37
48
1 12
2.2 – 0.15 + 0.35
0.9 ± 0.2
0.1 – 0.1+ 0.2
13.5
0.15 0.15 – 0.05 + 0.1
QFP-48P-L04
∗QFP048-P-1212-B
0.7g
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
