9316
National
Sem iconductor
9 3 1 6 /D M 9 3 1 6 S yn ch ro n o u s
General Description
T h e se synchronous, p re se tta b le co u n te rs fe a ture an in te r
nal ca rry lo o k-a h ea d fo r a p p lica tio n in high-speed co u n tin g designs. T h e 9 316 is a 4 -b it b inary co u n te r. T h e ca rry ou tpu t is d e co d e d by m eans o f a N O R gate, th u s pre ve n tin g spikes during th e norm al co u n tin g m ode o f o p e ra tio n . S yn ch ro n o u s o p e ration is p rovided by having all flip -flo p s clo ck e d sim ulta neously so th a t th e o u tpu ts ch a n g e co in cid e n t w ith each o th e r w h e n so in stru cte d by th e co u n t-e n a b le s inputs and internal gating. T h is m od e o f o p e ra tin g e lim in a tes th e ou tpu t cou n tin g sp ike s w h ich are no rm ally a sso cia te d w ith a syn ch ro n o u s (ripple clo ck) co u n te rs. A b u ffered c lo c k input trig gers th e fo u r flip -flo p s on th e rising (positive-going) e dge o f th e c lo ck input w a ve fo rm .
T h e se co u n te rs are fu lly p ro g ram m able; th a t is, th e o u tpu ts m ay be p re se t to e ith e r level. A s p re se tting is synchronous, se tting up a lo w level a t th e load in p u t d isa ble s th e co u n te r and ca u ses th e o u tp u ts to a g ree w ith th e setup d a ta a fte r th e n e xt c lo c k pulse re g a rd le ss o f th e le ve ls o f th e enable input. Low -to-high tra n sitio n s a t th e load in p u t are p e rfe ctly a cce pta b le re g a rd le ss o f th e lo g ic le ve ls on th e c lo c k o r en a ble inputs. T h e cle a r fu n ctio n is a syn ch ro n o us and a lo w level a t th e cle a r in p u t se ts o f th e flip -flo p o u tpu ts lo w re ga rdless o f th e levels o f clo ck, load, o r e n a ble inputs.
-B it C o u n te rs
T h e ca rry lo o k-a h ea d circuitry provides fo r ca s ca d in g co u n te rs fo r n -b it sy n ch ro n o u s a p p lica tio n s w ith o u t a d d itio n a l gating. In stru m e n ta l in a cco m p lish in g th is fu n ctio n are tw o co u n t-e n a b le in p u ts and a ripple carry o u tpu t. B oth co u n t- e n a ble in p u ts (P and T) m ust be high to co unt, and in p u t T is fe d -fo rw a rd to e n a ble th e ripple carry o utput. T h e rip ple c a r
ry o u tp u t th u s en a ble d w ill pro d u ce a high-level o u tp u t pulse w ith a d u ra tio n a p p ro xim a te ly equal to th e h igh-level p o rtio n o f th e Qa o utput. T h is high-level o ve rflo w rip ple ca rry pulse can be used to e n a ble su cce ssive ca sca d e d stages. High- to -lo w level tra n sitio n s a t th e enable P o r T in p u ts m ay o cc u r re g a rd le ss o f th e lo g ic level in th e clock.
Features
■ Internal lo o k-a h ea d fo r fa s t counting
■ C arry o u tp u t fo r n -b it ca sca d in g
■ S yn ch ro n o u s co u n tin g
■ Load co n tro l line
■ D io d e -cla m pe d in p u ts
■ T ypica l c lo c k fre q u e n c y 35 M Hz
■ P in-for-pin re p la ce m e n ts po p ula r 5 4 /7 4 c o u n te rs 5 4 1 6 A /7 4 1 6 A (binary)
■ A lte rn a te M ilita ry /A e ro s p a c e device (9316) is available.
C o n ta c t a N a tio n a l S em ico n d ucto r S ale s O ffic e /D is trib - u to r fo r sp e cifica tio n s.
Connection Diagram
D u a l-ln -L in e P ackag e
RIPPLE O UTPUTS
CARRY ---*--- > ENABLE
vcc o u t p u t Qa Qb Qc Qd t l o a d
O rd e r N u m b e r 9 3 1 6D M Q B , 93 1 6F M Q B , D M 9316J D M 9 3 1 6 W o r D M 9316N
S e e N S P ackag e N u m b e r J16A , N 16E o r W 1 6 A
Absolute Maximum Ratings (Note)
If M ilita ry /A e ro s p a c e s p e c ifie d d e v ic es a re req u ired , p lease c o n ta c t th e N ational S em ic o n d u c to r S ales O ffic e /D is trib u to rs fo r a v a ilability a nd s p e c ific atio n s .
S up p ly V oltage 7V
Input V olta g e 5.5V
O p e ra tin g Free A ir T e m pe ratu re R ange
M ilitary - 5 5 ° C to + 1 2 5 °C
C om m ercial 0°C to + 70°C
S to rag e Te m pe ratu re R ange - 65°C to + 1 50°C
N ote: The ‘‘Absolute Maximum Ratings” are those values beyond which the safety o f the device cannot be guaran
teed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics”
table are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table w ill define the conditions for actual device operation.
Recommended Operating Conditions
S ym b ol P a ra m e te r M ilitary C om m ercial U nits
Min Norn M ax Min Norn M ax
V e c S upply V oltage 4.5 5 5.5 4.75 5 5.25 V
V |H High Level Input V olta g e 2 2 V
V|L Low Level In p ut V oltage 0.8 0.8 V
•o h High Level O u tp u t C urrent - 0 . 8 - 0 . 8 m A
•OL Low Level O u tp u t C urrent 16 16 m A
fCLK C lock Fre q u e n cy (N ote 6) 0 25 0 25 M H z
tW Pulse W idth
(N ote 6)
C lock 25 25
ns
C lear 20 20
ts u S etup Tim e
(N o te 6) D ata 20 20
E nable P 20 20 ns
Load 25 25
C le a r 20 20
tH A ny H old Tim e (N o te s 1 & 6) 0 0 ns
Ta Free A ir O p e ra ting T e m pe ratu re - 5 5 125 0 70 °C
Electrical Characteristics
o ve r re co m m en d e d o p e ra tin g fre e air te m p e ra tu re range (unless o th erw ise n o ted)S ym b ol P a ra m e te r C ondition s M in T y p
(N o te 2) M ax U nits
V| Input C lam p V olta g e Vq c= M in, l| = —12 m A - 1 . 5 V
V oH H igh Level O u tp u t V oltage
V c c = M in, Iq h = M ax
V |l = M ax, V |h = M in 2.4 3.4 V
V 0 L Low Level O u tp u t V oltage
V c c = M in, Iq l = M ax
V |h = M in, V |l = M ax 0.2 0.4 V
•l Input C u rre n t @ M ax
Input V olta g e
V Cc = M ax, V| = 5.5V 1 m A
•lH High Level Input
C urrent
|>
IIoII o _> > C lock 80
E nable T 80 jwA
O th e r 40
•iL Low Level Input
C urrent < < - o II O oII $ C lock - 3 . 2
julA
E nable T - 3 . 2
O th e r - 1 . 6
•o s S h o rt C ircuit
O u tp u t C u rre n t V c c = M ax (N o te 3)
M IL - 2 0 - 5 7 m A
COM - 1 8 - 5 7
•CCH S upply C u rre n t w ith
O u tp u ts H igh V Cc = M ax (N o te 4)
M IL 59 85
m A
COM 59 94
•CCL S upply C u rre n t w ith
O u tputs Low V Cc = M ax
(N o te 5)
M IL 63 91 m A
COM 63 101
Note 1: The minimum HOLD time is as specified or as long as the CLOCK input takes to rise from 0.8V to 2V, whichever is longer.
Note 2: All typicals are at VCc = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time.
Note 4: (ecu is measured with the LOAD input high, then again with the LOAD input low, with all other inputs high and all outputs open.
Note 5: Iqcl is measured with the CLOCK input high, then again with the CLOCK input low, with all other inputs low and all outputs open.
Note 6: TA = 25°C and VCc = 5V.
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Switching Characteristics
a t v c c = 5V and Ta = 25°C (S ee S ectio n 1 fo r T e st W a v e fo rm s an d O u tp u t Load)S ym bol P a ra m e te r From (In p u t) Rl = 4 0 0 n ,C L = 15 pF
U nits
T o (O u tp u t) M in M ax
f MAX M axim um C lo ck Fre q u e n cy 25 M H z
tpLH P ro pa g a tio n D elay Tim e Low to H igh Level O u tp u t
C lo ck
to RC 27 ns
tp H L P ro pa g a tio n D elay T im e High to L o w Level O u tp u t
C lo ck
to R C 24 ns
tpLH P ro pa g a tio n D elay Tim e Low to H igh Level O u tp u t
C lo c k
to Q 20 ns
tp H L P ropagation D elay Tim e
H igh to L ow Level O u tp u t
C lo ck
to Q 23 ns
tpLH P ropagation D elay Tim e
Low to H igh Level O u tp u t
C lo ck
to Q 21 ns
*PHL P ro pa g a tio n D elay T im e H igh to L ow Level O u tp u t
C lo c k
to Q 25 ns
tpLH P ropagation D elay Tim e
L ow to H igh Level O u tp u t
E N T
to RC 15 ns
tp H L P ropagation D elay Tim e
H igh to L ow Level O u tp u t
E N T
to RC 16 ns
tp H L P ro pagation D elay Tim e
H igh to Low Level O u tp u t
C lear
to Q 36 ns
Logic Diagram
9316
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9316
9316
Timing Diagram
9 3 1 6 S yn ch ro n o u s B inary C o u n te rs T y p ic a l C lear, P re s e t, C o u n t and Inhibit S eq u e n c es
CLEAR J (ASYNCHRONOUS)
LOAD
f A
r -i
DATA ® r -
IN PU TS
c J i
i— — _ - — — _ — — — — — _ _ — U j
CLOCK ENABLE P
L n _ T j n j i J i j n j T j a n _ r i _ r L r
| l
ENABLE T 1 i
Qa
Qb I I 1
OUTPUTS
o c 1
O O I I I I LJI
1
RIPPLE CARRY _ i — i
OUTPUT 12 13 14 15 O 1 2
--- COUNT--- -- --- INHIBIT--- -- CLEAR PRESET
Sequence:
(1) Clear outputs to zero.
(2) Preset to binary twelve.
(3) Count to thirteen, fourteen, fifteen, zero, one, and two.
(4) Inhibit
TL/F/6606-3
Parameter Measurement Information
S w itc h in g T im e W a v e fo rm s
TL/F/6606-4 Note A: The input pulses are supplied by a generator having the following characteristics: PRR £ 1 MHz, duty cycle £ 50% , Zq u t ~ 50H, tr £ 10 ns, tf £ 10 ns.
Vary PRR to measure f^AX-
Note B: Outputs Qq and carry are tested at tn + ie for 9316/8316, where tn is the bit time when all outputs are low.
N o te C :V REF = 1.5V.
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Parameter Measurement Information
(C ontinued) S w itc h in g T im e W a v e fo rm sTL/F/6606-5 Note A: The input pulses are supplied by generators having the following characteristics: PRR £ 1 MHz, duty cycle £ 50%, Zq u t ~ 50ft, tr £ 10 ns, tf £ 10 ns.
Note B: Enable P and Enable T setup times are measured at tn + 16 tor 8316/9316.
Note C: VREF = 1.5V.
