MC14008B-2

4-Bit Full Adder

The MC14008B 4−bit full adder is constructed with MOS P−Channel and N−Channel enhancement mode devices in a single monolithic structure. This device consists of four full adders with fast internal look−ahead carry output. It is useful in binary addition and other arithmetic applications. The fast parallel carry output bit allows high−speed operation when used with other adders in a system.

Features

• Look−Ahead Carry Output

• Diode Protection on All Inputs

• All Outputs Buffered

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low−Power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature Range

• Pin−for−Pin Replacement for CD4008B

• This Device is Pb−Free and is RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to V_SS)

Symbol Parameter Value Unit

V_DD DC Supply Voltage Range − 0.5 to +18.0 V V_in, V_out Input or Output Voltage Range

(DC or Transient)

− 0.5 to V_DD + 0.5 V

I_in, I_out Input or Output Current (DC or Transient) per Pin

±10 mA

P_D Power Dissipation, per Package (Note 1)

500 mW

T_A Ambient Temperature Range − 55 to +125 °C T_stg Storage Temperature Range − 65 to +150 °C

T_L Lead Temperature (8−Second Soldering)

260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V_in and V_out should be constrained

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MARKING DIAGRAM SOIC−16 D SUFFIX CASE 751B

14008BG AWLYWW

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Indicator

See detailed ordering and shipping information in the package

ORDERING INFORMATION 1

16

13 14 15 16

9 10 11 12 5

4 3 2 1

8 7 6

S3 S4 C_out B4 V_DD

C_in S1 S2 B2

A3 B3 A4

V_SS A1 B1 A2

PIN ASSIGNMENT

BLOCK DIAGRAM

HIGH-SPEED

PARALLEL CARRY 14C_out

13S4

12S3

11S2

10S1 B4 15

A4 1

B3 2 A3 3

B2 4 A2 5

B1 6 A1 7 C_in 9

ADDER 4

ADDER 3

ADDER 2

ADDER 1

C4

C3

C2

V_DD = PIN 16 V_SS = PIN 8 TRUTH TABLE

(One Stage)

C_in B A C_out S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

ORDERING INFORMATION

Device Package Shipping^†

MC14008BDR2G SOIC−16

(Pb−Free)

2500 Units / Tape & Reel

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ELECTRICAL CHARACTERISTICS (Voltages Referenced to V_SS)

Characteristic Symbol V_DD Vdc

−55_C 25_C 125_C

Min Max Min Unit

Typ

(Note 2) Max Min Max

Output Voltage “0” Level V_in = V_DD or 0

V_in = 0 or V_DD “1” Level

V_OL 5.0

10 15

−

−

−

0.05 0.05 0.05

−

−

−

0 0 0

0.05 0.05 0.05

−

−

−

0.05 0.05 0.05

Vdc

V_OH 5.0

10 15

4.95 9.95 14.95

−

−

−

4.95 9.95 14.95

5.0 10 15

−

−

−

4.95 9.95 14.95

−

−

−

Vdc

Input Voltage “0” Level (V_O = 4.5 or 0.5 Vdc)

(V_O = 9.0 or 1.0 Vdc) (V_O = 13.5 or 1.5 Vdc)

(V_O = 0.5 or 4.5 Vdc) “1” Level (V_O = 1.0 or 9.0 Vdc)

(V_O = 1.5 or 13.5 Vdc)

V_IL

5.0 10 15

−

−

−

1.5 3.0 4.0

−

−

−

2.25 4.50 6.75

1.5 3.0 4.0

−

−

−

1.5 3.0 4.0

Vdc

V_IH 5.0 10 15

3.5 7.0 11

−

−

−

3.5 7.0 11

2.75 5.50 8.25

−

−

−

3.5 7.0 11

−

−

−

Vdc

Output Drive Current

(V_OH = 2.5 Vdc) Source (V_OH = 4.6 Vdc)

(V_OH = 9.5 Vdc) (V_OH = 13.5 Vdc)

(V_OL = 0.4 Vdc) Sink (V_OL = 0.5 Vdc)

(V_OL = 1.5 Vdc)

I_OH

5.0 5.0 10 15

–3.0 –0.64

–1.6 –4.2

−

−

−

−

–2.4 –0.51

−1.3

−3.4

–4.2 –0.88 –2.25

−8.8

−

−

−

−

–1.7

−0.36 –0.9

−2.4

−

−

−

−

mAdc

I_OL 5.0 10 15

0.64 1.6 4.2

−

−

−

0.51 1.3 3.4

0.88 2.25 8.8

−

−

−

0.36 0.9 2.4

−

−

−

mAdc

Input Current I_in 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc

Input Capacitance (V_in = 0)

C_in − − − − 5.0 7.5 − − pF

Quiescent Current (Per Package)

I_DD 5.0 10 15

−

−

−

5.0 10 20

−

−

−

0.005 0.010 0.015

5.0 10 20

−

−

−

150 300 600

mAdc

Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package)

(C_L = 50 pF on all outputs, all buffers switching)

I_T 5.0

10 15

I_T = (1.7 mA/kHz) f + I_DD I_T = (3.4 mA/kHz) f + I_DD I_T = (5.0 mA/kHz) f + I_DD

mAdc

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

I_T(C_L) = I_T(50 pF) + (C_L − 50) Vfk

where: I_T is in mA (per package), C_L in pF, V = (V_DD − V_SS) in volts, f in kHz is input frequency, and k = 0.005.

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SWITCHING CHARACTERISTICS (Note 5)(C_L = 50 pF, T_A = 25_C)

Characteristic Symbol

V_DD

Vdc Min

Typ

(Note 6) Max Unit

Output Rise and Fall Time

t_TLH, t_THL = (1.5 ns/pF) C_L + 25 ns t_TLH, t_THL = (0.75 ns/pF) C_L + 12.5 ns t_TLH, t_THL = (0.55 ns/pF) C_L + 9.5 ns

t_TLH,

t_THL 5.0

10 15

−

−

−

100 50 40

200 100 80

ns

Propagation Delay Time Sum in to Sum Out

t_PLH, t_PHL = (1.7 ns/pF) C_L + 315 ns t_PLH, t_PHL = (0.66 ns/pF) C_L + 127 ns t_PLH, t_PHL = (0.5 ns/pF) C_L + 90 ns Sum In to Carry Out

t_PLH, t_PHL = (1.7 ns/pF) C_L + 220 ns t_PLH, t_PHL = (0.66 ns/pF) C_L + 112 ns t_PLH, t_PHL = (0.5 ns/pF) C_L + 85 ns Carry In to Sum Out

t_PLH, t_PHL = (1.7 ns/pF) C_L + 290 ns t_PLH, t_PHL = (0.66 ns/pF) C_L + 122 ns t_PLH, t_PHL = (0.5 ns/pF) C_L + 90 ns Carry In to Carry Out

t_PLH, t_PHL = (1.7 ns/pF) C_L + 85 ns t_PLH, t_PHL = (0.66 ns/pF) C_L + 42 ns t_PLH, t_PHL = (0.5 ns/pF) C_L + 30 ns

t_PLH, t_PHL

5.0 10 15

5.0 10 15

5.0 10 15

5.0 10 15

−

−

−

−

−

−

−

−

−

−

−

−

400 160 115

305 145 110

375 155 115

170 75 55

800 320 230

610 290 220

750 310 230

340 150 110

ns

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

V_DD = -V_GS V_out

16 B4 A4 B3 A3 B2 A2 B1 A1 C_in

S4 S3

S2

S1

C_out

I_OH

8 V_SS

EXTERNAL POWER SUPPLY

EXTERNAL POWER SUPPLY

I_OL

V_DD = V_GS V_out

16 B4 A4 B3 A3 B2 A2 B1 A1 C_in

S4 S3

S2

S1

C_out 8 V_SS

Figure 3. Dynamic Power Dissipation Test Circuit and Waveform

20 ns 20 ns

V_in 90%

10%

V_DD V_SS

PULSE GENERATOR

V_DD

16 B4 A4 B3 A3 B2 A2 B1 A1 C_in

S4

S3 S2

S1

C_out

I_DD

8 V_SS C_L

C_L C_L

C_L C_L

500 mF

PULSE GENERATOR

V_DD

16 B4 A4 B3 A3 B2 A2 B1 A1 C_in

S4

S3 S2

S1

C_out

I_DD

8 V_SS C_L

C_L C_L

C_L C_L

20 ns 20 ns

C_in

V_DD V_SS V t_PLH t_PHL

90%50%

10%

Figure 5. Logic Diagram C_in

A1 B1 A2 B2 A3 B3 A4 B4

S1 S2 S3 S4 C_out

WORD A + B INPUTS

A1 B4 A1 B4 A1 B4 A1 B4

TYPICAL APPLICATION

PACKAGE DIMENSIONS

SOIC−16 CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING PLANE

F

M J

RX 45_ G

P8 PL

−B−

−A−

0.25 (0.010)M B ^S

−T−

D

K C

16 PL

B S

0.25 (0.010)M T A ^S

DIM MIN MAX MIN MAX INCHES MILLIMETERS

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

_ _ _ _

6.40

16X

0.58

16X1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH SOLDERING FOOTPRINT

16

8 9

8X

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