FQP13N50

(1)

13N50/ F Q PF13N50

QFET

^TM

FQP13N50/FQPF13N50

500V N-Channel MOSFET

General Description

These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology.

This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supply, power factor correction, electronic lamp ballast based on half bridge.

Features

• 12.5A, 500V, R_DS(on) = 0.43Ω @V_GS = 10 V

• Low gate charge ( typical 45 nC)

• Low Crss ( typical 25 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

Absolute Maximum Ratings

^TC = 25°C unless otherwise noted

* Drain current limited by maximum junction temperature.

Thermal Characteristics

Symbol Parameter FQP13N50 FQPF13N50 Units

V_DSS Drain-Source Voltage 500 V

I_D Drain Current - Continuous (T_C = 25°C) 12.5 12.5 * A

- Continuous (T_C = 100°C) 7.9 7.9 * A

I_DM Drain Current - Pulsed (Note 1) 50 50 * A

V_GSS Gate-Source Voltage ± 30 V

E_AS Single Pulsed Avalanche Energy ^{(Note 2)} 810 mJ

I_AR Avalanche Current (Note 1) 12.5 A

E_AR Repetitive Avalanche Energy (Note 1) 17 mJ

dv/dt Peak Diode Recovery dv/dt ^{(Note 3)} 4.5 V/ns

P_D Power Dissipation (T_C = 25°C) 170 56 W

- Derate above 25°C 1.35 0.45 W/°C

T_J, T_STG Operating and Storage Temperature Range -55 to +150 °C

T_L Maximum lead temperature for soldering purposes,

1/8" from case for 5 seconds 300 °C

Symbol Parameter FQP13N50 FQPF13N50 Units

R_θJC Thermal Resistance, Junction-to-Case 0.74 2.23 °C/W

R_θCS Thermal Resistance, Case-to-Sink 0.5 -- °C/W

TO-220

FQP Series

G DS TO-220F

FQPF Series GDS

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(2)

Rev. B, September 2002

13N50/ F Q PF13N50

Electrical Characteristics

^TC = 25°C unless otherwise noted

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 9.3mH, I_AS = 12.5A, V_DD = 50V, R_G = 25 Ω, Starting T_J = 25°C 3. I_SD ≤ 13.4A, di/dt ≤ 200A/µs, V_DD ≤ BV_DSS,Starting T_J = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

BV_DSS Drain-Source Breakdown Voltage V_GS = 0 V, I_D = 250 µA 500 -- -- V

∆BV_DSS / ∆T_J

Breakdown Voltage Temperature

Coefficient I_D = 250 µA, Referenced to 25°C -- 0.48 -- V/°C

I_DSS

Zero Gate Voltage Drain Current V_DS = 500 V, V_GS = 0 V -- -- 1 µA

V_DS = 400 V, T_C = 125°C -- -- 10 µA

I_GSSF Gate-Body Leakage Current, Forward V_GS = 30 V, V_DS = 0 V -- -- 100 nA I_GSSR Gate-Body Leakage Current, Reverse V_GS = -30 V, V_DS = 0 V -- -- -100 nA

On Characteristics

V_GS(th) Gate Threshold Voltage V_DS = V_GS, I_D = 250 µA 3.0 -- 5.0 V

R_DS(on) Static Drain-Source

On-Resistance V_GS = 10 V, I_D = 6.25 A -- 0.33 0.43 Ω g_FS Forward Transconductance V_DS = 50 V, I_D = 6.25 A -- 10 -- S

Dynamic Characteristics

C_iss Input Capacitance V_DS = 25 V, V_GS = 0 V, f = 1.0 MHz

-- 1800 2300 pF

C_oss Output Capacitance -- 245 320 pF

C_rss Reverse Transfer Capacitance -- 25 35 pF

Switching Characteristics

t_d(on) Turn-On Delay Time

V_DD = 250 V, I_D = 13.4 A, R_G = 25 Ω

-- 40 90 ns

t_r Turn-On Rise Time -- 140 290 ns

t_d(off) Turn-Off Delay Time -- 100 210 ns

t_f Turn-Off Fall Time -- 85 180 ns

Q_g Total Gate Charge V_DS = 400 V, I_D = 13.4 A, V_GS = 10 V

-- 45 60 nC

Q_gs Gate-Source Charge -- 11 -- nC

Q_gd Gate-Drain Charge -- 22 -- nC

Drain-Source Diode Characteristics and Maximum Ratings

I_S Maximum Continuous Drain-Source Diode Forward Current -- -- 12.5 A

I_SM Maximum Pulsed Drain-Source Diode Forward Current -- -- 50 A

V_SD Drain-Source Diode Forward Voltage V_GS = 0 V, I_S = 12.5 A -- -- 1.4 V t_rr Reverse Recovery Time V_GS = 0 V, I_S = 13.4 A,

dI_F / dt = 100 A/µs

-- 290 -- ns

Q_rr Reverse Recovery Charge -- 2.6 -- µC

(Note 4)

(Note 4, 5)

(Note 4)

(3)

13N50/ F Q PF13N50

0 5 10 15 20 25 30 35 40 45 50

0 2 4 6 8 10 12

V_DS = 250V V_DS = 100V

V_DS = 400V

※ Note : I_D = 13.4 A

VGS, Gate-Source Voltage [V]

Q_G, Total Gate Charge [nC]

10^-1 10⁰ 10¹

0 500 1000 1500 2000 2500 3000

3500 Ciss = Cgs + Cgd (Cds = shorted)

Coss = Cds + Cgd

Crss = Cgd

※ Notes : 1. VGS = 0 V 2. f = 1 MHz C_rss

C_oss C_iss

Capacitance [pF]

VDS, Drain-Source Voltage [V]

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

10^-1 10⁰ 10¹

150℃ 25℃

※ Notes : 1. VGS = 0V 2. 250μ s Pulse Test

IDR , Reverse Drain Current [A]

V_SD , Source-Drain Voltage [V]

0 10 20 30 40 50

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

V_GS = 20V V_GS = 10V

※ Note : T_J = 25℃

RDS(ON) [Ω], Drain-Source On-Resistance

I_D, Drain Current [A]

2 4 6 8 10

10^-1 10⁰ 10¹

※ Notes : 1. VDS = 50V 2. 250μ s Pulse Test -55℃

150℃

25℃

ID , Drain Current [A]

V_GS , Gate-Source Voltage [V]

10^-1 10⁰ 10¹

10⁰ 10¹

※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃

VGS

Top : 15 V 10 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V

ID , Drain Current [A]

V_DS , Drain-Source Voltage [V]

Typical Characteristics

Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage Variation vs. Source Current

and Temperature Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics

(4)

13N50/ F Q PF13N50

10⁰ 10¹ 10² 10³

10^-2 10^-1 10⁰ 10¹ 10²

10 µs

100 ms DC

10 ms 1 ms

100 µs Operation in This Area

is Limited by R DS(on)

※ Notes : 1. TC = 25 ^oC 2. TJ = 150 ^oC 3. Single Pulse

ID, Drain Current [A]

V_DS, Drain-Source Voltage [V]

25 50 75 100 125 150

0 3 6 9 12 15

T_C, Case Temperature [℃]

Figure 10. Maximum Drain Current vs. Case Temperature

10⁰ 10¹ 10² 10³

10^-1 10⁰ 10¹ 10²

10 µs

DC 10 ms

1 ms 100 µs Operation in This Area

is Limited by R DS(on)

※ Notes : 1. TC = 25 ^oC 2. TJ = 150 ^oC 3. Single Pulse

V_DS, Drain-Source Voltage [V]

-100 -50 0 50 100 150 200

0.0 0.5 1.0 1.5 2.0 2.5 3.0

※ Notes : 1. VGS = 10 V 2. ID = 6.7 A

RDS(ON), (Normalized) Drain-Source On-Resistance

T_J, Junction Temperature [^oC]

-100 -50 0 50 100 150 200

0.8 0.9 1.0 1.1 1.2

※ Notes : 1. V_GS = 0 V 2. I_D = 250 μ A

BVDSS, (Normalized) Drain-Source Breakdown Voltage

T_J, Junction Temperature [^oC]

Typical Characteristics

(Continued)

Figure 9-1. Maximum Safe Operating Area for FQP13N50

Figure 7. Breakdown Voltage Variation vs. Temperature

Figure 8. On-Resistance Variation vs. Temperature

Figure 9-2. Maximum Safe Operating Area for FQPF13N50

(5)

13N50/ F Q PF13N50

Typical Characteristics

(Continued)

1 0^{- 5} 1 0^{- 4} 1 0^{- 3} 1 0^{- 2} 1 0^{- 1} 1 0⁰ 1 0¹

1 0^{- 2} 1 0^{- 1} 1 0⁰

※ N o te s :

1 . ZθJ C( t ) = 0 . 7 4 ℃ / W M a x . 2 . D u t y F a c t o r , D = t₁/ t₂ 3 . TJ M - TC = PD M * ZθJ C( t )

s i n g le p u ls e D = 0 . 5

0 . 0 2 0 . 2

0 . 0 5 0 . 1

0 . 0 1 ZθJC(t), Thermal Response

t₁, S q u a r e W a v e P u ls e D u r a t io n [ s e c ]

Figure 11-1. Transient Thermal Response Curve for FQP13N50

t1

PDM

t₂

1 0^{- 5} 1 0^{- 4} 1 0^{- 3} 1 0^{- 2} 1 0^{- 1} 1 0⁰ 1 0¹

1 0^{- 2} 1 0^{- 1} 1 0⁰

※ N o te s :

1 . Z_θ_{J C}( t ) = 2 . 2 3 ℃ / W M a x . 2 . D u t y F a c t o r , D = t1/ t2

3 . TJ M - TC = PD M * ZθJ C( t )

s i n g l e p u ls e D = 0 . 5

0 . 0 2 0 . 2

0 . 0 5 0 . 1

0 . 0 1

ZθJC(t), Thermal Response

t₁, S q u a r e W a v e P u ls e D u r a t io n [ s e c ]

Figure 11. Transient Thermal Response Curve for FQPF13N50

t1

PDM

t₂

(6)

13N50/ F Q PF13N50

Gate Charge Test Circuit & Waveform

Resistive Switching Test Circuit & Waveforms

Unclamped Inductive Switching Test Circuit & Waveforms

Charge V

_GS

10V

Q

_g

Q

_gs

Q

_gd

3mA

V

_GS

DUT

V

_DS

300nF 50KΩ 200nF 12V

Same Type as DUT

Charge V

_GS

10V

Q

_g

Q

_gs

Q

_gd

3mA

V

_GS

DUT

V

_DS

300nF 50KΩ 200nF 12V

Same Type as DUT

V

_GS

V

_DS

10%

90%

t_d(on) t_r

t_on t_off

t_d(off) t_f

V

_DD

10V

V

_DS

R

_L

DUT R

_G

V

_GS

V

_GS

V

_DS

10%

90%

t_d(on) t_r

t_on t_off

t_d(off) t_f

V

_DD

10V

V

_DS

R

_L

DUT R

_G

V

_GS

E

_AS

= ---- L I

_AS²

2 1 --- BV

_DSS

- V

_DD

BV

_DSS

V

_DD

V

_DS

BV

_DSS

t _p

V

_DD

I

_AS

V

_DS

(t) I

_D

(t)

Time

10V DUT

R

_G

L

I

_D

t _p

E

_AS

= ---- L I

_AS²

2 E

_AS

= ---- 1 L I

_AS²

2 ---- 1

2 1 --- BV

_DSS

- V

_DD

BV

_DSS

V

_DD

V

_DS

BV

_DSS

t _p

V

_DD

I

_AS

V

_DS

(t) I

_D

(t)

Time

10V DUT

R

_G

L L

I

_D

I

_D

t _p

(7)

13N50/ F Q PF13N50

Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT

V

_DS

+

_

Driver R

_G

Same Type as DUT

V

_GS

• dv/dt controlled by R_G

• I_SDcontrolled by pulse period

V

_DD

L

I

_SD

10V

V_GS

( Driver )

I_SD ( DUT )

V_DS ( DUT )

V

_DD

Body Diode Forward Voltage Drop

V

_SD

I_FM, Body Diode Forward Current

Body Diode Reverse Current

I

_RM

Body Diode Recovery dv/dt di/dt D = Gate Pulse Width

Gate Pulse Period ---

DUT

V

_DS

+

_

Driver R

_G

Same Type as DUT

V

_GS

• dv/dt controlled by R_G

• I_SDcontrolled by pulse period

V

_DD

L

L I

_SD

10V

V_GS

( Driver )

I_SD ( DUT )

V_DS ( DUT )

V

_DD

Body Diode Forward Voltage Drop

V

_SD

I_FM, Body Diode Forward Current

Body Diode Reverse Current

I

_RM

Body Diode Recovery dv/dt di/dt D = Gate Pulse Width

Gate Pulse Period --- D = Gate Pulse Width Gate Pulse Period ---

(8)

13N50/ F Q PF13N50

Dimensions in Millimeters

Package Dimensions

4.50

±0.20

9.90

±0.20

1.52

±0.10

0.80

±0.10

2.40

±0.20

10.00

±0.20

1.27

±0.10

ø3.60

±0.10

(8.70)

2.80

±0.10

15.90

±0.20

10.08

±0.30

18.95MAX.

(1.70) (3.70) (3.00) (1.46) (1.00)

(45

° ) 9.20

±0.20

13.08

±0.20

1.30

±0.10

1.30

^+0.10_–0.05

0.50

^+0.10_–0.05

2.54TYP

[2.54

±0.20

]

2.54TYP [2.54

±0.20

]

TO-220

(9)

13N50/ F Q PF13N50

Dimensions in Millimeters

Package Dimensions

(Continued)

(7.00) (0.70)

MAX1.47

(30 ° )

#1

3.30

±0.10

15.80

±0.20

15.87

±0.20

6.68

±0.20

9.75

±0.30

4.70

±0.20

10.16

±0.20

(1.00x45 ° )

2.54

±0.20

0.80

±0.10

9.40

±0.20

2.76

±0.20

0.35

±0.10

ø3.18

±0.10

2.54TYP [2.54

±0.20

]

2.54TYP [2.54

±0.20

]

0.50

^+0.10_–0.05

TO-220F

(10)

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

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FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor.