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546 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 42, NO. 4, APRIL 1994

A High Gain Silicon AGC Amplifier

with a 3 dB Bandwidth

of

4

GHz

L.

C.

N.

de Vreede,

A. C.

Dambrine, J. L.Tauritz, Member, IEEE, and

R.

G.

F.

Baets, Member, IEEE

Abstract- In this paper, the design and realization of an

integrated high frequency AGC amplifier in BiCMOS technology are discussed. The amplifier has 36 dB voltage gain, 4 GHz bandwidth, dynamic range exceeding 50 dB, low spectral dis- tortion and low power consumption. The amplifier is suitable for application in wide-band optical telecommunication systems.

I. INTRODUCTION

ILICON is the material of choice for medium or large

S

scale integration of system blocks in many telecommu- nication applications. In the near future, however, bit rates of 5 to 10 GBit/s will become common. The design and use of silicon MMIC's for these applications is of growing interest and importance to the microwave community. This paper addresses the hierarchical design of an integrated AGC amplifier in silicon using commercial microwave design soft- ware. The amplifier chip has been realized in QUBiC, a Philips Semiconductors BiCMOS foundry process, featuring 1 micron geometry and encompasses more than eighty active devices. The AGC amplifier was designed for use in a 2.5 GBit/s coherent optical receiver. The amplifier was required to have a 3 dB bandwidth of at least 4 GHz and a minimum voltage gain of 30 dB (equivalent to a S,, of 24 dB). Additional requirements were a gain control range larger than 30 dB and the use of a standard 32 pin quad flat-pack ceramic package.

11. THE CIRCUIT DESIGN

The ordered design of complex integrated analog circuits is predicated on limited interaction between the constituent circuit blocks. One way to satisfy this, is the use of cascaded amplifier cells with a large inter-cell impedance mismatch, leading to potentially large bandwidth [2]. Inter-connects be- tween the amplifier stages must be kept short with respect to the minimum wavelength involved. The work of [5] which described an AGC amplifier design with a 3 dB bandwidth of

2.5 GHz has been used as a starting point for this study. The design of the AGC amplifier included additional speci- fications related to gain control, temperature stabilization and balanced as well as unbalanced application of the circuit.

Manuscript received February 19, 1993; revised June 21, 1993. L. C. N. de Vreede, J. L. Tauritz, and R. G. Baets are with Delft University of Technology, Dept. of Electrical Engineering, Laboratory for Telecommunication and Remote Sensing Technology, P.O. Box 5031, 2600 GA Delft, The Netherlands.

A. C. Dambrine was with Delft University of Technology, Dept. of Elec- trical Engineering, Laboratory for Telecommunication and Remote Sensing Technology, P.O. Box 5031, 2600 GA Delft, The Netherlands. She is now with Dassault Electronique, 92214 St. Cloud, France.

IEEE Log Number 92 1606 1.

p o l t

vee Fig. 1. Top level of the AGC amplifier.

Furthermore, in all the simulations the influence of bondwires, process tolerances etc. have been considered. The top level of the AGC amplifier design, including packaging parasitics, is given in Fig. 1. A block diagram of the silicon chip is depicted in Fig. 2.

The signal travels from the left to right passing respectively the matching input buffer (IB), two gain controllable amplifier cells (A1 and A2) each with a maximum of 12 dB gain, a fixed 12 dB gain amplifier cell (A3) and the output buffer (OB). Since dc coupling between stages is used, differential operation is required. The gain control signals are related to the differential voltage coming from the AC component peak detector PD1 and the DC reference peak detector PD2. The peak detectors feed their signals to the off-chip integrator circuit. The harmonic distortion of the high frequency signal is lowered by using an offset control circuit to reduce unbalance in the dc operating points of the amplifier stages.

A. The Input Buffer

The implementation of the input buffer together with an unbalanced 50 ohm external source is shown in Fig. 3. It should be noted that in combination with an external matching circuit the impedance level can be chosen to be 50 or 100 ohms. The extra resistor (marked with an asterisk in Fig. 3)

is necessary in this input circuit to avoid common mode to differential mode conversion of the supply voltage disturbance component on chip. The bondwire inductance in combination with the input impedance of the emitter follower input buffer can lead to unwanted resonances. Considerable effort has been expended on the development of a multi-purpose broadband input buffer to circumvent this problem. A solution has been found in a configuration, using a series RC-network in parallel with the input transistor to compensate for the negative input impedance. This yields an input buffer transfer characteristic 0018-9480/94$04.00 0 1994 IEEE

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g a i n c o n t r o l OUT c o n t r o l

{g

ldGC CONTROL

'

IB A 1 A2 A3

::I:}

. . P i c P i c

,

M L Y g a i n c o n t r o l IN slgnal l e v e l Fig. 2. Block diagram of the AGC amplifier.

double stage en1 tter follower (Cherry and Hooper) stages

o u t B

Q

o u t

Fig. 3. The input buffer with unbalanced input circuit.

(including package effects) that is flat within 2 dB up to at least 4 GHz. An additional advantage of the input compensation is very low power consumption for this circuit block.

B. The Amplijier Cells

Wide-band amplifier cells based on the circuit principles first proposed by Cherry and Hooper 29 years ago [2] have been designed. The combination of alternating transadmittance (TAS) and transimpedance stages (TIS) results in substantial impedance mismatch between succeeding stages leading to excellent wide-band performance. In Fig. 4, a dc-coupled differential amplifier cell based on this principle is given. This cell consists of a Cherry and Hooper stage and two emitter-follower stages. The emitter followers provide dc level shift and increased impedance transformation. Proper transistor dimensioning and biasing are essential for obtaining 4 GHz wide-band performance. The base resistance of the transistors involved is one of the bandwidth limiting factors in cascaded Cherry and Hooper stages. Through careful design low base resistance in combination with an acceptable bias current can be obtained. To further increase bandwidth a decrease in the TAS feedback with frequency is desired. This can be implemented by adding a simple capacitor or a tunable peaking impedance in parallel to the series feedback emitter impedance (see Fig. 4).

This peaking impedance changes the local feedback in the Cherry and Hooper stage and can be used to overcome prob-

Fig. 4. Principle circuit of the differential amplifier cells.

541

DE VREEDE ef ab: A HIGH GAIN SILICON AGC AMPLIFIER WITH A 3 dB BANDWIDTH OF 4 GHz

lems posed by process tolerances and variation of the bondwire inductances. The cells A1 and A3 have been provided with this peaking facility. Using this externally controllable tuning facility the slope of the gain frequency characteristic can be modified, canceling out hard to control parasitic effects, yielding a flat overall gain-frequency characteristic.

Consistent with the dynamic range requirement the first two amplifier cells ( A l , A 2 ) have variable gain. Gain control of these cells is based on the four-quadrant multiplier principle which offers large dynamic range and high linearity for large input voltage swings. In principal differential signals are converted to common mode signals at low gain levels. In the case of total conversion of the differential signal into a common mode signal no amplification will occur. A Cherry and Hooper stage with a four-quadrant multiplier is shown in Fig. 5. This proved to be well suited for the present task

[5]. We used the circuit shown in Fig. 5 in the first amplifier cell (Al). In this configuration four (equal) series feedback resistors and two shunt capacitors are required in the two upper differential stages. The schematic for the second amplifier cell (A2) shown in Fig. 6 is similar to that of cell A l , with the exception of the reversed gain-control and signal input. This has two advantages:

- Two emitter-follower stages are sufficient for shifting the signal level between the first and second cell. - This approach leads to compensation of the gain-

frequency characteristics of cell A1 and A2 for different gain levels. This is made possible since cell A1 the gain control is part of the ac signal path in contrast with the situation in cell A2.

The current sources in Fig. 4 are implemented as simple resistors. A current mirror at this point is undesirable due to the dominant parasitic capacitances of the transistors, which would lead to a decrease in impedance with frequency.

C. The Output Buffer

The output buffer should fulfil the following requirements - good impedance match at the output (to avoid instabil-

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548 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 42, NO. 4, APRIL 1994 trans1 npedance stage ( T I S ) four-quadrant l u l t i p l i e r gain c o n t r o l doubla stage (Cherry and thoper)

output

Fig. 5. in cell Al).

A Cherry and Hooper stage with a four-quadrant multiplier

double s t a g e transinpedance stage ( T I S ) I I ]output I ’ I I I I 2 (used transadmittance Fig. 6. in cell A2).

A Cherry and Hooper stage with a four-quadrant multiplier (used

- a flat frequency characteristic,

- insensitive to variation in the bond wire inductance, - extemal output impedance (open collector output). This list of requirements on the output buffer is nontrivial. In particular the matching problem (which leads to a 25 ohm load, as seen from the chip) in combination with the inductance of the bond wires ranging from 2 to 6 nH is problematical. Paralleling pins will reduce the inductance. One commonly used solution has a balanced open collector output to provide

- -

-

-1:;

- Fig. 7. The output buffer.

0 V 0

-

N Tu 1 v , ) m I

-

75 OC output b u f f e r w i t h c a m p e n s a t i a n - 0 0 Y . . h w 10.0 MHz f req 5.0 GHz

Fig. 8. Simulated output match for two different types of output buffer. high output impedance. However, sensitivity to bond wire variation remains a problem. Feedback contributed by the parasitic capacitances Cbc of the output transistors, results in additional mismatch in the output coupled with some peaking in Szl. This leads in turn to reduction in the stability factor

K . Simulations have shown that a modified open collector

buffer using the extemal output circuit depicted in Fig. 7 is less sensitive to this problem. The compensation circuitry has a positive influence on the stability factor K as well as the output match. This is illustrated in Figs. 8 and 9.

D. The Gain Control

The gain control-voltage generation is based on a two Peak Detector (PD) structure as shown in Fig. 2. We have chosen two PD’s to cancel out the effects of temperature variation. One PD detects the maximum value of the output signal (dc and ac component). The second PD detects only the value of the dc component. The difference between the output signals of the PD’s is directly related to the ac amplitude. Temperature variations which affect the dc level of the output signal will not be of influence on the differential voltage between the PD outputs.

The differential voltage output of the peak detector structure is fed to an external integrator. The output of the integrator circuit is connected to the AGC controller (on chip). This AGC

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DE VREEDE ef al.: A HIGH GAIN SILICON AGC AMPLIFIER WITH A 3 dB BAMlWIDTH OF 4 GHz 0 0 y Fig. 9 me(sured- . l , * l l l l . skruw'- A 10.0 MHz f r e o 5.0 GHz 0 V d (10diydiv)

. . .

ln ~ 549

Simulated stability factor K of the amplifier for two different output Fig. 11. The simulated and measured S Z ~ of the AGC amplifier for a set

buffers. offixed gain levels.

measured simulated fundamental frequency X second harmonic 0 third harmonic A fourlh harmonic 0 ... ... Fig. 10. Photograph of the chip showing the input buffer inpart as well the

- -

- -

- - -

first amplifier cell. fifth harmonic

Fig. 12. maximum gain.

Harmonic content versus input power with the amplifier set for

and A2. The symmetrical structure of the controllable amplifier cells leads to stringent requirements on the control voltages. Control signal deviation from zero leads to cell amplification. If the control signals change sign, amplification will once again occur. To ensure gain control stability, the differential gain control signal should be between 0 (no amplification) and 150 mV (maximum gain). Higher voltages will disturb the amplifier operation. A second condition for stable behavior of the gain control is the absence of high frequency components on the control voltages. Extra capacitors in cells A1 and A2 reduce the bandwidth of the gain control.

lead to an increase of the second harmonic of the HF signal and should be avoided. To obtain accurate offset control a simple integrator circuit has been used. For test purposes offset control was realized off chip.

F. Further Circuit Design Remarks

To insure proper behavior of the circuit conscious attention to detail was of the utmost importance. Three of the most significant aspects are listed below:

- In order to reduce the bondwire inductance of the most important signal paths, the size of the chip was customized to the size of the standard 32 pin quad flat-pack ceramic package.

- Particular attention has been paid to avoid unbalance in the layout of the chip.

E. The Offset Control

In high gain dc-coupled amplifiers, automatic offset control is mandatory. This is due to the fact that a small offset at the input will lead to a large change in operating point in the following differential stages. An offset in operating point will

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550

m 0

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 42, NO. 4, APRIL 1994

V

input -

Ln 0 I A 1 6 . 0 n s

t

I me 2 6 . 0 n s

Fig. 13. Measured input and output voltages under worst case conditions.

- All critical capacitors (on chip) in the HF path were specially placed in pairs such that their parasitics are balanced to substrate.

Layout generation is conform the standard design flow of the QUBiC process [3]. A photograph of the chip showing the input buffer in part as well as the first amplifier cell is given in Fig. 10. In this figure the balancing of parasitics in the chip layout can be noted.

111. SIMULATIONS

The development of the AGC amplifier has been carried out with the aid of HP’s Microwave Design System (MDS). Fine

tuning has been performed with Philips’ in house simulator Pstar using the more advanced silicon bipolar transistor model MEXTRAM (Pstar is a part of the recommended design flow of QUBiC). Pstar and MDS yielded comparable results. The low current levels used in the circuit tend to mask differences in the MEXTRAM and the Gummel Poon models in this application.

Although, dc and ac analysis are rather straightforward, the calculation of large signal behavior is more troublesome. The behavior of the feedback circuitry and the great difference in time constants between the HF signal path and the gain control loop complicate the simulation. This has proven to be independent of the simulation method employed. Both harmonic balance (HB) and time domain (TD) methods have their disadvantages. In the case of HB (as implemented in MDS release 4.0), the gain control feedback loop leads to a poorly chosen initial guess. Consequently, convergence of the solution takes excessive computing time. Time domain simulations (used in Pstar) are problematical due to the dif- ference in time constants in the HF signal path and the gain control loop. Computation of steady state conditions seems in this case interminable. In spite of these difficulties we have analyzed the large signal behavior of the complete network and the operation of the AGC loop. The results found using these advanced simulators, have been used to verify the circuitry under development and are in conformance with the measured results. V o u t p u t

level

1 6 . 0 n s t I me 26.0 n s Fig. 14. of 30 dB.

Output voltage of the AGC amplifier for an input dynamic range

Iv. EXPERIMENTAL CONFTGURATION AND RESULTS The packaged chip was soldered to a low cost FR4 (0.8 mm) glass-epoxy pc board. Use of this material facilitated drill hole metallization which we used to provide good grounding. In the test print design, extra attention was paid to obtaining suitable frequency characteristics while avoiding interaction between input and output. In the most sensitive areas of the test circuit uncoupling of the ac signals is carried out using two SMD capacitors in parallel with different values (e.g. 150 pF and 22 pF) to prevent capacitor self resonance peaks from influencing the characteristics to be measured.

The frequency response of the test print placed in a Cascade Microtech MTF26 test fixture was measured using a Hewlett Packard 85 10B/85 16A network analyzer-test set combina- tion. Time domain measurements were carried out using a Hewlett-Packard 54120T 20 GHz Digitizing Oscilloscope. For the spectral measurement use has been made of a Hewlett- Packard 8592A 50 kHz-22 GHZ Spectrum analyzer.

A. The Gain Frequency Characteristics

The simulated and measured gain frequency responses for several fixed gain levels as plotted in Fig. 11 are in excellent agreement. The measured (3 dB) bandwidth is 4 GHz com- pared to a simulated bandwidth of 4.2 GHz. The gain control range is seen to be better than 50 dB.

B. Large Signal Behavior

Large signal performance was determined by setting the amplifier to its maximum amplification and increasing the input power from -60 dBm up to -10 dBm. Simulated and measured harmonic content versus input power have been depicted in Fig. 12. In the automatic gain control mode worst case conditions for harmonic distortion occur when input and output signals are maximal (resp 700 mV and 400 mV peak to peak). Under these conditions the third harmonic component (harmonic distortion) is typically more than 20 dB down. The

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DE VREEDE et al.: A HIGH GAIN SILICON AGC AMPLIFIER WITH A 3 dB BANDWIDTH OF 4 GHz 551

TABLE I

EQUIVALENT CIRCUIT PARAMETERS FOR A TYPICAL

TRANSISTOR AS USED IN THE AGC AMPLIFIER

4 identical 2.4 x 2.4 pm2 Emitter mask size emitters

Cut-off frequency 9.5 GHz Current gain 90 Emitter-base capacitance C, e 59.6 fF Collector-base capacitance C,, 44.0 tF Collector-substrate capacitance 65.2 fF Base resistance 72.1 0 TABLE 11

MEASURED PERFORMANCE OF THE AGC AMPLIFIER

~ ~~

parameter measured result

max. voltage gain 36 dB

3dB Bandwidth 4 GHz

gain control range >50 dB max. dynamic input voltage 700 mV max. dynamic output voltage 400 mV

supply voltage 6 V

power consumption 450 mW

matchable impedance level 50-100 fl

time domain data for this situation using a 300 MHz input signal is illustrated in Fig. 13.

Note that the second and fourth harmonics will be lower in level then the third due to the balanced operation of the circuit.

C. The AGC Control

The operation of the AGC amplifier for various sinusoidal input levels is shown in Fig. 14. An input dynamic range of 30 dB is controlled to a fixed output level.

Summarizing the experimental results we conclude that the AGC amplifier under consideration meets the performance specifications noted in Table I.

V. CONCLUSION

Using advanced simulation programs and well established silicon foundry process technology (QUBiC) a low cost, low power, high gain, wide-band AGC amplifier chip with large dynamic range has been designed for mounting in a standard ceramic package. Testing has been performed using glass- epoxy pc board. Simulated and measured data show excellent agreement.

ACKNOWLEDGMENT

The authors wish to thank the following personnel of Philips Research Eindhoven: J. J. E. M Hageraats for his significant contribution to this project, P. W. Hooijmans and M. T. Tomesen for their useful comments and help during the design and layout period and Prof. R. J. van de Plassche for reviewing the initial design as well as the contents of this paper. Finally, the authors very much appreciated the assistance of P.M. de Greef of the SSP group of Philips Semiconductors who provided extensive software support.

REFERENCES

Y. Akazawa, N. Ishihara, T. Wakimoto, P. Kawarada and S. Konaka, “A design and packaging technique for high-gain gigahertz-band singlechip amplifier,” IEEE J. Solid-state Circuits, vol. SC-21 pp. 417-423, June 1986.

E. M. Cherry and D. E. Hooper, “The design of wide-band transistor feedback amplifiers,” Proc. Inst. Elec. Eng., vol. 110, pp. 375-389, Feb. 1963.

P. M. de Greef, G. H. M. Cloudt, G. M. Pasman, and J. D. P. van den Crommenacker, QUBiC design Jaw, P’ASIC/SSP-Philips Semiconductors, Eindhoven, Sept. 25, 1990.

M. Ohara, Y. Akazawa, N. Ishihara and S. Konaka, “High gain equal- izing amplifier integrated circuits for a gigabit optical repeater,” IEEE

J. Solid-state Circuits, vol. SC-20, pp. 703-707, June 1985.

R. Reimann and H. M. Rein, “A single-chip bipolar AGC amplifier with large dynamic range for optical-fiber receivers operating up to 3 Gbit/s,”

IEEE J. Solid-state Circuits, vol. 24, no. 6, pp. 1744-1748, Dec. 1989.

‘%

3

Leo C. N. de Vreede was born in Delft, The Netherlands in 1965. He received the B.S. degree in electrical engineering from the Hague Polytechnic, Hague, The Netherlands, in 1988.

In the summer of 1988, he joined the Microwave Component Group of the Laboratory of Telecom- munication and Remote Sensing Technology of the Department of Electrical Engineering, Delft Univer- sity of Technology. From 1988 to 1990, he worked on the characterization and modelling of CMC ca- pacitors. He is currently carrying out Ph.D. research on the hierarchical design of silicon “ 2 ’ s .

Anne Dambrine was born June 23, 1969 in Lille, France. She graduated in electrical engineering from the University Pierre et Marie Curie, Paris, France in 1991. She continued her studies in Electrical Engineering at the Ecole Nationale Suprieure du TI communications, graduating in June 1993.

In 1992, for a period of five months, she carried out research in the Microwave Component Group of the Delft University of Technology, Delft, The Netherlands, working on integrated AGC ampli- fiers. In 1993, she joined Dassault Electronique, St. Cloud, France. Her field of interest is microwave and optoelectronic devices.

Joseph L. Tauritz (S’60, M’63) was born in Brook- lyn, N.Y. in 1942. He received the B.E.E. from New York University, New York, NY, in 1963 and M.S.E. in electrical engineering from the University of Michigan in 1968.

From 1963 to 1970, he worked as technical specialist attached to the R.F. department of the Conduction Corporation where he designed inno- vative microwave, VHF and video circuitry for use in high resolution radar systems. In 1970, he joined the scientific staff of the Laboratory of the Telecom- munication and Remote Sensing Technology of the Department of Electrical Engineering, Delft University of Technology, Delft, The Netherlands where he is presently an Assistant Professor, after being a Research fellow from 1970 to 1971. Since 1976, he has headed the Microwave Component Group, where he is principally concerned with the systematic application of computer aided design techniques in research and education. His interests include the modelling of high frequency components for use in the design of MIC’s and MMIC’s, filter synthesis and planar superconducting microwave components. Mr. Tauritz is a member of ETA KAPPA NU and the Royal Dutch Institute of Engineers.

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552 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 42, NO. 4, APRIL 1994

Roe1 G. F. Baets (M'87) was born in Wommelgem, in electrical engineering from the University of Gent, Gent, Belgium, in 1977 and 1980 respectively. He received the M.S.E.E. from Stanford University, Stanford, CA, in 1981 and a D.Sc. from the Univer- sity of Gent in 1984.

Since 1981, he has been associated with the Laboratory of Electromagnetism and Acoustics of the Universitv of Gent. In 1989. he was aooointed

Belgium in 1957. He received the B.Sc. and M.Sc.

Professor in'the engineering faculty of the Uni- versity of Gent and in 1990 he received a part-time appointment at the Delft University of Technology, Delft, The Netherlands, as well. He has worked in the field of III-V devices for optoelectronic systems. With over 100 publications and conference papers he has made contributions to the modelling of semiconductor laser diodes, passive guided wave devices and to the design and fabrication of OEIC. His main interests are in the modelling, design and testing of optoelectronic devices, circuits and systems for optical communication and optical interconnects.

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