AN IMPLEMENTATION OF THE LINE CODE MB810

P O Z NA N UN I V E R S ITY O F TE C H N O LO GY A C A D E M IC J O U R N AL S No Electrical Engineering

Andrzej WOLCZKO*

Łukasz ŚLIWCZŃSKI*

Marcin LIPIŃSKI*

Przemysław KREHLIK*

AN IMPLEMENTATION

OF THE LINE CODE MB810

MB810 (minimum bandwidth 8B/10B) ) is another version of the popular 8B/10B code. It has been designed to obtain two properties: concentration of the power density in the low frequency range and elimination of the DC component. The description of the code, implementation in FPGA Spartan3 circuit and the results of the tests are briefly described in the text.

Keywords: 8B/10B codes, FPGA implementation, VHDL

1. INTRODUCTION

Patented in 2002 year [1] the MB810 code is not a composition of the subcodes as well known since eighties 8B/10B [2] (composition of 5B/6B and 3B/4B) but according to described in the patent procedure each possible 8-bit block is directly converted into 10-bit block.

2. BASE OF MB810 CODE

Inventors of the code assumed that goals to be achieved are:

• elimination of the DC component in serial data stream formed from 10-bit code blocks

• getting the power density spectrum mostly concentrated below the half Nyquist frequency f<1/2T, in other words less than half bit frequency. Above mentioned properties are strictly connected with values of the several parameter of the line codes. A convention that for current bit Y value -1/2 is attributed to logical zero and value +1/2 to logical one is set in this text.

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These parameters are:

RDS ( running digital sum)

∑

=

=

Y

RDS

Alternatively, parameter RD (running disparity) is defined as ΣYn taking values –1 and +1 for logical symbols – RD is not used in this article.

DSV (digital sum variation) DSV =maxRDS ; RAS (runnig alternate sum)

( )

n J I n

Y

RAS

∑

−

=

1

ASV (alternate sum variation) ASV =maxRAS ; In each situation I<J.

If in the line code [1], [3] ASV is finite that there is a notch (V-shape) in the continuous power density spectrum at half Nyquist frequency and is spectral null at Nyquist frequency. Moreover, if DSV is finite the code is DC free.

In MB810 both ASV and DSV are finite – ASV=5; DSV=6 [3]. In the coding process for each one of 256 possible 8-bit blocks the 10-bit block from the complete code table is taken out. This table contains 626 (of 1024 possible) 10-bit blocks with corresponding to each block RDS and RAS values. It means that (similarly to other codes) for each 8-bit input word one of two (or four) 10-bit words can be selected from the suitable cell of the code table. The choice, which one would be selected, is determined by values of RDS and RAS of the previous generated code word. The rules of selection, in the synthetic form, are shown in the table 1.

Each of 626 code words has one of twelve possible combinations of RDS, RAS determining one of twelve states of the coder s(1) ÷s(12). State s(i) of the currently generated code block in connection with 8-bit input word (i+1) sets the next s(i+1) state and i+1 output block according to the code table [1] but for the proper choice number of address group also must be known. This fact complicates the structure of the coder. Because the coder may be threaten as certain 8-bit input / 10-bit ROM with buffered output we identify 8-bit input word with an input address. Current control (word after word) of the RDS and RAS values makes possible keeping finite values of this parameters in arbitrary long sequence of coded data, what means that the generated sequence reaches the goal No2. In each of 626 code words the set of identical logic symbols do not exceed 6 what makes easier the bit synchronization (run length = 6). In analogy to the others excess codes MB810 makes possibility of error detection – the Hamming distance however do not exceed 2).

Table 1. Rules of selection of the code word

Code blocks 10 bits Input block

8 bits

decimal notation RDS RAS

Number of combinations in code table Number of out combinations for

1 input block Adress group 0 - 94 1 -1 0 0 95 95 2 1 95 - 193 0 0 1 -1 99 99 2 2 194 - 233 2 -2 -1 1 -1 1 -2 2 40 40 40 40 4 3 234 - 255 1 -1 -2 2 -2 2 -1 1 22 22 22 22 4 4

3. IMPLEMANTATION

It seems that the simplest circuit realization of the coder is the combinational logic structure with output buffer: 8-bit input / 10-bit output. Implementation of the MB810 coder needs writing of 256 conditional instructions in VHDL (or the other) language and to provide the rest of the task by computer synthesis tools. This way has been choice in the first attempt of the synthesis with Xilinx Spartan3 XC3S50 FPGA circuit. The conditional instructions for MB810 contained 13-argument logic sums, which are not realised within basic configurable logic block CLB in Spartan but must be made in the complex manner. The trial of synthesis in XC3S50 was not successful.

The second trial is based on an idea shown in figure 1. Synthesis and implementation has been made using Xilinx ISE 7.1 program. The hierarchic block diagram contains several circuit blocks witch are, according to design convenience, either ISE library blocks (sch) or functional, described using VHDL code (vhdl). Detailed code table contains partly two and partly four columns of the code words. Spartan 3 circuits have four dedicated RAM memories used in this project as ROM memories with the 8-bit address and 14-bit output word. Each of four columns of the code table containing 10-bit code word and additional 4-bit is located in separate memory.

Output Data Selector (vhdl) Clk2 Clk2 Clk2 Clk2 Output Serializer (vhdl) Clk1 RDS, RAS (4) MB810 (10) RAM1 (sch) RAM2 (sch) RAM3 (sch) RAM4 (sch) D1(14) D2(14 D3(14) D4(14) Pam (4) Wy_s Buffer 4 bits (sch) Argum (vhdl) Memory Selector (vhdl) (12) Clk2 Address(8) (6) Buffer 8 bits (vhdl) Clk2 Ps-random _Generator (vhdl) (8) Adress _Comparat. (sch+vhdl) 1/10 (vhdl) We Clk1 Clk2 Clk2

Fig.1. MB810 – block diagram.

The additional 4-bits represent one of 12 combinations RDS and RAS parameters associated with this particular code word. All memories are addressed by the same input word but only one of four 14-bit block is selected to output. The output data selector is controlled by signals pam(1÷4) . These signals depend on RDS, RAS data latched in 4-bit buffer during previous memory readout (code step) and on current address group (table 1) determined by the Address Comparators (fig.1).The proper generation of the pam signals is made in two important blocks: argum and memory selector. Such partition was caused only by the convenience in preparing their vhdl description. For simulation and test purposes of the coder three additional (external to coder) circuit blocks were added to the implementation: 8-bit pseudorandom generator, output serializer and 10-times frequency divider of the clock Clk1. During each 10 pulses of the Clk1 (one Clk2) the complete coding process is finished and 10-bit code serial sequence appears at the serial output.

4. TESTS OF THE CODER.

After synthesis, implementation and functional simulation the XC3S50 installed on a test board has been programmed. The clock frequency Clk1 was set to 50MHz and all tests have been done at this speed.

In figure 2 the eye pattern at the serial output of the coder is presented. Coupling with oscilloscope was AC; acquisition time over 1 minute. Sharp, clear oscillogram, especially along Y axis, shows that data stream is DC free.

Fig. 2. Eye pattern at the serial output of the coder.

In figure 3 the power density spectrum of the MB810 code is presented.

-50 -40 -30 -20 -10 0 0 25 50 75 100 f [MHZ] d [dBm/Hz]*

Fig. 3. Power density spectrum of the MB810 code

In the range 0÷25MHz (half Nyquist frequency) about 75% and in range 0÷50MHz about 93,5% of the whole power is concentrated.

*The exact value of the power density depends on the input signal level-in figure 3 the result has been normalized to the range 0÷-50 dBm.

The next test has been made using a piece about 20 m of twisted pair (UTP) as a transmission medium in the circuit shown in figure 4. High frequency operational amplifiers served as symmetrical and desymmetrical units.

47 47 100 51 51 In Out A_sym A_des

Fig. 4. Test circuit.

In figure 5 frequency transmittance of the test circuit (figure 4) is presented. The transmittance is dominated by frequency properties of the UTP; -3dB frequency limit is equal about 25 MHz.

-40 -30 -20 -10 0 10 0 20 40 60 80 100 f [MHz] dBm

Fig.5. Transmittance of the test circuit.

In the figure 6 the eye pattern of the MB810 coded sequence and in figure 7 the eye pattern of the NRZ sequence at the output of the test circuit (figure 4) are presented. Coupling with oscilloscope was AC; acquisition time over 1 minute. It can be observed that there are not fundamental differences between these two oscillograms. Although MB810 has power density moved to lower frequencies no spectacular advantage of the reduction of the inter symbol interference is noticed.

Fig.6. Eye pattern of the MB810 coded sequence.

Fig.7. Eye pattern of the NRZ sequence.

5. CONCLUSIONS

Measurements of the implemented in FPGA Spartan 3 MB810 coder show that the results are consistent with design assumptions and with published results [3]. Analysis of the Xilinx Post-Place&Route Static Timing implementation report indicates that minimal period of the Clk1 clock signal is equal 19,1 ns (max fClk1=52 MHz). It means that speed of the coder even in application of the fast

the coder is complex, advantages of ISI reduction are insignificant and because the elimination of the DC component can be made by simpler well known codes, in authors opinion, practical applications of the MB810 are not profitable.

REFERENCES

[1]

[2] A.X Widmer,P.A.Franaszek : A DC-balanced, Partitioned Block,8B/10B Transmission Code, IBM Journal Res.Developm. Vol.27 no.5 1983. [3] Lee and alt.: E New Line Code MB810 for 10GbE, ED

http://ieee.org/groups/802/3/10G_study/public/july99/kim_1_0799.pdf

[4] Xilinx Ds099 April 26, 2006, Spartan 3 FPGA Family: Complete Data Sheet,