ZESZY TY N A U K O W E P O L IT E C H N IK I ŚLĄ S K IE J Seria: A U T O M A T Y K A z. 134
2002 N r kol. 1554
Tadeusz SA W IK
A kadem ia G órniczo-H utnicza
SCHEDULING BATCHES OF PRINTED WIRING BOARDS IN SURFACE MOUNT TECHNOLOGY LINES1
S u m m a r y . T h e p a p e r p resen ts a m ixed integer program m ing approach for b atch scheduling o f p rin te d w iring b o a rd assem bly in surface m ount technology (SM T) lines. A ty p ic a l S M T line consists of several assem bly sta tio n s in series a n d /o r in parallel, se p a ra te d by finite in te rm ed ia te buffers. T h e problem objective is to m inim ize m a k esp a n of a n assem bly schedule for a m ix of b o ard types, w here identical b o a rd s are scheduled consecutively. N um erical exam ples m odeled after real-world S M T lines illu stra te th e approach.
S Z E R E G O W A N IE P A R T II W Y R O B Ó W E L E K T R O N IC Z N Y C H W L IN IA C H M O N T A Ż U P O W IE R Z C H N IO W E G O
S tr e s z c z e n ie . W p ra c y przedstaw iono m odel program ow ania calkowitoliczbowego m ieszanego do h arm onogram ow ania m on tażu powierzchniowego p a rtii w yrobów elektronicznych w liniach S M T (ang. Surface M ount Technology). L inia SM T zbudow ana je s t z szeregowo połączonych stadiów z m aszynam i równoległym i i b u forami m iędzyoperacyjnym i. N ależy w yznaczyć n ajk ró tszy harm onogram m ontażu wielu p a r tii różnych typów w yrobów , w k tó ry m w yroby jednego ty p u m ontow ane są kolejno. Z astosow ania opracow anego m odelu ilu stru ją przykłady liczbowe o p arte n a rzeczyw istych danych z przem ysłu elektronicznego.
1. Introduction
P rin te d w iring b o a rd assem bly is typically perform ed on an au to m ated Surface M ount T echnology (SM T ) line w hich includes th ree different processes in th e fol
lowing sequence: solder p rin tin g , com ponent placem ent an d solder reflow. A typical SM T line co n sists o f several assem bly sta tio n s in series a n d /o r in parallel, se p arate d by finite in te rm e d ia te buffers an d connected w ith a conveyor system th a t tran sfers the b o a rd s betw een th e sta tio n s, see [6].
'This work was partially supported by AGH and KBN (Poland) and by the Motorola Advanced Technology Center(USA)
340 T. Sawik
A n S M T line is a p rac tic a l exam ple of a flexible flow line w ith lim ited interm e
d ia te buffers a n d p arallel m achines, e.g. [4]. T h e lim ited in te rm e d ia te buffers result in a blocking scheduling problem , e.g. [2, 3], w here a com pleted b o a rd m ay remain on a m achine a n d block it u n til a do w n stream m achine becom es available.
In p ra c tic e scheduling of S M T line is based on daily d em an d s an d a sim ple ap
p roach to execu tin g daily p ro d u ctio n p la n is th e use of b a tc h scheduling, where b o a rd s of one ty p e are scheduled consecutively. In a high-volum e p ro d u ctio n , how
ever, th e p ro d u c tio n p la n is o ften sp lit in to several identical sets of sm aller batches of b o a rd s t h a t are scheduled repeatedly. T h e sm allest possible set of b o ard s in the sam e p ro p o rtio n as th e daily b o a rd m ix requ irem en ts is called M inim al P a r t Set (M P S ), e.g. [1],
R esearch on scheduling alg o rith m s for flexible assem bly lines w ith finite capacity buffers is m o stly re stric te d to h eu ristics w hich seek good solutions w ith in reasonable c o m p u ta tio n tim es, e.g. [3]. T h is p a p e r however, provides th e rea d e r w ith an exact m ixed in te g er p ro g ra m m in g form u latio n for b a tc h scheduling of p rin te d w iring board assem bly in S M T lines, e.g. [4, 5, 6]. T h e form ulation proposed is cap ab le of finding o p tim a l b a tc h schedules for various S M T line configurations b y using commercially available softw are for m ixed integer program m ing.
T h e p a p e r is organized as follows. In th e n e x t section a m ixed in teg er program m ing fo rm u latio n is p rese n ted for b a tc h scheduling in a flexible assem bly line with m achine blocking. N um erical exam ples m odeled a fte r real-w orld S M T lines and som e c o m p u ta tio n a l resu lts are provided in S ection 3, an d conclusions are given in th e la s t section.
2. M ixed integer program for batch scheduling
In th is section a m ixed integer pro g ram m in g m odel is p rese n ted for b a tc h schedul
ing in a flexible assem bly line w ith lim ited in te rm ed ia te buffers.
A unified m odeling ap p ro ach is a d o p ted w ith th e buffers view ed as machines w ith zero processing tim es. As a re su lt th e scheduling p roblem w ith buffers can be converted in to one w ith no buffers b u t w ith blocking, e.g. [3, 4],
N o ta tio n used to fo rm u late th e p roblem is show n in T able 1, w here buffers and m achines are referred to as processors.
T h e flexible assem bly line u n d e r stu d y consists of m processing stages in series.
E ach sta g e i, (i = 1, . . . , m ) is m ad e u p of > 1 identical p arallel processors.
L et Ji b e th e circu lar se t of indices of p arallel processors a t sta g e i. T h e system p roduces various ty p e s of b oards. L et G = { 1 , . . . ,p } , K = { 1 , . . . ,n } , an d K g = {H feG :f< g b f + 1, • • ■ , E / 6C:/<9 &/ + M be th e ordered sets of indices, respectively of all b a tc h e s of b o ard s, all in dividual b o ard s, a n d all b o a rd s of ty p e g € G, (bg]
n = bgi an d p denote, respectively th e num ber of b o a rd s of ty p e g, th e total n u m b e r o f b o ard s, a n d th e n u m b er of b atch e s in th e schedule.)
A ll b o a rd s are scheduled in b atch es of b o a rd s of th e sam e ty p e a n d w ithin the b a tc h in d iv id u al b o a rd s are processed consecutively. No se tu p s are required be
tw een different b o a rd s or different b atch e s of b o ard s. E ach b o ard m u st be processed w ith o u t p re e m p tio n o n exactly one processor in each of th e stages sequentially. The
Scheduling B atch es of P rin te d W iring B oards in S M T Lines 341
T able 1 N o tatio n
I n p u t p a r a m e t e r s bg = size of b a tc h g (num ber of b o ard s of ty p e g) m = n u m b e r of processing stages, ¿ G / = { l , . . . , m }
rrii = n u m b e r of p arallel processors a t stag e i, j e Ji — { 1 , . . . ,m ,}
n = to ta l n u m b er of b oards, k £ K = { I , . . . ,n }
V = n u m b e r of b atch es (b o ard ty p e s), j 6 G = { l , . . . , p } rig = processing tim e a t stag e i of b o ard ty p e g
D e c is io n v a r ia b le s Cmai = schedule le n g th
Cik = com p letio n tim e of b o a rd k a t stag e i dik = d e p a rtu re tim e of b o a rd k from stag e i
%ijk = 1, if b o a rd k is assigned to processor j £ Ji a t stage i £ I; otherw ise S'ijk d
y f 9 = 1, if b a tc h / precedes b a tc h g\ otherw ise y f g = 0
order of processing th e b o ard s in every stag e is identical an d d eterm ined by an in p u t sequence in w hich th e b o a rd s en ter th e line, i.e., a so-called p e rm u ta tio n flowshop is considered.
For every b o a rd k d en o te by c^k its com pletion tim e in each sta g e i, a n d by dik its d e p a rtu re tim e from sta g e i.
L e t Tig > 0 b e th e processing tim e a t sta g e i of each b o ard ty p e g £ G. Processing w ith o u t p re e m p tio n ind icates th a t b o ard k £ K g com pleted a t stage i a t tim e Cik sta rts its processing in t h a t sta g e a t tim e c** — r ^ . B oard k £ K g com pleted a t stage i a t tim e c,-* d e p a rts a t tim e dik > Cik to an available processor in th e n ex t stage i + 1. If a t tim e Ci* all m i+i processors a t stag e i + 1 are occupied, th e n th e processor a t sta g e i is blocked by b o a rd k u n til tim e dik — Ci+ik ~ r i+ig w hen b oard k £ K g s ta r ts processing on an available processor a t stag e i + 1.
T h e o b je ctiv e is to d eterm in e an in p u t sequence of b atches of b o ard s an d an assignm ent of b o a rd s to processors in each stage over a scheduling horizon to com plete all th e b o a rd s in m inim um tim e, th a t is, to m inim ize th e m akespan Cmax = maxj^ K (c m k ), w here c^k denotes th e com pletion tim e of b o ard k in th e last sta g e m .
T h e m ix ed in teg er p ro g ra m for b atch scheduling in a flexible assem bly line w ith finite in-process buffers is p resented below.
M inim ize
C m a x ( I )
su b je c t to
Board a ssig n m e n t constraints
X > yJfc = l; i £ l , k £ K (2) jeJi
X i,next U M , k + i = x a k \ i € I , j € Ji t g € G ,k £ K g : k < la st{K g),m i > 1 (3)
B oard com pletion constraints
C\k ft I'igi 9 ^ G, k G Kg (4)
Cik Ci—ifc ft rig, i G f f g G G ^ G Kg . i t> 1 (5) B oard departure constraints
Cik < dik; i G I , k G K : i < m (6)
Cmk = djfiki k G K (7)
B oard no n -in terferen ce constraints
342______________________________________________________________T. Sawik
£\k (Q ifg K ljfz')(2 + y/g Xijk 2'ijia3t(/<'a)) ^ ^tia3£{jra) 4" r if 4~ H ifk ; i G I , j G J i , f , g G G , k G K f : f < g (8) Ci, 4* {Qigf 4“ K igl)(3 y/g Xijlast(Kf) ~ duast(Kf) 4" 7*jg 4" K{g[,
i G I , j G Ji, f , g G G , l G K g : f < g (9) Cifirst(K/) 4- (Qifg 4- Tigi){2 + 2//g — XijfiT3t(Kf) ~ ®yi) — du + 7",/ + Tfgi,
i G I , j G J i , f , g G G , l G K g : f < g (10) Cifirst(Kg) 4- {Qigf 4" B ijk) (3 — yjg — Xijk ~ X ijjiTst{Ks)) ft dik 4- 4- T ifk,
i G I , j G J u f , g G G , k G K f : f < g (11)
B u ffe rin g constraints
rik — d i-ik 4- rig\ i G I , g G G , k G K g : i > 1 (12) M a x im u m com pletion tim e constraints
C m k < C max\ k G K (13) dik 4- 5 2 r kg — Cmax j ^ £ I , g G G ,k G K g : i < m (14)
h£l:h> i
g- 1 Cmi - C i , < C max - 5 2 bf ri f Vf g ~ 5 2 bf r ri0- ~ Vgf) ~ (l ~
Y
b})r\gfeG-f<g feG:f>g f =1
9
~~(y~! bf — l) r mg — 5 2 b fr mf ( 1 — y f g) — 5 2 bfTmf y gf\
f = 1 f£G:f<g feG:f>g
g G G, I G K g : m x = 1, m m = 1 (15)
B a tc h processing constraints
Cik+mt > d ik + r ig\ i G I , g G G ,k G K g : k + m i < la s t{ K g), m , > 1 (16) Cik+ i > C ik ; i G I , g G G ,k G K g : k < la s t ( K g) ,m i > 1 (17) CiJt+i > (kk + rig-, i G I , g G G ,k G K g : k < la s t ( K g), m , = 1 (18)
Variable elim in a tio n constraints
y fg = 0; k , l G
K
: f > g (19)Scheduling B a tc h es of P rin te d W irin g B oards in 5 M T Lines 343
Variable n o n n eg a tivity and integrality constraints
C ik > 0 \ i € l , k < = K (2 0 )
dik > 0; i G I , k G K (21)
Xijk € {0,1}; i € l , j <=Ju k < = K (22)
yig € {0,1}; / , g G G (23)
T he o b je ctiv e fu n ctio n (1) rep rese n ts th e schedule len g th to b e m inim ized. A s
signment c o n s tra in t (2) ensures t h a t in every stag e each b o ard is assigned to exactly one processor, a n d (3) assigns successive b o a rd s of one ty p e altern ativ ely to differ
ent p arallel processors (n e x t ( j , J j) is th e n ex t processor a fte r j G J* in th e circular set Jj of p a ra lle l processors a t sta g e i). C o n s tra in t (4) ensures th a t each b o ard is processed in th e first stag e, an d (5) g u aran tees th a t it is also processed in all dow n
stream stag es. C o n s tra in t (6) ind icates th a t each b o ard ca n n o t be d e p a rte d from a stage u n til it is co m p leted in th is stag e, an d eq u atio n (7) ensures th a t each b o ard leaves th e line as soon as it is co m pleted in th e la st stage. C o n stra in ts (8),(9),(10) and (11) are b o a rd non-interference co n strain ts. No tw o b o ard s can b e perform ed on the sam e processor sim ultaneously. For a given sequence of b atch es only one con
straint (8) o r (9) is active, an d only if b o th bo ard s k € K f an d la s t(K g) or I G K g and l a s t ( K f ) are assigned to th e sam e processor. Likewise, eith er (10) or (11) is active, an d only if b o th b o ard s I G K g an d f i r s t ( K f ) or k G K f an d f i r s t ( K g) are assigned to th e sam e processor. E q u atio n (12) in d icates th a t processing o f each board in every sta g e s ta r ts im m ediately a fte r its d e p a rtu re from th e previous stage.
Constraint (13) defines th e m axim um com pletion tim e of all boards. C o n stra in t (14) relates b o a rd d e p a r tu re tim es to m akespan directly. E very b o a rd m u st b e d e p a rte d from a sta g e sufficiently early in order to have all of its rem aining ta sk s com pleted within th e rem a in in g processing tim e. C o n stra in t (15) ensures th a t each b o ard is processed w ith in th e tim e interval rem aining a fte r processing of all preceding b o ard s and before processing o f all succeeding b oards. Flow tim e Cmi — (cu — r ig) of each board I G K g c a n n o t b e g re a te r th a n th e m akespan C max m inus sum of processing times of all preceding b o ard s in th e first stag e
<7-1
J 2 bf r u y f g + Y , V v ( i - ya/ ) + (f - 1 - I > / ) n 9,
fe G :f< g fs G -.f> g / = 1
and sum of processing tim es of all succeeding b o a rd s in th e la st stag e 9
( Y . bf l)rmg + Y , bfrmj ( l — yf g) + Y , bfrmf ygf.
/ = 1 fe G :f< g f<zG :f>g
Batch processing c o n stra in ts (16),(17) along w ith (3) ensure th a t b o ard s of one type are processed consecutively in each sta g e w ith p arallel processors, w hereas consecutive processing of identical b o ard s in each stage w ith a single processor is imposed by (18).
P ara m e te rs f f i / t , 7}/* a n d Q tf g in c o n stra in ts (8)—(11) are calcu lated as below.
/ - i
H ifk — m ax{0, [(k ~ Y bg ~ € I , f e G , k £ K f (24) g = l
344 T. Sawilc
!
T ifk = m ax{0, [ ( Y bg - k - r r i i + 1 ) / m iJ } r i / ; j € / , / 6 G , k 6 K f (25) 5=1
Qi f a = Y Y b9r ig /m i - Y r V - Y r ^g< i € l , f , g € G (26)
i € i g&G h<zl:h<i h e l:h > i
w here H ijk a n d T ifk d en o te respectively, h ea d an d ta il of b o ard A; € K f in batch / a t sta g e i > a n d Q ijg is a large n u m b e r n o t less th a n th e schedule le n g th calculated for sta g e i w hen b a tc h / precedes b a tc h g.
T h e p ro p o sed m ixed integer p ro g ra m includes various c u ttin g co n stra in ts that w ere id e ntified ex p lo itin g ty p ic al S M T fine configurations a n d som e properties of b a tc h p rocessing on p arallel m achines. T h e c o n stra in ts m ay significantly reduce c o m p u ta tio n a l effort req u ired to find th e o p tim al solution.
3. Numerical examples
In th is se ctio n n u m erical exam ples are presen ted , an d som e co m p u ta tio n a l results are re p o rte d to illu s tra te th e m ixed integer pro g ram m in g approach. T h e examples are m odeled a fte r real-w orld S M T fines [6]. T h e assem bly schedules for th e examples were c a lc u la te d on a la p to p C om paq P re sario 1830 w ith P e n tiu m III, 450 MHz using A M P L m odeling lang u ag e a n d C P L E X v.7.1 solver.
3.1. E x a m p le 1: F a c to ry w ith single s ta tio n s
T h e S M T fine co n figuration for E x am p le 1 is show n in F ig u re 1. T h e fine consists of a loader, screen p rin te r, four placem ent m achines a n d a vision in sp ectio n machine, in series se p a ra te d b y in te rm e d ia te buffers.
(3) (g)
E O & O O H M O
©
" O ’ O h o ...
C H D - O
© © ©
O S K > * C H i K >
1 © © ©
] - machine Q ~ buffer O “ many buffers
Fig. 1. Factory with single stations Rys. 1. Linia z pojedynczymi maszynami
T h e lin e rep rese n ts a ty p ic al low-volume, m edium -variety p ro d u c tio n system.
F or th e in d u s try scenario th a t w as stu d ied , 13 different b o a rd ty p es are assembled in sm all to m edium size batches. T able 2 fists th e processing tim es for boards, and T able 3 p re se n ts th e in p u t d a t a for selected p roblem in stan c es t h a t represent five d aily p ro d u c tio n orders.
Scheduling B a tc h es of P rin te d W irin g B o ard s in S M T Lines 345
T able 2 E xam ple 1: P rocessing tim es in seconds B oard ty p e P rocessing stag e
1 3 7 11 15 19 23
1 20 25 123 45 38 62 45
2 20 25 155 156 28 58 50
3 20 25 67 56 36 35 45
4 20 25 93 95 - 51 40
5 20 25 76 111 41 63 50
6 20 25 87 93 52 48 45
7 20 25 34 78 92 55 45
8 20 25 66 28 34 - 30
9 20 25 141 90 49 - 40
10 20 25 86 83 56 22 45
11 20 25 98 84 36 43 45
12 20 25 176 T75 76 65 50
13 20 25 - 17 67 28 45
Table 3 Example 1: Input D ata________________________
Problem Daily Mix
no. Board Batch Board Batch Board Batch Board Batch
type size type size type size type size
1 7 13 9 6 - - - -
2 2 23 9 1 - - - -
3 7 2 11 66 - - - -
4 5 34 7 2 8 22 9 2
5 1 42 4 2 7 4 10 14
T h e c h a ra c te ristic s of m ixed integer p ro g ram s for th e exam ple problem s a n d th e solution re su lts are su m m arized in T able 4. T h e size of th e m ixed integer program s for th e ex am p le pro b lem s is rep resen ted b y th e to ta l n um ber of variables, Var., number o f b in a ry variables, B in ., nu m b er of c o n stra in ts, Cons., a n d n u m b e r of
T able 4 E x am p le 1: C o m p u ta tio n a l R e su lts
P ro b le m Var. Bin. Cons. Nonz. L B C*max Nodes C P U "
1 1085 590 2687 9649 1722 1722 13 1.4
2 1370 745 3442 12284 3953 3967 0 1.1
3 3878 2109 •9861 35022 6789 6789 0 9.9
4 3427 1866 17964 73788 4869 5016 12 38
5 3541 1928 18579 76280 6923 6925 1 51
* o p tim a l m akespan, “ C P U tim e for proving o p tim ality
346 T . Sawik
nonzero coefficients, N onz., in th e co n s tra in t m a trix . T h e la st four colum ns of Table 4 p rese n t th e lower b o u n d L B on th e m akespan, th e o p tim al m akespan Cmai, the n o d e n u m b e r in th e b ra n c h -a n d -b o u n d tre e a t w hich th e o p tim al solution was found, an d C P U tim e in seconds req u ired to prove o p tim ality of th e solution. T h e lower b o u n d w as ca lc u lated as below.
L B — m a x { ] P bgr ig/ m i + m i n geg( £ r hg) + m i n gGG( ^ r *s)} (27)
l £ / geG h e l:h < i h £ l:h > i
3.2. E x a m p le 2: F a c to ry w ith p a ra lle l s ta tio n s
Fig. 2. Factory with paraUel stations Rys. 2. Linia z maszynami równoległymi
T able 5 E x am p le 2: P rocessing tim es in seconds B oard ty p e P rocessing stag e
1 5 9 13 17 19 21
1 22 207 213 204 80 40 62
2 22 208 220 204 80 40 62
3 22 207 224 191 80 40 62
4 22 207 213 204 80 40 62
5 22 207 220 204 80 40 62
6 22 184 196 199 80 40 62
T h e S M T line co n figuration for E x am p le 2 is show n in F ig u re 2. T h e fine consists of a screen p rin te r, th re e sets of tw o p arallel p lacem ent m achines a n d four shuttles ro u tin g th e b o a rd s to th e n e x t available placem en t m achine, a vision inspection ma
chine a n d a single placem ent m achine, in series se p a ra te d by in te rm ed ia te buffers.
T h e line rep rese n ts a ty p ic al high-volum e, low -variety p ro d u c tio n system , in which six different b o a rd types are p ro d u ce d in m edium to large size batches. T able 5 lists th e processing tim es for b o ard s, an d T able 6 presents th e in p u t d a t a for selected pro b lem in sta n c e s th a t rep rese n t five daily p ro d u c tio n orders a n d th e correspond
ing m in im u m p a r t sets (M PS ). T h e ch a racteristics of m ixed integer program s for th e M P S p ro b lem s an d th e solution resu lts are sum m arized in T able 7. Figure 3
Scheduling B a tc h es o f P rin te d W irin g B o ard s in S M T Lines 347
Table 6 Exemple 2: Input D ata
Problem Daily M ix/M PS
no. Board Batch Board Batch Board Batch Board Batch
type size type size type size type size
1 3 240/6 4 200/5 5 480/12 - -
2 1 80/2 2 120/3 3 240/6 5 480/12
3 1 180/6 2 210/7 3 510/17 - -
4 3 300/3 4 400/4 5 500/5 - -
5 3 1080/27 6 400/10 - - - -
T able 7 E xam ple 2: C o m p u ta tio n a l R esults
P ro b le m Var. Bin. Cons. Nonz. L B C1*^max N odes CPU**
h 1269 670 4778 18250 3127 3233 20 20
2 1272 673 6265 25433 3137 3247 46 200
3 1654 873 6276 23892 3915 3993 8 26
4 664 351 2432 9400 1914 1992 21 1.6
5 2037 1074 5380 17975 4583 4695 11 5.4
* o p tim a l m akespan, ** C P U tim e for proving o p tim ality
shows G a n tt c h a rt w ith th e o p tim al b a tc h schedule o b ta in e d for P ro b le m 2, w here le tte r B s ta n d s for Buffer an d M sta n d s for M achine for screen p rinting, com ponent placem ent, o r vision inspection. Buffering or m achine blocking is in d ic ated w ith a narrow b ar. T h e in p u t sequence of b o a rd ty p es is 5,2,1,3, an d th e o p tim al m akespan Cmax = 3247.
4. Conclusion
T h is p a p e r h a s p rese n ted a n ex a ct ap p ro ach for b a tc h scheduling in flexible as
sembly lines w ith lim ite d in te rm ed ia te buffers. T h e ap proach based on a m ixed integer p ro g ra m m in g form u latio n is cap ab le of o p tim al scheduling S M T lines by using com m ercially available softw are for integer program m ing. T h e co m p u ta tio n tim e h a s b ee n reduced by in tro d u c in g various c u ttin g co n stra in ts exploiting S M T line co nfigurations a n d consecutive processing of identical b o ard s as well as a spe
cific M P S scheduling m ode. T h e ap p ro ach can b e applied to a variety of different real-w orld assem bly line configurations a n d p ro d u c tio n scenarios w ith only sm all m odifications to th e co n s tra in t form ulations an d in p u t d a t a definitions, see [5, 6].
348 T. Sawik
M13' B12 M il Biq M9
..
B8__ IM7
B6
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O 250 500 750 1000 1250 1500 1750 2000 2250 2500 Cmax = 3247
Fig. 3. Batch schedule for SMT line with parallel stations
Rys. 3. Uszeregowanie partii wyrobów dla linii z maszynami równoległymi
R E F E R E N C E S
1. D ea n e R .H . an d M oon S.H.: W ork flow control in th e flexible flow line. In te rn a tio n a l Jo u rn a l o f Flexible M anufacturing System s, n o .3 /4 , 1992, p p .217-235.
2. H all N .G . a n d S risk a n d a ra ja h C.: A survey of m achine scheduling problem s w ith blocking an d no-w ait in process. Operations Research, vol.44, 1996, pp.510-525.
3. M cC orm ick, S .T ., P inedo, M .L., S henker, S. an d Wolf, B.: S equencing in an assem bly line w ith blocking to m inim ize cycle tim e. O perations Research, vol.37, 1989, p p .925-936.
4. Saw ik T .: M ixed integer p rogram m ing for scheduling flexible flow lines w ith lim ite d in te rm e d ia te buffers, M athem atical and C om puter M odelling, vol. 31, 2000, pp .3 9 -5 2 .
5. Saw ik T .: M ixed in teg er pro g ram m in g for scheduling surface m o u n t technology lines. In te rn a tio n a l Jo urnal o f P roduction Research, vol. 39, 2001, pp. 3219-3235.
6. Saw ik T ., S challer A. an d T irp a k T .M .: Scheduling of p rin te d w iring b o ard as
sem bly in surface m o u n t technology lines. Jo urnal o f E lectronics M anufacturing,
S cheduling B atch es of P rin te d W irin g B oards in S M T Lines 349
sp ecial issue on P roduction P lanning and Scheduling in Electronics M anufactur
ing, vol. 11, n o .l, 2002, pp. 1-17.
R ecenzent: D r hab.inż. M irosław Zaborow ski, Prof. Pol. Śl.
S t r e s z c z e n i e
W p ra c y przed staw io n o m odel program ow ania całkowitoliczbowego mieszanego do szeregow ania o p era cji m o n ta żu powierzchniowego k art elektronicznych w liniach S M T (ang. Surface M o u n t Technology). L in ia SM T zbudow ana je s t z szeregowo połączonych sta d ió w rozdzielonych buforam i m iędzyoperacyjnym i o ograniczonych p ojem nościach, z m aszynam i rów noległym i w niektórych stad iach . W y ró b wyko
n a n y w p ew nym sta d iu m m oże blokować m aszynę oczekując n a zwolnienie b ufora p rzed n a s tę p n y m sta d iu m . N ależy w yznaczyć n ajk ró tszy harm o n o g ram m ontażu w ielu p a r tii różnych ty p ó w w yrobów , gdzie w yroby jednego ty p u są m ontow ane kolejno, je d e n po d rugim . W m odelu m atem aty czn y m bufory trak to w a n e są jako do d atk o w e m aszyny z zerowym i czasam i w ykonyw ania wyrobów , lecz z możliwością blokow ania. B lokowanie tak iej m aszyny oznacza oczekiwanie przez w yrób w buforze. D o m odelu m atem aty czn eg o w prow adzono ta k ż e różne ograniczenia o d cin ają ce , k tó re w yznaczono an a liz u ją c typow e konfiguracje linii S M T oraz pew ne w łaściw ości uszeregow ań p a rtii w yrobów n a m aszynach równoległych. Zam ieszczone p rzy k ła d y liczbow e z rzeczyw istym i d anym i zaczerpniętym i z przem ysłu elektroni
cznego ilu s tru ją możliwość zastosow ania opracow anego m odelu m atem atycznego do w y zn aczan ia h arm o n o g ram ó w produkcji w elastycznych liniach m ontażow ych.
