A high IIP2 SAW-less superheterodyne receiver with multistage harmonic rejection
Madadi, I; Tohidian, M; Cornelissens, Koen; Vandenameele, Patrick; Staszewski, RB
DOI
10.1109/JSSC.2015.2504414 Publication date
2016
Document Version Final published version Published in
IEEE Journal of Solid State Circuits
Citation (APA)
Madadi, I., Tohidian, M., Cornelissens, K., Vandenameele, P., & Staszewski, RB. (2016). A high IIP2 SAW-less superheterodyne receiver with multistage harmonic rejection. IEEE Journal of Solid State Circuits, 51(2), 332-347. https://doi.org/10.1109/JSSC.2015.2504414
Important note
To cite this publication, please use the final published version (if applicable). Please check the document version above.
Copyright
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons. Takedown policy
Please contact us and provide details if you believe this document breaches copyrights. We will remove access to the work immediately and investigate your claim.
This work is downloaded from Delft University of Technology.
332 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016
A High IIP2 SAW-Less Superheterodyne Receiver
With Multistage Harmonic Rejection
Iman Madadi, Member, IEEE, Massoud Tohidian, Member, IEEE, Koen Cornelissens, Patrick Vandenameele,
and Robert Bogdan Staszewski, Fellow, IEEE
Abstract—In this paper, we propose and demonstrate the first
fully integrated surface acoustic wave (SAW)-less superheterodyne receiver (RX) for 4G cellular applications. The RX operates in discrete-time domain and introduces various innovations to simul-taneously improve noise and linearity performance while reducing power consumption: a highly linear wideband noise-canceling low-noise transconductance amplifier (LNTA), a blocker-resilient octal charge-sharing bandpass filter, and a cascaded harmonic rejec-tion circuitry. The RX is implemented in 28-nm CMOS and it does not require any calibration. It features NF of 2.1–2.6 dB, an immeasurably high input second intercept point for
closely-spaced or modulated interferers, and input third intercept point
of 8–14 dBm, while drawing only 22–40 mW in various operating modes.
Index Terms—Bandpass filter (BPF), charge-sharing,
discrete-time, IIP2, process-scalable, receiver, surface acoustic wave (SAW)-less, superheterodyne.
I. INTRODUCTION
C
ONVENTIONAL multiband, multistandard cellular receivers (RXs) require many external duplexers, surface acoustic wave (SAW) filters and switches, typically one per band, to attenuate out-of-band (OB) blockers before they reach the sensitive low-noise amplifier (LNA) input. In time-division duplexing (TDD) systems, external SAW filters can be eliminated if the RX chain can handle large interferers (e.g., 0 dBm at 20 MHz away from a GSM channel of interest [1]). On the other hand, for frequency-division duplexing (FDD) systems, the external SAW filters are responsible for not only the filtering of OB blockers but also for duplexing, i.e., separation of concurrent transmit (TX) and RX operations. To reduce cost and size of the total system solution, in which the external antenna interface network is nowadays the largest contributor, the recent trend is to eliminate SAW filters and switches by using a highly linear wideband RX [2]–[7]. As a consequence, the isolation of TX-to-RX and the suppression of TX interferers are worsening, which all further increase RX linearity requirements in FDD systems.Manuscript received May 18, 2015; revised August 21, 2015 and October 11, 2015; accepted November 12, 2015. Date of publication January 20, 2016; date of current version January 29, 2016. This work was supported in part by the EU ERC Starting Grant 307624. This paper was approved by Associate Editor Waleed Khalil.
I. Madadi and M. Tohidian are with Qualinx B. V. and Delft University of Technology, Delft, The Netherlands.
K. Cornelissens and P. Vandenameele are with M4S/Hisilicon, Leuven, Belgium.
R. B. Staszewski is with University College Dublin, Dublin, Ireland. He is also with Delft University of Technology, Delft, The Netherlands.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2015.2504414
Fig. 1. Comparison of conventional receiver architectures. (a) Zero-IF/low-IF. (b) Superheterodyne.
The resulting reductions in OB filtering imply tough IIP2 requirements (e.g., 90 dBm [7], [8]) for zero-IF (ZIF) and low-IF (Llow-IF) receivers. The IIP2 performance of such receivers depends mainly on the second-order nonlinearity of LNA and RF mixer in the receiver chain, as shown in Fig. 1(a). Since the typical IIP2 of an RF mixer is between 50 and 70 dB [9], ZIF/LIF receivers require highly sophisticated calibration algo-rithms [7], [10]–[15] to be frequently executed to account for variations in power supply [4], [16]–[20], process corner [20], temperature [21], mixer transistor’s gate bias [16], RF blocker frequency [14], [17], [19], [20], LO frequency [17], [19], [20], LO power [20], and channel frequency [21]. Also, the IIP2 cali-bration time is rather very slow and it needs to be run repeatedly due to environmental and operational changes [16].
Superheterodyne or high-IF (HIF) architectures, on the other hand, can have a theoretically infinite IIP2. As shown in Fig. 1(b), the desired signal and modulated blocker at the RF input will be down-converted to a higher IF and dc, respec-tively; thus, the modulated blocker can be completely filtered out by a bandpass filter (BPF) [22], [23]. For this reason, there is an increasing interest in uncalibrated high-IIP2 SAW-less 0018-9200 © 2015 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution
Fig. 2. State-of-the-art superheterodyne receivers.
superheterodyne RXs with integrated blocker-tolerant BPFs that are amenable to CMOS scaling.
This paper is organized as follows. An overview of wireless receivers is presented in Section II. In Section III, the gen-eral idea of the proposed RX with M/N -phase discrete-time (DT) operation is discussed. Section IV provides detailed analy-sis of the M/N -phase DT charge-sharing (CS)-BPF. Section V gives a description of a cascaded three-stage harmonic rejection (HR) circuitry. Design and implementation of the receiver chain are described in Section VI, with measurement results given in Section VII. Finally, the conclusion is drawn in Section VIII.
II. OVERVIEW OFSTATE-OF-THE-ARTWIRELESS RECEIVERS
The pioneers of RFIC integration have quickly realized the superiority of operating receivers at ZIF/LIF rather than at HIF: [24] simpler architecture, and a much higher level of mono-lithic integration as a result of using low-frequency low-pass filters (LPFs) for channel selection [see Fig. 1(a)]. This was despite the many issues associated with ZIF/LIF receivers: time-variant dc offsets, sensitivity to1/f (flicker) noise, large in-band LO leakage, and the second-order nonlinearity [2]–[7]. Those issues were viewed rather as an inconvenience and han-dled through various calibrations. However, high-performance cellular ZIF/LIF receivers now require extensive calibration efforts. For example, an intensive IIP2 calibration needs to be concurrently run in the background with dc offset and HR calibration [8], [18].
A superheterodyne architecture, shown in Fig. 1(b), pushes the IF frequency much higher such that the aforementioned problems are not a major concern anymore. Despite the obvious advantages, the superheterodyne radios have been abandoned for decades because it was extremely difficult to integrate a high quality (Q)-factor BPF for image rejection in CMOS using continuous-time (CT) circuitry [24].
The integration problem of HIF BPF was addressed in [25] [see Fig. 2(a)] utilizing an N-path filtering technique
[26]–[31]; and in [32] [see Fig. 2(b)], [33] using a discrete-time (DT) quadrature CS-BPF [34]–[36]. The N-path filter cannot reject images defined as blockers/interferers at harmon-ics of the IF frequency because it inherently features replicas there [25]. On the contrary, a transfer function (TF) of the DT CS-BPF has only one peak in the entire sampling frequency domain of−fs/2 to fs/2, which makes it a proper candidate as an integrated BPF for superheterodyne receivers [34]. The center frequency and bandwidth of the full-rate DT CS-BPF in [32] and [33] are precisely controlled via fs and capaci-tor ratios. Additionally, that filter comprises only transiscapaci-tors as switches and capacitors, which occupy a small area and follow the process scaling very well. Unfortunately, the CS-BPF in [32] and [33] has insufficient blocker rejection to support the SAW-less operation.
In this work, we propose the superheterodyne architecture shown in Fig. 3 that utilizes a novel charge-sharing BPF based on an M/N -phase signaling and an extra pole to improve filter-ing. Combined with a proposed highly linear wideband low-noise transconductance amplifier (LNTA) and cascaded HR stages, the first-ever SAW-less HIF (superheterodyne) RX is thus demonstrated. By exploiting two stages of the M/N -phase CS-BPF, the desired signal is amplified, while the images and in-band/OB blockers are progressively filtered out thoroughout the receiver chain.
As stated above, the proposed architecture has several key advantages compared to state-of-the-art LIF RXs. First, since its IF is high, the issues associated with LIF RXs are elimi-nated, specially IIP2 and the need for dc offset calibration. Also, 1/f noise is not a concern anymore, so the active IF amplifiers use minimum length transistors. Second, two stages of DT CS-BPF consist of only capacitors as information charge storage devices, and transistors as switches. All of this makes the struc-ture more compatible with the technology scaling. Moreover, the proposed RX offers the same level of monolithic integra-tion as LIF RXs without using any calibraintegra-tion. Furthermore, the proposed RX exhibits clear advantages over the traditional superheterodyne RXs, which are summarized below. First, it includes two stages of integrated blocker-tolerant complex
334 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016
Fig. 3. Proposed superheterodyne receiver architecture including two stages of CS-BPF filtering and three stages of HR.
image-reject CS-BPFs and three stages of HR circuitry. Second, since the center frequency (i.e., coinciding with the chosen IF) of the M/N -phase DT CS-BPF is well controlled by clock frequency and ratio of capacitors, the IF frequency could be changed, thus avoiding RX desensitization in face of extremely large blockers. Finally, the second mixer and baseband filters have moved to the digital domain after the ADC (external in this work); hence, they are ideal.
III. PROPOSEDSAW-LESSSUPER-HETERODYNE RECEIVER
Digital circuits benefit from process scaling in both speed and power consumption due to, respectively, the increase in transistor transit frequency fT and lowering of its dimensions with every finer process technology node. However, analog/RF circuitry is getting worse, except for LNAs,1because the thresh-old voltage Vth remains almost constant, while the supply
voltage VDD decreases. Also, the intrinsic gain and signal
swing are reduced. All of those make analog/RF circuitry not amenable to CMOS scaling [37]–[42].
One the other hand, the DT approach is based on build-ing blocks that scale very well: transistors actbuild-ing as switches, switched capacitors, inverter-based gm-cells, and digital clock generation circuitry. Hence, the RF performance improves with newer CMOS technology [32], [43]. These reasons motivate us to exploit the DT approach in the proposed SAW-less superheterodyne RX shown in Fig. 3.
The input voltage at the antenna is converted to current by LNTA and down-converted to HIF by DT sampling RF mixer, as shown in Fig. 3. The octal (i.e., eight-phase) mixer can be reconfigured to operate in the quadrature (i.e., four-phase) mode if the detected reception conditions are not demanding. After the mixer, the sampled down-converted signal is fed to the DT CS-BPF to attenuate images and OB blockers. To reduce
1LNA noise figure improves when f
Tincreases.
the power consumption of the first CS-BPF even further, the decimation by 2 can be performed by integrating two samples, thus giving rise to the antialiasing sinc-type TF. In addition to all advantages of the two-stage CS-BPF, each of them provides intrinsic 3rd/5th HR that can be further improved by turning
on the additional HR block. The second CS-BPF is cascaded via inverter-based gm-cells providing flicker-noise-free gain. The sufficient front-end filtering provided by the two-stage CS-BPF (unlike in [32]) allows to directly digitize the IF signal using a low-power ADC, and move the second mixer and baseband filtering into the digital domain. As calculated, a 10 bit 400 MS/s ADC should be sufficient after the two stages of CS-BPF filtering, while consuming less than 2 mW with state-of-the-art successive approximation register ADC [44]. Also, it should be mentioned that the IIP2 generated by ADC is not a concern because the ADC’s IM2 component is at dc and the desired signal is at IF. The only possible limitation on the IIP2 in the proposed receiver is the quantization noise of the second digital mixer, but it can be arbitrarily reduced by increasing its word length.
IV. DT M/N -PHASECS-BPF
The DT CS-BPF exhibits clear advantages over the tradi-tional types of filters, such as active-RC, N-path, gm-C, and biquad. The active-RC and gm-C filters are substantially noisier due to the noise contributions from opamp and gm compo-nents. Those components also generate flicker noise; thus to suppress it, their area needs to be very large. Furthermore, typ-ical IF and BB filters need to be reconfigurable, in which the required bandwidth scales over a decade. Since the bandwidth in active filters is determined by the RC or C/gmtime constant, the capacitors should be up to 50% larger to compensate for RC and gm-C mismatches. This contributes to their area disadvan-tage. As far as the N-path filters are concerned, they suffer from replicas at harmonics of their mixer switching frequency, while CS-BPF has only one peak in the entire sampling frequency.
Fig. 4. Evolution toward (f) M/N -phase CS-BPF (M= 8, N = 16), starting from (a) simplest 1st-order IIR LPF, then through (b)2nd-order IIR LPF, through
(c)4th-order IIR LPF, through (d) conventional CS-BPF, and finally through (e) 8/8-phase CS-BPF.
Also, in the traditional N-path filter, the stop-band rejection is severely limited by the switchON-resistance.
A. Conventional Quadrature CS-BPF
Fig. 4(a) shows the well-known DT IIR LPF [45]. The input current i, generated by a gm-cell, is integrated on the history
CH and rotating CR capacitors as the input charge packet
q0=nTs
(n−1)Tsi dt during ϕ1 over a time window Ts. At ϕ1
going inactive, CR samples a portion of the total “history” charge. As a result, the DT circuit illustrated in Fig. 4(a) has a1st-order IIR characteristic, with CRacting as a lossy com-ponent (termed “switched-capacitor resistor”). The order of the Fig. 4(a) DT IIR filter can be further increased to2ndor 4th, as shown in Fig. 4(b) and (c), respectively, or indefinitely beyond, as demonstrated in [46]. The conventional quadrature CS-BPF with a single real-valued output can be synthesized from the 4th-order DT IIR filter by applying input charge packets q
0,
q90, q180, and q270with a multiple of 90◦degree phase shifts, as shown in Fig. 4(d) [34]. By defining the complex-valued input constructed from two differential signals having the quadrature relationship, qI = q0− q180and qQ= q90− q270, the complex
TF of a conventional quadrature CS-BPF is derived as
H(z) = VqoI(z) + jVoQ(z) I(z) + jqQ(z) = k 1 − [a + j · (1 − a)]z−1 (1) where k = 1/(CH+ CR) (2) a = CH/(CH+ CR). (3) This TF has a1st-order complex BPF characteristic with its
peak located at fIF= fs 2πarctan 1 − a a . (4)
The filter comprises only capacitors and switching transis-tors. Its center frequency fIF only depends on the sampling frequency fs and capacitor ratios. Hence, it is fully amenable to process scaling.
B. 8/8-Phase CS-BPF
The filtering characteristic and tolerance to OB blockers of the conventional quadrature CS-BPF can be significantly enhanced by increasing the number of inputs, corresponding history capacitors, and digital clock phases to 8 (i.e., octal) or more. As an example of such a filter, the schematic of a 8/8-phase CS-BPF is proposed in Fig. 4(e), where it features eight inputs/outputs, eight history capacitors, and eight digital clock phases. The inputs, which are generated by the DT mixer for the first filter, are differential integrated charge packets q1, q2, q3, q4
336 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016
Fig. 5. Various full-rate M/N -phase CS-BPF configurations. (a) M/M-phase CS-BPF. (b) M/(2M)-phase CS-BPF. (c) M/N-phase CS-BPF.
that are phase shifted by 0, 45◦, 90◦, 135◦. As in the tradi-tional CS-BPF, CRshares the charge between various CHs. By defining the complex output voltage as
VoC = Vo,1+ ejπ/4Vo,2+ ejπ/2Vo,3+ ej3π/4Vo,4 (5) and complex input charge as
qiC = q1+ ejπ/4q2+ ejπ/2q3+ ej3π/4q4 (6)
and following the same approach as presented in [34], we find the complex TF of the 8/8-phase CS-BPF, driven by ideal input charge packets, as
H8/8(z) = VqoC(z) iC(z) =
k
(1 − az−1) − ejπ/4(1 − a)z−1 (7) where k and a are the same as in (2) and (3). The peak of the TF lies at fIF= 2πfsarctan (1 − a)sin(π/4) a + (1 − a)cos(π/4) . (8)
The 8/8-phase CS-BPF has a1st-order BPF characteristic
centered at fIF. In addition to the filtering improvement over
its conventional counterpart, this filter is capable of filtering images and OB blockers at3rd/5thLO harmonics. It should be noted that this filter still maintains the full compatibility with the technology scaling due to its DT passive nature.
C. 8/16-Phase CS-BPF
To further improve the filtering order and characteristics of the 8/8-phase CS-BPF, we propose to add an IIR LPF (of single or multiple poles) during the charge-sharing process in between every two adjacent inputs. As an example of such a filter, one LPF pole is added between each pair of adjacent input history capacitors CHin Fig. 4(f) to give rise to an 8/16-phase CS-BPF.
This filter has 8 inputs, 8 outputs, 16 CH’s (8 of them are input
CH’s), and 16 nonoverlapped clock phases with a duty cycle of 1/16. The input is interpreted as four differential charge pack-ets (q1, q2, q3, and q4) with multiples of 45◦degree phase shifts
provided by the DT mixer. The eight individual single-ended input charge packets are accumulated into their respective input
CH’s. At the end of each odd-numbered phase ϕ1, ϕ3, . . . ,ϕ15, the rotating capacitor CR samples a charge from the active
CH. In the following even-numbered phase of ϕ2, ϕ4, . . ., ϕ16,
CR containing the previous packet is charge-shared with a newly introduced history capacitor, termed “output CH,” which contains the intermediate (i.e., additionally LPF filtered) ver-sion of the “history” charge. Therefore, in each phase, CR removes a charge proportional to CR/(CH+ CR) from each
CH (whether input or output) and then delivers it to the next
CH. The newly introduced output history capacitors add sig-nificant extra filtering, thus improving blocker resiliency. They also provide convenient pick-up nodes for the dedicated output port that is now physically separate from the input.
In the above case, the 8/16-phase CS-BPF does not operate at the full rate and so all eight outputs can be read out at the maximum sampling rate of fs= 1/Ts= fLO. By defining the
VoC and qiC, the same as (5) and (6), the filtering TF of the filter driven by ideal charge packets, as shown in Fig. 4(f), can be proven to be H8/16(z) =VqoC(z) iC(z) = k · (1 − a)z−1 (1 − az−1)2− ejπ/4[(1 − a)z−1]2 (9) where k and a are the same as (2) and (3), respectively. We find the center frequency of the filter to be
fIF=2πfsarctan (1 − a) sin(π/8) a + (1 − a) cos(π/8) . (10)
D. Proposed GeneralM/N-Phase CS-BPF
Fig. 5 proposes various configurations of the single-stage full-rate CS-BPF: 1) without the additional LPF poles; 2) with one LPF pole; and 3) with X = (N/M − 1) LPF poles between the adjacent history capacitors. For extending the CS-BPF to a general form, we use the notation of “M/N -phase CS-BPF,” where it has M inputs, M outputs, N history capacitors, N nonoverlapped clock phases with a duty-cycle of D= 1/N, and X LPF poles in the charge-sharing loop. Inputs of the filter are interpreted as differential charge packets, q1, q2, . . ., qM/2 that are phase shifted by 0, 2π/M, 4π/M, . . ., (M − 2)π/M radians, and for the first CS-BPF, provided by the M -phase DT mixer.
To summarize, the blocker-resilient 8/16-phase CS-BPF fea-tures a sharp and highly linear TF to filter images and OB blockers even at3rd/5thharmonics of LO. The OB filtering of
blockers is improved significantly compared to [32] and [34] by increasing the number of input phases of CS-BPF and adding the LPF pole between each pair of adjacent input history capac-itors. The center frequency of the filter is fully controllable by the capacitance ratios and sampling frequency, thus mak-ing it insensitive to PVT. The only possible concern in the future CMOS nodes would be a degradation of metal-oxide-metal (MOM) capacitor matching for constant capacitance units, which become more dense and thus more mismatched due to the metal stack becoming more compressed. This would normally prevent aggressive area scaling of MOM capacitors. However, this architecture employs charge-sharing rotation that acts akin to dynamic weighted averaging (DWA), thus making it robust to capacitor mismatches. Simulations reveal that folded images are below−120 dB (normalized to the TF peak) even in face of a 50% capacitor mismatch.2 Therefore, the capaci-tor mismatch degradation in the advanced CMOS technologies would be insignificant in the CS-BPF.
To support the full-rate operation, parallelism/interleaving techniques are used to increase the sampling frequency to fs=
MfLO[34]. As in any sampling system, frequency components at fs± fIFare folded to the desired frequency at IF. Therefore, larger M increases fs, thus pushing away the closest fold-ing frequencies. Similarly, increasfold-ing M improves the CS-BPF tolerance to blockers but at the same time introduces more complexity and power consumption in the full-rate mode, i.e., without any decimation.
To investigate the TF of full-rate M/N -phase CS-BPF, the time-domain output voltage expressions at t= nTs, where
Ts= 1/fs, can be derived as
Vi,1[n] = CHVi,1[n − 1] + CRVo,X,M/2[n − 1] + 2q1[n]
CH+ CR
(11)
2Note that the MOM capacitor mismatch in this design is merely 0.03%– 0.1%.
Fig. 6. Ideal TF of M/N -phase CS-BPF.
Vi,h[n] = CHVi,1[n − 1] + CCRVo,X,h−1[n − 1] + 2qh[n] H+ CR
(12)
Vo,2,j[n] = CHVo,2,j[n − 1] + CC RVi,j[n − 1]
H+ CR (13)
Vo,l,j[n] = CHVo,l,j[n − 1] + CC RVo,l−1,j[n − 1]
H+ CR (14)
where i ∈ [1, M/2], j ∈ [1, M/2], h ∈ [2, M/2], and
l ∈ [3, X]. By performing a conversion from time-domain
to z-domain, the general TF and center frequency can be derived as fIF≈ 2πfsarctan (1 − a) sin(2π/N) a + (1 − a) cos(2π/N) (16) where k and a are the same as (2) and (3), respectively. The simulated and calculated normalized complex TFs are plotted in Fig. 6 for the conventional (i.e., 4/4-phase), 8/8-, 8/16-, and 16/32-phase CS-BPF with the following conditions: CR= 1 pF and fs= 8 GHz, and the same IF frequency (fIF= 15 MHz). The switch resistance is assumed to be sufficiently small. Most notably, the filtering characteristic of the M/N -phase filter is improved substantially for higher M . Filter’s rejection for far-out frequencies depends on its order. Since both 8/16- and 16/32-phase CS-BPFs have a 2nd-order characteristic, they
have the same rejection at far-out frequencies. Nevertheless, the close-in rejection of the 16/32-phase filter is higher than that of 8/16-phase. Also, the calculated TF based on (15), shown at the bottom of the page, agrees well with simulations.
V. HARMONICREJECTION
The differential mixer driven by a square-wave clock is a lin-ear time-variant circuit that down-converts the desired signal
HM/N(z) = M/2 l=1(Vo,X,l(z))e j(2l−2)π/M M/2 l=1(ql(z))e j(2l−2)π/M = k · ((1 − a)z−1) N M−1 (1 − az−1)N/M − ej2π/M((1 − a)z−1)N/M (15)
338 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016
Fig. 7. Concept of (a) multistage phase-frequency controlled system; (b) multistage PCF.
Fig. 8. (a) Proposed HR stages in the superheterodyne receiver. (b) Harmonic rotation vectors. (c) Harmonics cancellation summation.
together with undesired interferers at higher LO harmonics. In narrow-band receivers, those interferers are not of a major con-cern because of a customary RF band filtering right after the antenna. In wideband RF receivers, such RF band select filter-ing would be very difficult, so it is the LO harmonics instead that need to get rejected. The required level of LO HR is 60– 100 dB, which is almost impossible with only one HR stage due to practical amplitude and phase mismatches. A two-stage HR
was introduced in [47], but it prevents further HR improvements because of the nonredundant (i.e., quadrature) signal represen-tation. In this section, we propose a mismatch insensitive HR concept that can be arbitrarily cascaded without any bound on the HR capability.
Fig. 7(a) starts with a high-level model of a multistage phase-frequency control system. Its key feature is that the harmonic TF depends on both the input frequency f and phases φi, i =
Fig. 9. TFs of 8/16-phase CS-BPF for different harmonics, both calculated and simulated. 0, 1, 2, . . .. Multiple phases φi can be generated with an M
-phase mixer, shown in Fig. 7(b), which not only down-converts the desired signal at the fundamental but also does the inter-ferers at higher 3rd, 5th, . . ., nth LO harmonics to the same
IF frequency with multiple phases of |ϕi| = (i − 1) × 2π/M where i= 1, 2, . . ., M. Therefore, instead of storing the har-monic information in the frequency domain, as is the case before the mixer (f1, f3, f5, . . ., fn), it is now stored as phases in the M mixer output lines, with M >4 to ensure redundancy, where it will be preserved as long as the number of lines is maintained. The multiple phases in M lines can be processed by the phase-controlled filter (PCF) leading to a different TF for every harmonic.
A. CS-BPF Harmonic Rejection Concept
In our implementation, the PCF HR circuitry consists of three stages in total, as shown in Fig. 8. It includes two stages of CS-BPFs. Although the1st and3rd/5th input harmonics are
down-converted to the same IF frequency by the octal mixer, the phase difference between two adjacent lines for the1stand
3rd/5thharmonics are π/4 and (−3π/4)/(5π/4), respectively.
The charge-sharing phases of the signal for the 1st (blue),
3rd (red), and5th (purple) harmonics are shown in Fig. 8(a).
Assuming that the even harmonics are removed due to the differential configuration, the phase difference of odd harmon-ics is sensed by CS-BPF, so the general harmonic TF of the
M/N-phase CS-BPF and ϕican be found as
H(z, ϕi) = 1/(CR+ CH) ·
(1 − a)z−1 N/M−1
(1 − az−1)N/M − ejϕi· [(1 − a)z−1]N/M (17)
ϕi= (−1)i−12 × i × 2π/M (18)
respectively, where i∈ [1, 2, . . ., n] and a is equal to (3). Fig. 8(b) shows the corresponding arrangement of phase rota-tion vectors. The HR for 3rd/5th harmonics is ∼22 dB for
each CS-BPF, which can be infinitely improved by cascading CS-BPFs since the octal format fully preserves the harmonic information.
HR is further improved by the proposed “stage-2” HR block. It consists of four X1 blocks, each comprising three identical
Fig. 10. Harmonic rejection of 8/16-phase CS-BPF for different harmonics versus M .
gm-cells adding three adjacent vectors. This results in amplifi-cation of the1st and partial rejection of the3rd/5th harmonic
vectors, as shown in Fig. 8(c). The two proposed techniques are mismatch insensitive and do not require any calibration, whereas other well-known approaches, such as HR-mixers [4], [47]–[50], suffer from such sensitivity, so they require exten-sive calibration. Also, HR-mixers and switch-capacitor HR [51] cannot be further enhanced because the combined output sig-nals are converted to I/Q (quadrature), thus causing irreversible aliasing of the harmonic phase information.
The simulated normalized TFs of the1st, 3rd and5th
har-monics are compared in Fig. 9 with calculations based on (17). The following conditions apply: CR= 1 pF, CH = 31.4 pF, and fs= 8 GHz. The plots verify that the 3rd and 5th harmonics are attenuated by 22 dB. Furthermore, based
on (17), the3rd, 5th, and7th HR levels are plotted in Fig. 10
versus the number of inputs M for the M/2M-phase CS-BPF. The conditions are: CR= 1 pF, CH = 31.4 pF, and fs=
M×1 GHz.
VI. DESIGN ANDIMPLEMENTATION OF THE RECEIVERCHAIN
We have described so far the evolution of the M/N -phase CS-BFP toward its full exploitation as an image reject
340 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016
Fig. 11. Clock generation block diagram.
filter in the fully integrated SAW-less discrete-time super-heterodyne receiver. In this section, we describe the detailed design implementation of the receiver, starting with various operational modes of the fully reconfigurable M/N -phase CS-BPF.
A. 4/16-Phase and 8/16-Phase CS-BPFs
The two implemented CS-BPF filters are each programmed as either quadrature (4/16-phase) or octal (8/16-phase). In either mode, the filter is clocked by 16 nonoverlapped signals with
D = 1/16 and the filter’s center frequency is located at IF with
no replicas present. The 16 history CH and 16 rotating, CR capacitors in the full-rate CS-BPFs shown in Fig. 5(b) and (c) are actually eight differential capacitors each, in order to save the chip area by×4. Also, due to the differential imple-mentation, common-mode voltage and even-order nonlinearity of the prior stages are canceled out. CH and CR are digitally tunable with 8-bit binary-weighted codes to support variable IF of−10 MHz up to −90 MHz for GSM.
B. Clock Generation Circuitry
Block diagram of the clock generation is shown in Fig. 11. An external sinusoidal input is converted to a 50% duty-cycle clock after passing through the input buffer. It drives three clock generation circuits. The first circuit provides all the clock phases required for the RF mixer, while the remaining two provide all the clock phases for the CS-BPFs. All three circuits are independently programmable to operate in either the octal or quadrature mode. In these modes, the mixer clock generation has a respective output duty-cycle of 12.5% and 25%, while the clock for both CS-BPFs is always at D= 6.25%, as shown in Fig. 11. To be able to further save dissipated power, the dividers are used to enable decimation by 1, 2, or 4 for both CS-BPF stages.
Functional block diagram of the clock generation circuitry for the mixer and the two CS-BPF stages is the same. Fig. 12 shows an example of the mixer LO generation. TheCK and CK input clocks with D= 50% are driving eight and four dynamic latches connected back-to-back in a loop for the octal and quadrature modes, respectively. The latch outputs are followed by digital gates, which produce 12.5% (octal) and 25% (quadra-ture) duty-cycle clocks. The final output is selected between the octal or quadrature outputs by eight multiplexers. Therefore, in the quadrature mode, half of the mixer switches areOFF.
Fig. 12. Functional block diagram of the mixer clock generation for both octal and quadrature modes.
The effect of LO phase noise or jitter on the switched-capacitor circuits has been discussed in detail in [52]–[54]. Ref. [54] shows that switched-capacitor filters are robust to many nonidealities, such as charge injection, nonzero rise/fall times of the clock, and switch resistance. They are exception-ally robust to clock jitter and there is no need for a special clocking scheme, such as bootstrapped driving and dummy switches. The same applies to passive switched-capacitor filters and, by extension, to CS-BPFs.
C. Low-Noise Transconductance Amplifier
Fig. 13(a) shows a fully differential schematic of the pro-posed LNTA, which simultaneously features low NF and high IIP3 (only single-ended signal waveforms are shown). The noise-canceling common-gate transistors (Mn1/Mn2) pro-vide the RX input matching. The noise-canceling operation is as follows. The input signal gets amplified by transistors
Mn1/Mn3 and Mp1 in a differential feed-forward manner, whereas the thermal noise of Mn1channel experiences subtrac-tion at the output nodes because of the out-of-phase correlated noise voltages at Vx and Voutn. The 3rd-order
nonlinear-ity of Mn1 and Mn3 can be simultaneously canceled at the differential output because Mn1and Mn3 operate in weak and saturation regions, respectively, resulting in out-of-phase gm3 (3rd-order transconductance) to each other. Therefore, partial
cancellation of the IM3 component happens at the differen-tial output. The cancellation happens at the desired frequency because at other frequencies, an additional IM3 is generated due to the2nd-order nonlinearity of M
n3. Simulated (with extracted parasitics) NF and gain of LNTA with a resistive load is shown in Fig. 13(b) across 0.1– 4 GHz.
Fig. 13. (a) LNTA schematic. (b) Its post-layout simulated noise figure and gain.
Fig. 14. (a) Simplified block diagram of the RX front-end. (b) Simulated LNTA output impedance when the CS-BPF isON/OFF.
Fig. 14 shows the simplified block diagram of the RX front-end and simulated impedances at the LNTA output. The composite impedance load Zout seen by the LNTA is
com-prised of its own intrinsic output impedance, Zo, in parallel with a load provided by the mixer and CS-BPF, ZCS. Since Zo (~ 350 Ω) is several times (>2.5x) higher than ZCS (140 Ω peak), the mixer is considered to be operating in a current com-mutating mode [55], rather than in a voltage mode. As a result, the effect of the on-resistance of the mixer switches is also minimized.
D. IF Stage Transconductance Amplifier (gm-cell)
Fig. 15 shows a schematic of the pseudo-differential inverter-based IF transconductance amplifier with a common-mode
Fig. 15. IF gm-cell schematic with common-mode rejection load.
(CM) rejection load. The gm-cell operates at 0.9 V supply and a pair of complementary thick-oxide PMOS/NMOS tran-sistors is utilized to increase the transconductance linearity to
> +11 dBm (simulated) for all corner cases within a
tem-perature range of –30◦C to 100◦C [56]. The common-mode feedback circuitry provides a proper bias of VDD/2 to the
outputs.
To suppress any possible CM oscillation in the RX chain, the CM gain of the gm-cell is drastically reduced by placing a CM load at its output. It features different impedances for the CM and differential-mode (DM) signals. The impedance for DM signals is very high; it is proportional to the small-signal drain resistance of the CM load transistors Mn and
Mp, while the impedance for CM signals is very low, equal to 1/((gmn+ gmp)A), where gmn and gmpare the small-signal transconductance of Mnand Mp.
VII. MEASUREMENTRESULTS
Fig. 16 shows the chip micrograph of the proposed super-heterodyne RX for 4G cellular mobiles realized in TSMC 28 nm CMOS [57]. The active area is 0.52 mm2, which is
mostly occupied by CHand CRcapacitors of the two CS-BPFs. Both the RX and clock inputs are differential and so “hybrids” are used to interface with 50-Ω single-ended instrumentation. The chip is wire-bonded to a PCB and the characteristics of
342 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016 LNTA First CS-BPF RF mixer gm -Cells Second CS-BPF CLK gen
Fig. 16. Chip micrograph of the proposed discrete-time superheterodyne receiver.
Fig. 17. Measured RX TF for different bands.
PCB lines and cables are de-embedded from the measure-ment’s results. All the measurements are performed at high RX gain without any calibrations, even those concerning the linearity.
The RX is fully characterized in “2G 5” and “3G band-1,” as representatives of GSM and PCS bands, respectively, but it is fully functional in the entire 0.5–2.5 GHz RF input frequency range. The measured normalized TFs are shown in Fig. 17 for GSM, PCS, and LTE bands with 0.85, 2.1, and 2.5 GHz RF input frequencies. The RX bandwidth is 6.5 MHz for 2G/3G and 20 MHz for LTE, while IF frequency is−15 and
−35 MHz for 0.85–2.1 GHz and 2.5 GHz carriers, respectively.
Also, the absolute value of IF in the proposed RX can be vari-able in a face of large blocker, within the range of 10–90 MHz, 25–220 MHz, and 29–262 MHz for 2G, 3G, and LTE bands, respectively.
Fig. 18 shows the RX gain at 0.85 and 2.1 GHz carriers for
I channel only. By recombining the I/Q channels, an extra
6 dB gain can be obtained. The overall pass-band gain of LNTA and 1st CS-BPF in GSM and PCS bands is around 18 and 17.5 dB, respectively. The gain of IF gm-cell and2ndCS-BPF
is measured by subtracting the total RX gain from the gain pro-vided by LNTA and1st CS-BPF. That peak gain value is 17
and 16.5 dB for 2G and 3G, respectively. The total RX gain is between 29 and 35 dB for 0.85–2.5 GHz carriers. Although the 1stand2ndCS-BPFs are identical, the former shows a sharper
filtering characteristic due to a larger output resistance of LNTA versus that of IF gm-cell.
The comparisons of measured TFs of LNTA and 1st
CS-BPF with calculations per (17) are shown in Fig. 19(a) and
(b), respectively, for 3rd and 5th harmonics. The difference
between the measured and calculated1stharmonic at IF is due to the effect of LNTA output impedance. The 19-dB rejection of3rdand5thharmonics per each CS-BPF stages is measured at IF.
The measured wideband TFs in the normal and HR modes for three ICs is shown in Fig. 20. All the images are rejected by more than 65 dB, including the IF image, in all three mea-sured ICs without any calibration. The worst-case HR of 58 dB is achieved when the HR-block is ON: 40 dB from the two-stage CS-BPFs, 15 dB from the HR-block, and the rest from the LNTA’s finite bandwidth. The highlighted images are multiples of smallest LO frequency in the clock generation circuitry with an offset of±fIF.
Fig. 21 plots the measured receiver NF of 2.1–2.6 dB with an LO frequency of 865, 2115, and 2535 MHz for 2G, 3G, and LTE, respectively. The minimum noise figure in each standard happens at the center frequency of CS-BPFs, which coincides with the IF location. Also, the NF contribution of each building block is summarized in Table I for GSM an PCS bands.
The simulated (post-layout extracted) OB-IIP3 of CS-BPF is more than +30 dBm. Furthermore, because of its strong blocker filtering, OB-IIP3 is mainly determined by the linearity of LNTA. Fig. 22 shows the measured OB-IIP3 of the RX ver-sus offset frequency for 2G and 3G. It should be mentioned that the linearity was measured at the maximum gain (i.e., the lowest noise figure) and without any calibration. The variation in OB-IIP3 over offset frequency is due to the linearity dependency of LNTA on the offset frequency. The peak IIP3 of +14 dBm is achieved for the offset frequencies specified by the 2G/3G standards at duplex (fTX) and half duplex ((fTX+ fRX)/2)
frequencies.
For IIP2 measurements, we consider two separate test cases: 1) closely spaced tones or a modulated single tone IIP2 test
case (limited by the mixer’s IIP2);
2) far away two-tone test case (limited by the LNA’s IIP2)
The first test case is a strong impediment to the removal of the SAW filter at the front of RF chain. The required IIP2 would be more than +90 dBm. The second test case is additionally applicable to wideband RXs, but it is less stringent. To calculate the needed IIP2, let us assume the blocker level of−32.5 dBm applied to the RX for the required sensitivity of−99 dBm and SNR of 9 dB to maintain signal purity. The IM2 component should be below −108 dBm. Therefore, the needed IIP2 is +43 dBm. To clarify the situation, both IIP2 test cases are measured.
For the first test case, since the RX architecture is super-heterodyne with an fIF of −15 to −35 MHz, the applied
closely spaced two-tone or single modulated tone with 15 MHz
bandwidth will be down-converted to around dc, thus
com-pletely filtered out. This case has been measured when the RX
is in high-gain mode, and unsurprisingly, the only phenomenon observed was the instrument’s noise floor.
For the second test case, the two tones are far away from each other but the generated IM2 by the LNTA is in-band.
Fig. 18. Measured RX gain versus output frequency.
Fig. 19. Comparison of the normalized measured1st, 3rdand5thharmonic TF with calculation for GSM band. All TFs are normalized to maximum gain of1st
harmonic extracted from the calculation.
Fig. 20. Measured wideband TF of the complete RX (fRF= 860MHz).
In our tests, the two tones are located at fRF+spacing and
2fRF+spacing, while fRF is 860 MHz in GSM. As shown
in Fig. 23, IIP2 of better than +50 dBm is achieved when the LNTA is set to mid-gain (the standard allows for a gain relaxation there).
The RX blocker tolerance is demonstrated by means of “NF under blocker” tests. Special attention to the purity of the large blocker signal is paid in these measurements: an external BPF
is added to the RF blocker source to eliminate its phase noise components falling within the RF signal band, thus preventing reciprocal mixing from inadvertently increasing the measured NF. Fig. 24 shows the RX NF measurement versus the blocker power at 20 and 80 MHz offsets for PCS and GSM bands when the LNTA is in mid- and high-gain modes, respectively. For the PCS band,−12 dBm blocker at 20 MHz and 0 dBm blocker at 80 MHz offsets increase the measured NF to 7.2 and
344 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016
Fig. 21. Measured noise figure for GSM, PCS, and LTE bands.
TABLE I
NOISEFIGURECONTRIBUTION OFEACHBUILDINGBLOCK IN
THERX CHAIN
Fig. 22. Measured IIP3 for (a) GSM and (b) PCS bands versus frequency offset.
14 dB, respectively, while for the GSM band, the blocker NF of 17.4 dB is achieved for a 0 dBm blocker at 20 MHz offset. The RX passes all GSM and PCS bands requirements except for those with a 0 dBm blocker NF at 20 MHz offset. The excessive rise of NF at the 0 dBm blocker is mainly due to the LNTA’s
Fig. 23. Measured IIP2 for the far away two-tone test case at fRF+spacing and 2fRF+spacing. fRFis 860 MHz.
Fig. 24. Measured OB blocker noise figure for GSM and PCS bands.
cascode structure that operates at a very low VDD= 0.9 V sup-ply due to I/O constraints in our testchip. Using I/O transistors at 1.8 or 2.5 V supply should add enough headroom to eliminate this linearity issue.
The measured power consumption of the RX chip versus input frequency is shown in Fig. 25. The overall RX power consumption varies from 22 to 40 mW dependent on input RF band and related clock frequency. The main contributor to the overall RX power is analog part for GSM band. As the clock frequency increases for PCS band, the main contributor is the power consumed by DT part including RF mixer, CS-BPF1, CS-BPF2, and clock buffers and dividers.
Table II compares the proposed DT RX with state-of-the-art RXs. While being the best-in-class in meeting the key performance parameters without any calibration, its power consumption and area are generally the lowest, and it does not suffer from any issues related to dc offsets, flicker noise, or IM2 products since its IIP2 is immeasurably high for closely spaced or single modulated interferers.
VIII. CONCLUSION
We have proposed and demonstrated a new architecture of a discrete-time superheterodyne receiver targeting a SAW-less
Fig. 25. Measured RX power consumption for (a) GSM (fRF= 860 MHz). (b) PCS (fRF= 2.1 GHz) carriers.
TABLE II
PERFORMANCESUMMARY ANDCOMPARISONWITHSTATE-OF-THE-ART
∗Worst-case without calibration and measured three IC samples,$with calibration,due to an IF mixer (second Mixer),†with
optimized setting
#1-dB typical input balun loss should be included in TDD mode for RXs with differential inputs
§Not applicable, because for the closely-spaced two-tone test or modulated blocker, the superheterodyne architecture generates IM2
far outside of IF
πBlocker at 80 MHz offsetξBlocker at 20 MHz offset.
operation of the 4G cellular standard. The consequence of reduced filtering at the antenna interface network forces much better linearity and filtering of the on-chip RF front-end. Consequently, the LNA is made wideband with a new noise
cancellation scheme. The RF mixer and two stages of bandpass filtering are octal, which provides strong filtering and allows to naturally reject input harmonics. The architecture is realized in 28 nm CMOS and is amenable to further scaling.
346 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016
ACKNOWLEDGMENT
The authors would like to thank Atef Akhnoukh, and espe-cially Wil Straver from TUDelft and P. Vanbekbergen and P. Stynen from M4S/Hisilicon for their support.
REFERENCES
[1] “Digital cellular telecommunications system (Phase 2+); Radio transmis-sion and reception,” Std. (3GPP TS 45.005 vertransmis-sion 11.2.0 Release 11), 2013.
[2] I. Fabiano, M. Sosio, A. Liscidini, and R. Castello, “SAW-less analog front-end receivers for TDD and FDD,” IEEE J. Solid State Circuits, vol. 48, no. 12, pp. 3067–3079, Dec. 2013.
[3] M. D. Tsai, C. F. Liao, C. Y. Wang, Y. B. Lee, B. Tzeng, and G. K. Dehng, “A multi-band inductor-less SAW-less 2G/3G-TD-SCDMA cellular receiver in 40 nm CMOS,” in IEEE Int. Solid State Circuits Conf.
(ISSCC) Dig. Tech. Papers, 2014, vol. 57, pp. 354–355.
[4] B. Van Liempd et al., “A 0.9 V 0.4-6 GHz harmonic recombination SDR receiver in 28 nm CMOS with HR3/HR5 and IIP2 calibration,” IEEE J.
Solid-State Circuits, vol. 49, no. 8, pp. 1815–1826, Aug. 2014.
[5] D. Murphy, H. Darabi, and H. Xu, “A noise-cancelling receiver resilient to large harmonic blockers,” IEEE J. Solid-State Circuits, vol. 50, no. 6, pp. 1336–1350, Jun. 2015.
[6] D. Murphy et al., “A blocker-tolerant, noise-cancelling receiver suitable for wideband wireless applications,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2943–2963, Dec. 2012.
[7] D. Kaczman et al., “A single-chip 10-band WCDMA/HSDPA 4-band GSM/EDGE SAW-less CMOS receiver with DigRF 3G interface and +90 dBm IIP2,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 718–739, Mar. 2009.
[8] B. Debaillie, P. Van Wesemael, G. Vandersteen, and J. Craninckx, “Calibration of direct-conversion transceivers,” IEEE J. Sel. Topics Signal
Process., vol. 3, no. 3, pp. 488–498, Jun. 2009.
[9] S. Chehrazi, A. Mirzaei, and A. Abidi, “Second-order intermodulation in current-commutating passive FET mixers,” IEEE Trans. Circuits Syst. I, vol. 56, no. 12, pp. 2556–2568, Dec. 2009.
[10] E. E. Bautista, B. Bastani, and J. Heck, “High IIP2 downconversion mixer using dynamic matching,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1934–1941, Dec. 2000.
[11] M. Brandolini, P. Rossi, D. Sanzogni, and F. Svelto, “A +78 dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 552–559, Mar. 2006.
[12] H. Darabi, H. J. Kim, J. Chiu, B. Ibrahim, and L. Serrano, “An IP2 improvement technique for zero-IF down-converters,” in IEEE Int.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2006, vol. 38,
pp. 171–174.
[13] I. Elahi and K. Muhammad, “IIP2 calibration by injecting DC offset at the mixer in a wireless receiver,” IEEE Trans. Circuits Syst. II, vol. 54, no. 12, pp. 1135–1139, Dec. 2007.
[14] K. Dufrene and R. Weigel, “A novel IP2 calibration method for low-voltage downconversion mixers,” in Proc. IEEE Radio Freq. Integr.
Circuits Symp., no. 1, 2006, pp. 292–295.
[15] Q. Huang et al., “A tri-band SAW-less WCDMA/HSPA RF CMOS transceiver with on-chip DC-DC converter connectable to battery,” in
IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2010,
vol. 53, pp. 60–61.
[16] Y. Feng, G. Takemura, S. Kawaguchi, N. Itoh, and P. Kinget, “A low-power low-noise direct-conversion front-end with digitally assisted IIP2 background self calibration,” in IEEE Int. Solid-State Circuits Conf.
(ISSCC) Dig. Tech. Papers, 2010, pp. 70–71.
[17] K. Dufrêne, Z. Boos, and R. Weigel, “A 0.13µm 1.5V CMOS I/Q down-converter with digital adaptive IIP2 calibration,” in IEEE Int. Solid-State
Circuits Conf. (ISSCC) Dig. Tech. Papers, 2007, pp. 86–87.
[18] B. Van Liempd, J. Borremans, S. Cha, E. Martens, H. Suys, and J. Craninckx, “IIP2 and HR calibration for an 8-phase harmonic recom-bination receiver in 28 nm,” in Proc. IEEE Custom Integr. Circuits Conf., 2013, pp. 2–5.
[19] K. Dufrêne, Z. Boos, and R. Weigel, “Digital adaptive IIP2 calibration scheme for CMOS downconversion mixers,” IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 2434–2445, Nov. 2008.
[20] Y. Feng, G. Takemura, S. Kawaguchi, N. Itoh, and P. R. Kinget, “Digitally assisted IIP2 calibration for CMOS direct-conversion receivers,” IEEE J.
Solid-State Circuits, vol. 46, no. 10, pp. 2253–2267, Oct. 2011.
[21] M. Chen, Y. Wu, and M. F. Chang, “Active 2nd-order intermodulation cal-ibration for direct-conversion receivers,” in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, 2006, pp. 1830–1839.
[22] L. Longo, R. Halim, B.-R. Horng, K. H. K. Hsu, and D. Shamlou, “A cellular analog front end with a 98 dB IF receiver,” in IEEE Int.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 1994, pp. 226–227.
[23] A. Hairapetian, “An 81-MHz IF receiver in CMOS,” IEEE J. Solid-State
Circuits, vol. 31, no. 12, pp. 1981–1986, Dec. 1996.
[24] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, 2nd ed., Cambridge University Press, 2004.
[25] A. Mirzaei, H. Darabi, and D. Murphy, “A low-power process-scalable super-heterodyne receiver with integrated high-Q filters,” IEEE J.
Solid-State Circuits, vol. 46, no. 12, pp. 2920–2932, Dec. 2011.
[26] L. E. Franks and I. W. Sandberg, “An alternative approach to the realiza-tion of network transfer funcrealiza-tions: The N–Path filter,” Bell Syst. Tech. J., vol. 39, no. 5, pp. 1321–1350, 1960.
[27] A. Mirzaei, H. Darabi, and D. Murphy, “Architectural evolution of inte-grated M-phase high-Q bandpass filters,” IEEE Trans. Circuits Syst. I, vol. 59, no. 1, pp. 52–65, Jan. 2012.
[28] A. Mirzaei, X. Chen, A. Yazdi, J. Chiu, J. Leete, and H. Darabi, “A fre-quency translation technique for SAW-less 3G receivers,” in Proc. Symp.
VLSI Circuits, 2009, no. 949, pp. 280–281.
[29] A. Ghaffari, E. A. M. Klumperink, M. C. M. Soer, and B. Nauta, “Tunable high-Q N-Path band-pass filters: Modeling and verification,”
IEEE J. Solid-State Circuits, vol. 46, no. 5, pp. 998–1010, May
2011.
[30] M. Darvishi, R. Van Der Zee, E. A. M. Klumperink, and B. Nauta, “Widely tunable 4th order switched GM-C band-pass filter based on N-path filters,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 3105–3119, Dec. 2012.
[31] M. Darvishi, R. Van Der Zee, and B. Nauta, “Design of active N-path filters,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 2962–2976, Dec. 2013.
[32] M. Tohidian, I. Madadi, and R. B. Staszewski, “A fully integrated highly reconfigurable discrete-time superheterodyne receiver,” in IEEE Int.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2014, pp. 72–74.
[33] I. Madadi, M. Tohidian, and R. B. Staszewski, “A 65 nm CMOS high-IF superheterodyne receiver with a high-Q complex BPF,” in Proc. IEEE
Radio Freq. Integr. Circuits Symp., 2013, pp. 323–326.
[34] I. Madadi, M. Tohidian, and R. B. Staszewski, “Analysis and design of I/Q charge-sharing band-pass-filter for superheterodyne receivers,” IEEE
Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 8, pp. 2114–2121, Aug.
2015.
[35] S. Karvonen, T. A. D. Riley, and J. Kostamovaara, “A CMOS quadrature charge-domain sampling circuit with 66-dB SFDR up to 100 MHz,” IEEE
Trans. Circuits Syst. I, vol. 52, no. 2, pp. 292–304, Feb. 2005.
[36] S. Karvonen, T. A. D. Riley, S. Kurtti, and J. Kostamovaara, “A quadra-ture charge-domain sampler with embedded FIR and IIR filtering func-tions,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 507–515, Feb. 2006.
[37] E. Morifuji et al., “Future perspective and scaling down roadmap for RF CMOS,” in Symp. VLSI Technol. Dig. Tech. Papers, 1999, pp. 163–164. [38] C. Yue and S. Wong, “Scalability of RF CMOS,” in IEEE Radio Freq.
Integr. Circuits Symp. Dig. Papers, 2005, pp. 53–56.
[39] K. Lee et al., “The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application,” IEEE Trans. Electron
Devices, vol. 52, no. 7, pp. 1415–1422, Jul. 2005.
[40] L. Tiemeijer et al., “Record RF performance of standard 90 nm CMOS technology,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2004, pp. 441–444.
[41] P. H. Woerlee et al., “RF-CMOS performance trends,” IEEE Trans.
Electron Devices, vol. 48, no. 8, pp. 1776–1782, Aug. 2001.
[42] C. H. Diaz, D. D. Tang, and J. Y. C. Sun, “CMOS technology for MS/RF SoC,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 557–566, Mar. 2003.
[43] R. B. Staszewski et al., “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS,” IEEE J.
Solid-State Circuits, vol. 39, no. 12, pp. 2278–2291, Dec. 2004.
[44] B. Verbruggen et al., “A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28 nm digital CMOS,” in Proc.
Symp. VLSI Circuits (VLSIC), 2013, pp. C268–C269.
[45] G. Hueber and R. B. Staszewski, Multi-Mode/Multi-Band RF Transceivers for Wireless Communications: Advanced Techniques, Architectures, and Trends, Wiley, 2011.
[46] M. Tohidian, S. Member, and I. Madadi, “Analysis and design of a high-order discrete-time passive IIR low-pass filter,” IEEE J. Solid-State
[47] Z. Ru, N. A. Moseley, E. A. M. Klumperink, and B. Nauta, “Digitally enhanced software-defined radio receiver robust to out-of-band interfer-ence,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3359–3375, Dec. 2009.
[48] J. Weldon et al., “A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers,” in IEEE Int. Solid-State
Circuits Conf. (ISSCC) Dig. Tech. Papers, 2001, pp. 160–161.
[49] R. Bagheri et al., “An 800-MHz–6-GHz software-defined wireless receiver in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2860–2875, Dec. 2006.
[50] T. Forbes, W. G. Ho, and R. Gharpurey, “Design and analysis of harmonic rejection mixers with programmable LO frequency,” IEEE J. Solid-State
Circuits, vol. 48, no. 10, pp. 2363–2374, Oct. 2013.
[51] Z. Ru, E. A. M. Klumperink, and B. Nauta, “Discrete-time mixing receiver architecture for RF-sampling software-defined radio,” IEEE J.
Solid-State Circuits, vol. 45, no. 9, pp. 1732–1745, Sep. 2010.
[52] H. Darabi, “Highly integrated and tunable RF front-ends for reconfig-urable multi-band transceivers,” Proc. IEEE Custom Integr. Circuits Conf.
(CICC), 2010.
[53] A. Mirzaei and H. Darabi, “Analysis of imperfections on performance of 4-phase passive-mixer-based high-Q bandpass filters in SAW-less receivers,” IEEE Trans. Circuits Syst. I, vol. 58, no. 5, pp. 879–892, 2011. [54] A. Mirzaei, S. Chehrazi, and R. Bagheri, and A. A. Abidi, “Analysis of
first-order anti-aliasing integration sampler,” IEEE Trans. Circuits Syst. I, vol. 55, no. 10, pp. 2994–3005, 2008.
[55] H. Khatri, P. S. Gudem, and L. E. Larson, “Distortion in current com-mutating passive CMOS downconversion mixers,” IEEE Trans. Microw.
Theory Techn., vol. 57, no. 11, pp. 2671–2681, 2009.
[56] H. Zhang and E. Sánchez-Sinencio, “Linearization techniques for CMOS low noise amplifiers: A tutorial,” IEEE Trans. Circuits Syst. I, vol. 58, no. 1, pp. 22–36, 2011.
[57] I. Madadi, M. Tohidian, and R. B. Staszewski, “A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28 nm CMOS,” in Proc. Symp. VLSI Circuits, 2015.
Iman Madadi (S’08–M’15) received the B.S. degree from K. N. Toosi University of Technology, Tehran, Iran, in 2007, the M.S. degree from the University of Tehran, Tehran, Iran, in 2010, and the Ph.D. degree from Delft University of Technology, Delft, The Netherlands, in 2015, all in electrical engineering.
From 2013 to 2014, he was a Consultant at M4S/Hisilicon, Leuven, Belgium, where he designed a 28-nm SAW-less receiver chip for mobile phones. Since February 2015, he has been the Cofounder and CTO of Qualinx B.V., Delft, The Netherlands. He holds six patents and patent applications in the field of RF-CMOS design. His research interests include analog and RF IC design for wireless communications.
Massoud Tohidian (S’08–M’15) received the B.Sc. and M.Sc. degrees in electrical engineering (with Hons.) from Ferdowsi University of Mashhad, Mashhad, Iran, and the University of Tehran, Tehran, Iran, in 2007 and 2010, respectively, and the Ph.D. degree (cum laude) from Delft University of Technology (TU Delft), Delft, The Netherlands, in 2015.
He was a Researcher at IMEP-LAHC Laboratory, Grenoble, France, from 2009 to 2010. He was a Consultant at M4S/Hisilicon, Leuven, Belgium, from 2013 to 2014, designing a 28-nm SAW-less receiver chip for mobile phones. Since February 2015, he has been a Cofounder and CEO of Qualinx B.V., Delft, The Netherlands, developing low-power CMOS wireless chips. He holds seven patents and patent applications in the field of RF-CMOS design. His research interests include RF transceivers, discrete-time/digital signal processing, PLL, and oscillators.
Koen Cornelissens received the M.Sc. degree in electrical engineering from KU Leuven, Leuven, Belgium, in 2004, and the Ph.D. degree from KU Leuven, in 2010, for his work entitled “Delta-Sigma A/D converter design in nanoscale CMOS.”
To conduct the research, he obtained a Ph.D. Fellowship at the Research Foundation–Flanders (FWO). He joined M4S-Huawei, where he is cur-rently working as a Senior Analog Design Engineer on integrated circuits for cellular transceivers.
Patrick Vandenameele received the Ph.D. degree at KU Leuven, Leuven, Belgium.
He has 4 years of research experience at IMEC, Leuven, Belgium, researching the usage of MIMO for WLAN applications. In 2000, he joined Resonext Comunications and found its Belgian R&D centre. In this company and subsequentely after the acquisition by RFMD, he and his team developed 802.11a/b/g solutions, including the world’s first PCI-Express-based WLAN SiP for the PC market and a low-power low-cost SDIO-based WLAN SoC solution for the mobile phone market. He subsequently co-founded or consulted for several new wireless and/or semiconductor ventures, including Rivermark Technology Group (providing soft WiFi IP for embedded systems), Essensium (com-bination of an aggregator-type silicon and embedded SW service business, and a long-term and technologically aggressive product development in the active RF-ID space), Future Waves (fabless semiconductor startup in mobile broadcasting market), and finally M4S (fabless semiconductor startup in cel-lular radio market). In each venture, his role included setting out technology roadmaps, definition and execution of successful semiconductor products, rais-ing venture capital, buildrais-ing teams, and managrais-ing engineerrais-ing organizations. In 2011, M4S was acquired by Huawei, for which he is currently a consultant at HiSilicons wireless R&D centre located in Leuven. He has authored and pre-sented 25+ papers at conferences and in journals, as well as 10+ patents issued or pending of which four are licensed to third parties.
Robert Bogdan Staszewski (M’97–SM’05–F’09) was born in Bialystok, Poland. He received the B.S. degree (summa cum laude) in electrical engineer-ing, the M.S. degree in electrical engineerengineer-ing, and the Ph.D. degree in electrical engineering from the University of Texas at Dallas, Dallas, TX, USA, in 1991, 1992, and 2002, respectively.
From 1991 to 1995, he was with Alcatel Network Systems, Richardson, TX, USA, working on SONET cross-connect systems for fiber optics communica-tions. He joined Texas Instruments, Dallas, TX, USA, in 1995, where he was elected Distinguished Member of Technical Staff (lim-ited to 2% of technical staff). Between 1995 and 1999, he was engaged in advanced CMOS read channel development for hard disk drives. In 1999, he costarted a Digital RF Processor (DRP) Group within Texas Instruments with a mission to invent new digitally intensive approaches to traditional RF functions for integrated radios in deeply-scaled CMOS processes. He was appointed a CTO of the DRP Group between 2007 and 2009. In July 2009, he joined Delft University of Technology, Delft, The Netherlands, where he is currently a part-time Full Professor. Since September 2014, he has been a Professor with the University College Dublin (UCD), Dublin, Ireland. He has authored and co-authored three books, five book chapters, 190 journal and conference publications, and holds 140 issued U.S. patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters, and receivers.
Prof. Staszewski has been a TPC Member of ISSCC, RFIC, ESSCIRC, ISCAS, and RFIT. He is a recipient of the IEEE Circuits and Systems Industrial Pioneer Award.
