74ACT11898

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SCAS144 − OCTOBER 1990 − REVISED APRIL 1993

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265 POST OFFICE BOX 1443

•

HOUSTON, TEXAS 77001

Copyright  1993, Texas Instruments Incorporated

2−1

• Inputs Are TTL-Voltage Compatible

• AND-Gated (Enable/Disable) Serial Inputs

• Fully Buffered Clock and Serial Inputs

• Direct Clear

• Fully Synchronous Data Transfers

• Flow-Through Architecture Optimizes PCB Layout

• Center-Pin V

_CC

and GND Pin Configurations Minimize High-Speed Switching Noise

• ^EPIC  (Enhanced-Performance Implanted CMOS) 1- µ m Process

• 500-mA Typical Latch-Up Immunity at 125 ° C

• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

description

The 74ACT11898 features AND-gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data. A low at either input inhibits entry of new data and resets the first flip-flop to the low level on the rising edge of the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low provided the minimum setup and hold time requirements are met. Clocking occurs on the low-to-high transition of the clock input.

The 74ACT11898 is characterized for operation from − 40 ° C to 85 ° C.

FUNCTION TABLE

INPUTS OUTPUTS

CLR CLK A B QA QB ... QJ

L X X X L L L

H L X X QA0 QB0 QJO

H ↑ H H H QAN QIN

H ↑ L X L QAN QIN

H ↑ X L L QAN QIN

H = high level (steady state)

X = irrelevant (any input, including transitions)

↑ = transition from low to high level

QA0, QB0, QJ0 = the level of QA, QB, QJ respectively, before the indicated steady-state inputconditions were established.

Qn, Qin = the level or QA or QJ before the most recent ↑ transition of the clock; indicates aone-bit shift.t

!"# $ %&'# "$ (&)*%"# +"#',

+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$

$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'

#'$#1 "** (""!'#'$,

EPIC is a trademark of Texas Instruments Incorporated.

DW OR N PACKAGE (TOP VIEW)

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11 Q_C

Q_D Q_E GND GND GND GND Q_F Q_G Q_H

Q_B Q_A CLR A V_CC V_CC B CLK Q_J Q_I

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logic symbol ^† logic diagram (positive logic)

SRG10 13

18

20 1 2 3 8 A 17

14 B

C1/

19

9 10 11 12

&

1D

QA

QB QC QD QE QF QG QH QI QJ CLR

CLK

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

12 QJ QI QH

11 10

QG QF QE

9 8 3

QD QC QB QA

2 1 20 19

CLR CLK B A

18 13 14 17

R C1 1D

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•

2−3

absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ^† Supply voltage range, V

_CC

. . . −0.5 V to 7 V Input voltage range, V

_I

(see Note 1) . . . −0.5 V to V

_CC

+ 0.5 V Output voltage range, V

_O

(see Note 1) . . . −0.5 V to V

_CC

+ 0.5 V

Input clamp current, I

_IK

(V

_I

< 0 or V

_I

> V

_CC

) . . . ± 20 mA Output clamp current, I

_OK

(V

_O

< 0 or V

_O

> V

_CC

) . . . ± 50 mA Continuous output current, I

_O

(V

_O

= 0 to V

_CC

) . . . ± 50 mA Continuous current through V

_CC

or GND . . . ± 250 mA

Storage temperature range . . . −65 ° C to 150 ° C

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

recommended operating conditions (see Note 2)

MIN MAX UNIT

VCC Supply voltage 4.5 5.5 V

VIH High-level input voltage 2 V

VIL Low-level input voltage 0.8 V

VI Input voltage 0 VCC V

VO Output voltage 0 VCC V

IOH High-level output current − 24 mA

IOL Low-level output current 24 mA

Dt/Dv Input transition rise or fall rate 0 10 ns/ V

TA Operating free-air temperature − 40 85 °C

NOTE 2: Unused or floating inputs must be held high or low.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC TA = 25°C

PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX UNIT

IOH = − 50 A

4.5 V 4.4 4.4

IOH = − 50 mA

5.5 V 5.4 5.4

VOH IOH = − 24 mA

4.5 V 3.94 3.8 V

VOH IOH = − 24 mA 5.5 V 4.94 4.8

V

IOH = − 75 mA‡ 5.5 V 3.85

IOL = 50 A 4.5 V 0.1 0.1

IOL = 50 mA

5.5 V 0.1 0.1

VOL IOL = 24 mA

4.5 V 0.36 0.44 V

VOL IOL = 24 mA 5.5 V 0.36 0.44

V

IOL = 75 mA‡ 5.5 V 1.65

IOZ VO = VCC or GND 5.5 V ±0.5 ±5 mA

II VI = VCC or GND 5.5 V ±0.1 ±1 mA

ICC VI = VCC or GND, IO = 0 5.5 V 8 80 mA

DICC§ One input at 3.4 V,

5.5 V 0.9 1 mA

DICC§ One input at 3.4 V,

Other inputs at GND or VCC 5.5 V 0.9 1 mA

Ci VI = VCC or GND 5 V 4 pF

‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.

§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC.

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timing requirements over recommended operating free-air temperature range, V _CC = 5 V _± 0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER TA = 25°C

MIN MAX UNIT PARAMETER

MIN MAX MIN MAX UNIT

fclock Clock frequency 0 40 0 40 ns

tw Pulse duration CLR low 4.5 4.5

tw Pulse duration ns

CLK high or low 12.5 12.5 ns

tsu Setup time before CLK↑ Data 10 10

tsu Setup time before CLK↑ CLR inactive 1.5 1.5 nsns

th Hold time, data after CLK↑ 0 0 ns

switching characteristics over recommended operating free-air temperature range, V _CC = 5 V _± 0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER FROM TO TA = 25°C

PARAMETER FROM

(INPUT)

TO

(OUTPUT) MIN TYP MAX MIN MAX UNIT

fmax 20 65 40 MHz

tPHL CLR Any Q 4.6 6.7 11.1 3.8 12.1 ns

tPLH CLK Any Q 4.1 5.5 8.8 2.7 9.7

tPHL CLK Any Q ns

4.4 6.3 9.4 3.1 10.6 ns

operating characteristics, V _CC = 5 V, T _A = 25 _° C

PARAMETER TEST CONDITIONS TYP UNIT

Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 117 pF

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•

2−5

PARAMETER MEASUREMENT INFORMATION

50% VCC 1.5 V

1.5 V 1.5 V

3 V

3 V 0 V

0 V th

tsu

VOLTAGE WAVEFORMS Data Input

tPLH

tPHL

tPLH VOH

VOH VOL

VOL 1.5 V 1.5 V

3 V

0 V

50% VCC 50% VCC

Input (see Note B)

Out-of-Phase Output In-Phase

Output Timing Input

(see Note B)

50% VCC

VOLTAGE WAVEFORMS

3 V

0 V

1.5 V 1.5 V

tw

VOLTAGE WAVEFORMS Input

LOAD CIRCUIT From Output

Under Test

CL = 50 pF

(see Note A) 500 Ω

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.

C. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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PACKAGING INFORMATION

Orderable Device Status⁽¹⁾ Package Type

Package Drawing

Pins Package Qty

Eco Plan⁽²⁾ Lead/Ball Finish MSL Peak Temp⁽³⁾

74ACT11898DW OBSOLETE SOIC DW 20 TBD Call TI Call TI

(1)The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 30-Mar-2005

Addendum-Page 1

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