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BUZ32-CHIP

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rz 7 SGS-THOMSON

#™ * ® © [ iL i( g r a * S BUZ32 CHIP

N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR IN DIE FORM

• DIE SIZE: 156x 156 mils

• METALLIZATION:

Top Al

Back A u /C r/N i/A u

• BACKSIDE THICKNESS: 6100 A

• DIETHICKNESS: 16 ± 2 mils

• PASSIVATION: P-Vapox

• BONDING PAD SIZE:

Source 40 x 34 mils

Gate 1 5 x 1 9 mils

• RECOMMENDED WIRE BONDING:

Source Al - max 10 mils

Gate Al - max 7 mils

V DSS ^ D S (on) d*

200 V 0.4 fi 9.5 A

N-channel enhancement mode POWER MOS field effect transistor. Easy drive and very fast switching times make this POWER MOS ideal for high speed switching applications.

Die geometry

SOURCE

■ GATE

Drain on backside

MC-0074

* With R,h><; max. 1.67°C/W

June 1988 1/2

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B U Z 3 2 C H IP

GUARANTEED PROBED ELECTRICAL CHARACTERISTICS (Tj = 25°C, Note 1)

Parameters Test Conditions Min. Typ. Max. Unit

V(BR) d s s Drain-source breakdown voltage

lD= 250 ij.A VGS= 0 200 V

lDss Zero gate voltage drain current

VDS= Max Rating

VDS = Max Rating x 0.8 Tf = 125°C

250 1000

fA fA

lGSS Gate-body leakage current

VGS= ± 2 0 V 100 nA

VGs (th) Gate threshold voltage

Vds = VGs Id = 1 mA 2.1 4 V

R Ds (on) Static drain-source on resistance

VGS= 1 0 V lD = 1 A 0.4

NOTES: 1 - Due to probe testing limitations dc parameters only are tested. They are measured using pulse techni­

ques: pulse width <300 fts, duty cycle <2%

2 - For detailed device characteristics please refer to the discrete device datasheet

57

SCS-THOMSON M W SM M W Offi*

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