Pełen tekst

(1)

AMC7820

SBAS231B – MARCH 2002

DESCRIPTION

The AMC7820 is a complete analog monitoring and control circuit that includes an 8-channel, 12-bit Analog-to-Digital Converter (ADC), three 12-bit Digital-to-Analog Converters (DACs), nine operational amplifiers, a thermistor current source, an internal +2.5V reference, and an SPI serial interface.

External reference may be applied. Typical power dissipation is 40mW. For the ADC, the unbuffered analog input range is 0V to +5.0V, and the buffered analog common-mode input range is 0V to +3.8V. For the DACs, the analog output range is 0V to +2.5V or 0V to +5.0V.

The AMC7820 is ideal for multichannel applications where low power and small size are critical. The AMC7820 is available in a TQFP-48 package and is fully specified and tested over the –40°C to +85°C temperature range.

SPI is a trademark of Motorola.

FEATURES

100kHz SAMPLING RATE 12-BIT ADC

8 ANALOG INPUT CHANNELS

THREE 12-BIT DACS

NINE OPERATIONAL AMPLIFIERS

THERMISTOR CURRENT SOURCE

INTERNAL 2.5V REFERENCE

SPI SERIAL INTERFACE

3V LOGIC COMPATIBLE

SINGLE +5V SUPPLY

LOW POWER: 40mW

TQFP-48 PACKAGE

ANALOG MONITORING AND CONTROL

APPLICATIONS

CW LASER AND PUMP LASER CURRENT CONTROL IN DWDM

TEC COOLER CURRENT CONTROL IN DWDM

OPTICAL POWER MONITORING

TUNABLE LASER

AMC7820

ADC 12-Bit ADC/DAC

Current Source up to 1mA

5 Precision OPAs

External Reference

2.5V Output

DAC2 SPI

Interface and Control

DAC1 DAC0 AMC7820

Reference (2.5V) 8-Channel MUX

(2)

ELECTRICAL CHARACTERISTICS

At –40°C to +85°C, AVDD, DVDD, BVDD = +5V, using external 2.5V reference, unless otherwise noted.

ABSOLUTE MAXIMUM RATINGS

(1)

AVDD, DVDD, BVDD to GND ... –0.3V to +6V Digital Input Voltage to GND ... –0.3V to BVDD + 0.3V Analog Input Voltage to GND ... –0.3V to AVDD + 0.3V Input Current: Continuous ...±20mA Momentary ...±100mA Operating Temperature Range ... –40°C to +105°C Storage Temperature Range ... –65°C to +150°C Junction Temperature (TJ Max) ... +150°C TQFP Package

Power Dissipation ... (TJ Max – TA)/θJA

θJC Thermal Impedance ... 15°C/W θJA Thermal Impedance ... 60°C/W Lead Temperature (soldering)

Vapor Phase (60s) ... +220°C Infrared (15s) ... +220°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

SPECIFIED SPECIFIED

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY

AMC7820Y TQFP-48 PFB –40°C to +85°C AMC7820Y AMC7820Y/250 Tape and Reel, 250

AMC7820Y “ “ “ AMC7820Y AMC7820Y/2K Tape and Reel, 2000

PACKAGE/ORDERING INFORMATION

PARAMETER CONDITION MIN TYP MAX UNITS

ADC ANALOG INPUTS(1) Channels 2-5

Input Voltage Range 0 2 • VREF V

Input Impedance 5 MΩ

Input Capacitance 15 pF

Input Leakage Current ±1 µA

ADC

Resolution 12 Bits

No Missing Codes 12 Bits

Integral Linearity ±1 ±2 LSB(2)

Differential Linearity ±1 LSB

Offset Error ±2 ±5 LSB

Offset Error Drift ±4 ppm/°C

Offset Error Match Channels 2-5 0.5 1 LSB

Gain Error ±0.3 ±1.5 %

Gain Error Match Channels 2-5 0.3 1 LSB

Noise 150 µVrms

Power-Supply Rejection +AVDD, +DVDD = +5V ±5% 1.2 LSB

Throughput Rate 100 kHz

Total Conversion Time Scan All 8 Channels 80 µs

DAC(3)

Output Voltage Range DAC_OUT_SET Connected to DAC_OUT 0 VREF V

DAC_OUT_SET = AGND 0 2 • VREF V

Output Current Refer to the Characteristic Curves ±1 mA

Resolution 12 Bits

Integral Linearity(4) ±4 ±8 LSB

Monotonicity 12 Bits

Differential Linearity ±0.1 ±1 LSB

Offset Error Output Range 0 – VREF ±0.5 ±5 mV

Output Range 0 – 2 • VREF ±1 ±10 mV

Offset Error Drift ±4 ppm/°C

Gain Error Output Range = 0V to 2 • VREF or 0V to VREF ±0.3 ±1.5 %

Settling Time Step Between Codes 1024 and 2048 3 µs

Code Change Glitch Impulse 1LSB Change Around Major Carry 20 nV-s

THERMISTOR CURRENT SOURCE

Output Current Range 10 100 1000 µA

Output Current Accuracy RISET = 100kΩ 98 102 µA

Output Impedance RISET = 100kΩ 500 MΩ

Compliance Voltage 0 3 V

Power-Supply Rejection Ratio 60 dB

AMC7820 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

(3)

ELECTRICAL CHARACTERISTICS (Cont.)

At –40°C to +85°C, AVDD, DVDD, BVDD = +5V, using external 2.5V reference, unless otherwise noted.

PARAMETER CONDITION MIN TYP MAX UNITS

AMC7820

VOLTAGE REFERENCE (VREF)

Internal Reference Voltage 2.45 2.50 2.55 V

Internal Reference Drift(5) 0°C to +85°C ±10 ppm/°C

–40°C to +85°C ±30 ppm/°C

2.5V Output Impedance (pin 26) 0.5

2.5V Output Current (pin 26) ±1 mA

Short-Circuit Current (pin 26) ±15 mA

External Reference Voltage Range (pin 27) 2.45 2.50 2.55 V

External Reference Input Resistance 10 kΩ

External Reference Input Capacitance 5 pF

OP AMP CHARACTERISTICS(6)

Input Offset Voltage ±0.5 ±4 mV

vs Temperature ±2 µV/°C

vs Power Supply 50 µV/V

Input Bias Current(7) TA = +25°C ±2 ±50 pA

TA = –40°C to +85°C See Typical Characteristics

Input Offset Current(7) TA = +25°C ±1 ±50 pA

Input Voltage Noise f = 0.1Hz to 10Hz 6 µVp-p

Input Voltage Noise Density f = 1kHz 26 nV/√Hz

Current Noise Density f = 1kHz 0.6 fA/√Hz

Common-Mode Voltage Range –0.2 AVDD – 1.2 V

Common-Mode Rejection Ratio(8) –0.2V < VCM < AVDD – 1.2V 74 90 dB

Open-Loop Gain(8) RL = 25kΩ, 125mV < VO < AVDD – 125mV 100 120 dB

Gain-Bandwidth Product G = 1 3 MHz

Slew Rate G = 1 1.2 V/µs

Settling Time: 0.1% 2V Step, CL = 100pF, G = 1, RL = 10kΩ 3 µs

Voltage Output Swing from Rail RL = 25kΩ 40 mV

Closed-Loop Output Impedance 0.4

Output Current See Typical Characteristics ±1 mA

Short-Circuit Current ±18 mA

DIGITAL INPUT/OUTPUT Logic Level:

VIH BVDD = 5V, |IIH| ≤ 10µA 3.5 BVDD + 0.3 V

VIL BVDD = 5V, |IIL| ≤ 10µA 0 0.8 V

VOH BVDD = 5V, IOH = –3mA 4.0 BVDD V

VOL BVDD = 5V, IOL = 3mA 0 0.4 V

Logic Level:

VIH BVDD = 3V, |IIH| ≤ 10µA 2.1 BVDD + 0.3 V

VIL BVDD = 3V, |IIL| ≤ 10µA 0 0.6 V

VOH BVDD = 3V, IOH = –3mA 2.4 BVDD V

VOL BVDD = 3V, IOL = 3mA 0 0.4 V

Input Capacitance 5 pF

POWER-SUPPLY REQUIREMENTS Power-Supply Voltage

AVDD, DVDD Specified Performance 4.75 5 5.25 V

BVDD Specified Performance 2.7 5.25 V

Quiescent Current of AVDD 8 12 mA

Quiescent Current of DVDD 0.3 0.75 mA

Quiescent Current of BVDD 0.01 0.1 mA

Power Dissipation 40 mW

TEMPERATURE RANGE

Specified Performance –40 +85 °C

Storage –65 +150 °C

NOTES: (1) For channels 2-5, fed into MUX directly. (2) LSB means Least Significant Bit. (3) DACs are tested without output load. (4) Measured from code 010 to FFF. (5) Internal reference voltage has been optimized for lowest drift from 0°C to +85°C. (6) Applies to all amplifiers; see Figure 2. (7) Offset current will double for each 10°C of temperature increase. See Operational Amplifier section. (8) Ensured by design.

(4)

PIN CONFIGURATION

Top View TQFP

24 23 22 21 20 19 18 17 16 15 14 13 37

38 39 40 41 42 43 44 45 46 47 48

36 35 34 33 32 31 30 29 28 27 26

1 2 3 4 5 6 7 8 9 10 11

25

12

AMC7820

RESET CH2 CH3 CH4 CH5 OPA1_IN OPA1_OUT OPA1_IN+ SW1_OUT EXT_REF_IN REF_OUT_+2.5V OPA3_IN+

OPA3_OUT OPA3_IN–

DAC1_OUT DAC1_OUT_SET DAC2_OUT_SET AVDD

AGND DAC2_OUT OPA4_IN+

OPA4_OUT OPA4_IN–

OPA5_IN+

SCLK MOSI MISO SS BVDD DVDD DGND THERM_I_OUTPUT ISET_RESISTOR OPA7_IN–

OPA7_OUT OPA7_IN+

SW2_OUT T_SENSOR_VOLTAGE OPA6_IN OPA6_OUT OPA6_IN+ DAC0_OUT DAC0_OUT_SET OPA2_IN OPA2_OUT OPA2_IN+ OPA5_IN OPA5_OUT

(5)

PIN DESIGNATOR DESCRIPTION

1 SW2_OUT Output from SW2. This pin connects to OPA7_OUT when SW2 is enabled; connects to the output of SW3 when SW2 is disabled.

2 T_SENSOR_VOLTAGE Output of temperature sensor (Thermistor) voltage buffer.

3 OPA6_IN– Inverting Input of OPA6

4 OPA6_OUT Output of OPA6

5 OPA6_IN+ Noninverting Input of OPA6

6 DAC0_OUT Output of DAC0

7 DAC0_OUT_SET This pin determines the full-scale output of DAC0. When tied to DAC0_OUT, the full-scale output equals VREF. When connected to AGND, full-scale output equals 2 • VREF.

8 OPA2_IN– Inverting Input of OPA2

9 OPA2_OUT Output of OPA2

10 OPA2_IN+ Noninverting Input of OPA2 11 OPA5_IN– Inverting Input of OPA5

12 OPA5_OUT Output of OPA5

13 OPA5_IN+ Noninverting Input of OPA5 14 OPA4_IN– Inverting Input of OPA4

15 OPA4_OUT Output of OPA4

16 OPA4_IN+ Noninverting Input of OPA4

17 DAC2_OUT Output of DAC2

18 AGND Analog Ground

19 AVDD Analog Power Supply (+5V)

20 DAC2_OUT_SET This pin determines the full-scale output of DAC2. When tied to DAC2_OUT, the full-scale output equals VREF. When connected to AGND, full-scale output equals 2 • VREF.

21 DAC1_OUT_SET This pin determines the full-scale output of DAC1. When tied to DAC1_OUT, the full-scale output equals VREF. When connected to AGND, full-scale output equals 2 • VREF.

22 DAC1_OUT Output of DAC1

23 OPA3_IN– Inverting Input of OPA3

24 OPA3_OUT Output of OPA3

25 OPA3_IN+ Noninverting Input of OPA3 26 REF_OUT_+2.5V +2.5VOUT

27 EXT_REF_IN An external reference can be connected here. Also can be used as a filter for internal reference.

28 SW1_OUT Output from SW1. This pin connects to DAC2_OUT when SW1 is enabled; connects to AGND when SW1 is disabled.

29 OPA1_IN+ Noninverting Input of OPA1

30 OPA1_OUT Output of OPA1

31 OPA1_IN– Inverting Input of OPA1

32 CH5 Analog Input of Channel 5

33 CH4 Analog Input of Channel 4

34 CH3 Analog Input of Channel 3

35 CH2 Analog Input of Channel 2

36 RESET Reset Input. Logic LOW on this pin will cause the part to perform a hardware reset.

37 SCLK Serial Clock Input

38 MOSI Master Out, Slave In. Digital data input for the serial interface.

39 MISO Master In, Slave Out. Digital data output for the serial interface.

40 SS Slave Select Input (active LOW). Data will not be clocked into MOSI unless SS is LOW. When SS is HIGH, MISO is high impedance.

41 BVDD Interface Power Supply. Connects to 3V for 3V logic; connects to 5V for 5V logic.

42 DVDD Digital Power Supply (+5V)

43 DGND Digital Ground

44 THERM_I_OUTPUT Current source output to drive the thermistor.

45 ISET_RESISTOR The resistor connected to this pin sets the current output from the pin THERM_I_OUTPUT.

46 OPA7_IN– Inverting Input of OPA7

47 OPA7_OUT Output of OPA7

48 OPA7_IN+ Noninverting Input of OPA7

PIN DESCRIPTIONS (Refer to Figure 1, Block Diagram)

(6)

TIMING CHARACTERISTICS

At –40°C to +85°C, +AVDD = +DVDD = +5V, VREF = +2.5V, +BVDD = +5V, unless otherwise noted.

PARAMETER SYMBOL MIN MAX UNITS

SCLK Period tSCK 30 ns

SCLK HIGH or LOW Time tWSCK 15 ns

Rise Time tR 30 ns

Fall Time tF 30 ns

Enable Lead Time tLEAD 15 ns

Enable Lag Time tLAG 15 ns

Sequential Transfer Delay tTD 30 ns

Data Setup Time tSU 10 ns

Data Hold Time (inputs) tHI 10 ns

Slave Access Time tA 15 ns

Data Valid tV 10 ns

Data Hold Time (outputs) tHO 0 ns

Slave MISO Disable Time tDIS 15 ns

TIMING CHARACTERISTICS

At –40°C to +85°C, +AVDD = +DVDD = +5V, VREF = +2.5V, +BVDD = +3V, unless otherwise noted.

PARAMETER SYMBOL MIN MAX UNITS

SCLK Period tSCK 40 ns

SCLK HIGH or LOW Time tWSCK 20 ns

Rise Time tR 30 ns

Fall Time tF 30 ns

Enable Lead Time tLEAD 15 ns

Enable Lag Time tLAG 15 ns

Sequential Transfer Delay tTD 30 ns

Data Setup Time tSU 10 ns

Data Hold Time (inputs) tHI 10 ns

Slave Access Time tA 15 ns

Data Valid tV 15 ns

Data Hold Time (outputs) tHO 0 ns

Slave MISO Disable Time tDIS 15 ns

TIMING DIAGRAM

tTD

tR

tLAG

tF

tV

tA Hi-Z

tHO tDIS

tSCK tWSCK tWSCK tLEAD

tSU tHI SS

SCLK

MOSI

MISO

Command BIT 15 (MSB)

Command BIT 14 . . . 1

Command BIT 0 (LSB)

DATA IN BIT 15 (MSB)

DATA IN BIT 14 . . . 1

DATA IN BIT 0 (LSB)

DATA OUT BIT 15 (MSB)

DATA OUT BIT 14 . . . 1

DATA OUT BIT 0 (LSB) WRITE COMMAND FROM THE HOST

WRITE OPERATION

DATA WRITTEN INTO AMC7820’s REGISTERS

Previous value of register N before writing operation. NOTE: If SS is HIGH, MISO is in Hi-Z.

tTD

tR

tLAG

tF

tV

tA Hi-Z

tHO tDIS

tSCK tWSCK tWSCK tLEAD

tSU tHI SS

SCLK

MOSI

MISO

Command BIT 15 (MSB) Don’t

Care

Command BIT 14 . . . 1

Command BIT 0 (LSB)

Don’t Care

DATA OUT BIT 15 (MSB)

DATA OUT BIT 14 . . . 1

DATA OUT BIT 0 (LSB) READ COMMAND FROM THE HOST

READ OPERATION DATA READ FROM AMC7820’s REGISTERS NOTE: If SS is HIGH, MISO is in Hi-Z.

(7)

TYPICAL CHARACTERISTICS: ADC

At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted.

2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0

LE (LSB)

LINEARITY ERROR vs CODE (–40°C)

0 512 1024 1536 2048 Code

2560 3072 3584 4096 2.0

1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0

DLE (LSB)

2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0

LE (LSB)

LINEARITY ERROR vs CODE (+25°C)

0 512 1024 1536 2048 Code

2560 3072 3584 4096 2.0

1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0

DLE (LSB)

2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0

LE (LSB)

LINEARITY ERROR vs CODE (+85°C)

0 512 1024 1536 2048 Code

2560 3072 3584 4096 2.0

1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0

DLE (LSB)

OFFSET vs TEMPERATURE (Internal or External Reference)

Temperature (°C)

Delta from +25°C (LSB)

1.0

0.5

0.0

–0.5

–1.0

–50 –25 0 25 50 75 100

GAIN ERROR vs TEMPERATURE

Temperature (°C)

Delta from +25°C (%)

0.40

0.20

0.00

–0.20

–0.40

–0.60

–0.80

–50 –25 0 25 50 75 100

With 2.5V External Reference

With 2.5V Internal Reference

CHANNEL-TO-CHANNEL MATCH vs TEMPERATURE (Unbuffered Channels 2, 3, 4, 5)

Temperature (°C)

Delta from +25°C (LSB)

0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00

–50 –25 0 25 50 75 100

Offset Error Match

Gain Error Match

(8)

TYPICAL CHARACTERISTICS: ADC (Cont.)

At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted.

GAIN ERROR, OFFSET ERROR, INTERNAL VREF vs AVDD SUPPLY VOLTAGE

(Unbuffered Channels)

Supply Voltge, AVDD (V)

4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25

Gain Error, Internal VREF Delta from AVDD = 5V (%) Offset Error Delta from AVDD = 5V (LSB)

0.030 0.025 0.020 0.015 0.010 0.005 0.000 –0.005 –0.010 –0.015 –0.020

0.300 0.250 0.200 0.150 0.100 0.050 0.000 –0.050 –0.100 –0.150 –0.200 Offset

Internal VREF

Gain

40 35 30 25 20 15 10 5 0

POWER-SUPPLY REJECTION vs FREQUENCY

AVDD Ripple Frequency (Hz)

Power-Supply Rejection (mV/V)

100 1k 10k 100k 1M

10

INTERNAL REFERENCE VOLTAGE vs TEMPERATURE

Temperature (°C)

Delta from +25°C (mV)

10

5

0

–5

–10

–15

–20

–50 –25 0 25 50 75 100

INTERNAL 2.5V REFERENCE DISTRIBUTION

Internal Reference Voltage (V)

Percent of Units (%)

25

20

15

10

5

0

2.450 2.455 2.460 2.465 2.470 2.475 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 2.525 2.530 2.535 2.540 2.545 2.550

(9)

TYPICAL CHARACTERISTICS: DACs (DAC0, DAC1, DAC2)

At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted.

8 6 4 2 0 –2 –4 –6 –8

LE (LSB)

LINEARITY ERROR vs CODE (–40°C)

0 512 1024 1536 2048 Code

2560 3072 3584 4096 1.00.8

0.60.4 0.20 –0.2–0.4 –0.6–0.8 –1.0

DLE (LSB)

8 6 4 2 0 –2 –4 –6 –8

LE (LSB)

LINEARITY ERROR vs CODE (+25°C)

0 512 1024 1536 2048 Code

2560 3072 3584 4096 1.00.8

0.60.4 0.20 –0.2–0.4 –0.6–0.8 –1.0

DLE (LSB)

8 6 4 2 0 –2 –4 –6 –8

LE (LSB)

LINEARITY ERROR vs CODE (+85°C)

0 512 1024 1536 2048 Code

2560 3072 3584 4096 1.00.8

0.60.4 0.20 –0.2–0.4 –0.6–0.8 –1.0

DLE (LSB)

OFFSET ERROR vs TEMPERATURE

Temperature (°C)

Delta from +25°C (mV)

2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0

–50 –25 0 25 50 75 100

Gain = +2

Gain = +1

GAIN ERROR vs TEMPERATURE (DAC Gain = +1 or +2)

Temperature (°C)

Delta from +25°C (%)

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–50 –25 0 25 50 75 100

Ext 2.5V Ref Int 2.5V Ref

OUTPUT VOLTAGE vs OUTPUT CURRENT, GAIN = +1

Output Current Magnitude (mA)

Output Voltage Sinking Current (V) Output Voltage Sourcing Current (V)

5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0

2.5000 2.4995 2.4990 2.4985 2.4980 2.4975 2.4970 2.4965 2.4960 2.4955 2.4950

0 1 2 3 4 5 6 7

Sourcing Current DAC at FFFH

Sinking Current DAC at 008H

(10)

TYPICAL CHARACTERISTICS: DACs (DAC0, DAC1, DAC2) (Cont.)

At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted.

OUTPUT VOLTAGE vs OUTPUT CURRENT, GAIN = +2

Output Current Magnitude (mA)

Output Voltage (V)

5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0

0 1 2 3 4 5 6 7

Sourcing Current DAC at FFFH

Sinking Current DAC at 008H

SETTLING TIME, GAIN = +2

Time (2µs/div)

Output (500mV/div) Settling Detail (1LSB/div)

Code 2048

Settling Detail

Code 1024 CL = 10pF RL = 20kΩ

POWER-ON RESET TO 0V

Time (20µs/div)

1V/div

DAC Resets to 000H 5V

AVDD, DVDD, Reset Pin

0V 0V

TYPICAL CHARACTERISTICS: Thermistor Current Source (THERM IOUT, Pin 2)

At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted.

THERM_I_OUTPUT vs TEMPERATURE

Temperature (°C)

Delta from +25°C (µA)

0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0

–50 –25 0 25 50 75 100

Ext 2.5V Ref Int 2.5V Ref

THERM_I_OUTPUT vs COMPLIANCE VOLTAGE

Compliance Voltage (V)

Delta from 10µA and 100µA (nA) Delta from 1mA (µA)

10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100

10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

10µA Nominal

100µA Nominal 1mA Nominal

(11)

TYPICAL CHARACTERISTICS: Thermistor Current Source (THERM IOUT, Pin 2) (Cont.)

At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted.

TYPICAL CHARACTERISTICS: Operational Amplifiers

At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted.

INPUT BIAS CURRENT vs TEMPERATURE

Input Bias Current (pA)

100.0

10.0

1.0

INPUT BIAS CURRENT vs INPUT COMMON-MODE VOLTAGE

Delta from Mid-Supply (pA)

2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 OFFSET VOLTAGE DISTRIBUTION

Percent of Amplifiers (%)

Offset Voltage (mV)

2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

20 18 16 14 12 10 8 6 4 2 0

OFFSET VOLTAGE DRIFT DISTRIBUTION

Percent of Amplifiers (%)

Offset Voltage Drift (µV/°C) 18

16 14 12 10 8 6 4 2 0

6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

THERM IOUT CURRENT DISTRIBUTION WITH INTERNAL VOLTAGE REFERENCE

Therm IOUT (µA)

Percent of Units (%)

25

20

15

10

5

0

98.0 98.2 98.4 98.6 98.8 99.0 99.2 99.4 99.6 99.8 100.0 100.2 100.4 100.6 100.8 101.0 101.2 101.4 101.6 101.8 102.0

RISET = 100kΩ

THERM IOUT CURRENT DISTRIBUTION WITH EXTERNAL VOLTAGE REFERENCE

Therm IOUT (µA)

Percent of Units (%)

25

20

15

10

5

0

98.0 98.2 98.4 98.6 98.8 99.0 99.2 99.4 99.6 99.8 100.0 100.2 100.4 100.6 100.8 101.0 101.2 101.4 101.6 101.8 102.0

RISET = 100kΩ

(12)

TYPICAL CHARACTERISTICS: Operational Amplifiers (Cont.)

At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted.

INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY

Frequency (Hz)

Voltage Noise (nVHz)

1k

100

10

1

0.1

1k

100

10

1

0.1

1 10 100 1k 10k 100k 1M

Current Noise (fAHz)

Voltage Noise

Current Noise

OP AMP OUTPUT VOLTAGE vs INPUT VOLTAGE

Input Voltage (V)

Output Voltage (V)

5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 0.01 0.005 0

0 0.0050.01 1.5 2 2.5 3 3.5 4 4.5 5 Common-

Mode Input Range is Exceeded

VOUTPUT Clamps at +5mV

For 0.01V < VINPUT < 3.8V CMRR > 74dB

Input

Output G= +1

OPEN-LOOP GAIN/PHASE vs FREQUENCY

Frequency (Hz)

Open-Loop Gain (dB) Phase (°)

160 140 120 100 80 60 40 20 0 –20

1 10 100 1k 10k 100k 1M 10M

G

φ

0

–45

–90

–135

–180

AOL, CMRR, PSRR vs TEMPERATURE

AOL, CMRR (dB) PSRR (dB)

140

130

120

110

100

90

80

130

120

110

100

90

80

70 PSRR

CMRR

Temperature (°C)

–50 –25 0 25 50 75 100

AOL

POWER-SUPPLY REJECTION RATIO AND COMMON-MODE REJECTION RATIO vs FREQUENCY

Frequency (Hz)

PSRR, CMRR (dB)

100 90 80 70 60 50 40 30 20 10

1 10 100 1k 10k 100k 1M 10M

+PSRR

CMRR

SMALL-SIGNAL STEP RESPONSE G = 1, CL = 100pF

Time (1µs/div)

Op Amp Output (50mV/div)

(13)

TYPICAL CHARACTERISTICS: Operational Amplifiers (Cont.)

At TA = +25°C, +AVDD, BVDD = +5.0V, VREF = Internal +2.5V, unless otherwise noted.

LARGE-SIGNAL STEP RESPONSE AND SETTLING TIME CL = 100pF, Gain = +1

Time (2µs/div)

Op Amp Output (500mV/div) Output Settling Detail (0.2%/div)

2.1V

0.1V

Output Settling Detail Op Amp Output

LARGE-SIGNAL STEP RESPONSE AND SETTLING TIME CL = 100pF, Gain = +1

Time (2µs/div)

Op Amp Output (500mV/div) Output Settling Detail (0.2%/div)

2.1V

0.1V

Output Settling Detail

Op Amp Output

SETTLING TIME vs CLOSED-LOOP GAIN

Closed-Loop Gain (V/V)

Settling Time (µs)

100

10

1

1 10 100 1k

0.01%

0.1%

SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE

Load Capacitance (pF)

Overshoot (%)

60

50

40

30

20

10

0

10 100 1k 10k

(G = ±1)

(G = ±10)

OUTPUT VOLTAGE SWING FROM SUPPLY RAILS vs OUTPUT CURRENT

Output Current Magnitude (mA)

Output Voltage (V)

5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0

0 1 2 3 4 5 6 7 8

Sinking Current Sourcing Current

(14)

OVERVIEW

The AMC7820 is an analog monitoring and control circuit for control of laser diodes and TEC coolers in DWDM applica- tions. A register-based architecture eases integration with DSP-based (or microprocessor-based) systems through a standard SPI bus. All peripheral functions are controlled through the registers and onboard state machines.

The AMC7820 consists of the following blocks (refer to the block diagram of Figure 2):

• 8-Channel, 12-Bit ADC

• Three 12-Bit DACs

• Nine Operational Amplifiers

• +2.5V Reference

• TEC Soft Start Controller

Communication to the AMC7820 is via a standard SPI serial interface. This interface requires that SS, the Slave Select signal, be driven LOW to communicate with the AMC7820.

The data is then shifted into and out of the AMC7820 under control of the host DSP or microprocessor, which also provides the serial data clock.

Control of the AMC7820 and its functions is accomplished by writing to different registers in the AMC7820. A simple com- mand protocol is used to address the 16-bit registers. Regis- ters control the operation of the ADC, DACs, and device configuration. The results of measurements made are placed in the memory map and can be read by the host at any time.

All pins have ESD protection circuitry as the first active element on the chip. All input and output pins have protection diodes connected to supply and ground that remain reverse biased under normal operation. If the input voltages exceed the absolute maximum voltage range, it is necessary to add resistance in series with the input to limit the current to 10mA or less.

ADC

The analog inputs are provided via a multiplexer to the Successive Approximation Register (SAR) ADC. The ADC architecture is based on capacitive redistribution architecture that inherently includes a sample-and-hold function.

The multiplexer provides eight analog input channels to the ADC. Channels 0, 1, 6, and 7 are buffered by amplifiers OPA3, OPA4, OPA5, and OPA6, respectively. Channels 2, 3, 4, and 5 connect directly to external pins. The multiplexer connects each analog input to the ADC sequentially. Analog current into the device must charge the internal sample- and-hold capacitor during the sampling period. When the converter is in Hold mode, and the sampling capacitor has been fully charged, the input impedance of the analog input is greater than 1GΩ.

The on resistance of each multiplexer switch is typically 150Ω. In order to charge the internal sample-and-hold ca- pacitor completely during the acquisition time, the source impedance of the analog input should be no more than 1kΩ. The ADC runs continuously upon start-up, scanning through each channel. The results of conversions made are stored in the appropriate ADC registers.

Since the input range of the ADC is 2 • VREF, codes near FFF will be missing if the output range of the signal source driving an ADC input channel is limited to less than 2 • VREF. This is the case for channels 0, 1, 6, and 7 which are driven from internal op amps which have an output range limit of AVDD. If all codes including FFF are required, the value of the reference voltage must be reduced or the value of AVDD must be increased.

Data Format

The AMC7820 output data is in Straight Binary format, as shown in Figure 1. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise.

DACS

The three 12-bit DACs of the AMC7820 use a resistor-string architecture with switchable taps that are buffered by an operational amplifier (see DAC0 in Figure 4). Each op amp buffer can be configured for a gain of +1 or +2, which sets the output range to 0V to +2.5V or 0V to +5.0V, respectively. This architecture is inherently monotonic, a critical requirement for any system requiring “smooth” setpoint control.

The op amp buffer has a rail-to-rail output stage that has limitations on sinking or sourcing current when the output voltage is near AGND or AVDD, respectively (see the typical characteristics). For example, if a DAC (Gain = +1) is set to code 010H (+10mV) and is required to sink 1mA of current, the DAC output voltage will be approximately 250mV instead of the desired value of +10mV.

This problem is solved by restricting the DAC output voltage to values greater than +250mV or by reducing the required sink current. This restriction does not apply for the case of sourcing current for gain set at +1. When the gain is set at +2, there is a limitation on sourcing current with the output voltage near the positive supply rail.

The slope of the DAC output voltage curve for sinking or sourcing current is due to an increase in the inherent closed- loop output impedance of the operational amplifier buffer, when operating near a supply rail. Refer to the typical characteristic curves.

FIGURE 1. Ideal Input Voltage and Output Codes.

Output Code

0V

FS = Full-Scale Voltage = 2VREF 1LSB = 2VREF/4096

FS – 1LSB 11...111

11...110 11...101

00...010 00...001 00...000

1LSB

Input Voltage (V)

(15)

DAC1 (12 Bits)

DAC2 (12 Bits)

DAC0 (12 Bits)

MUX ADC

(12 Bits)

Clock MUX

CTL Reference

(2.5V)

SPI and Registers

R R

R R

Current Mirror 1:4

OPA8

2.5V

DAC1_OUT_SET 21

22

20 17

29

30 28

31 10

9

8

25

24

23

27

26

15

14

16

35 34 33 32 12

11

13 0

1

2 3 4 5

6

7

6 7 4

3

5

48 47

1

46

2

44 45

DAC1_OUT

DAC2_OUT_SET

DAC2_OUT

OPA1_IN+

OPA1_OUT SW1_OUT

OPA1_IN–

OPA2_IN+

OPA2_OUT

OPA2_IN–

OPA3_IN+

OPA3_OUT

OPA3_IN–

EXT_REF_IN

REF_OUT_+2.5V

OPA4_OUT

OPA4_IN–

OPA4_IN+

CH2 CH3 CH4 CH5 OPA5_OUT

OPA5_IN–

OPA5_IN+

DAC0_OUT DAC0_OUT_SET OPA6_OUT

OPA6_IN–

OPA6_IN+

OPA7_IN+

OPA7_OUT

SW2_OUT

OPA7_IN–

T_SENSOR_VOLTAGE

THERM_I_OUTPUT ISET_RESISTOR OPA4

OPA3 OPA2 OPA1

OPA5

OPA6

SW2_DISABLE

EN DIS Unipolar_Bipolar_CTR

“1” = SW2 Disable

Bip Uni SW3

SW2 DIS SW1

OPA7

OPA9 R

R 37

38 39 40 36 SCLK MOSI MISO SS RESET

19

18

42

43

41 AVDD

AGND

DVDD

DGND

BVDD

NOTE: After power-on or reset, SW1 and SW2 are disabled, SW3 is positioned to Bip, SW4 is on, and the voltage on pin 47 equals 2.5V (VREF) if OPA7 is connected as an integrator.

TEC Soft-Start Controller EN

ON OFF

SOFT_START_ENABLE SOFT_START_CTR = “1”

After Reset

SW4

SW1_DISABLE

“1” = Disable

Obraz

Updating...

Powiązane tematy :